1ARM Virtual Generic Interrupt Controller (VGIC) 2=============================================== 3 4Device types supported: 5 KVM_DEV_TYPE_ARM_VGIC_V2 ARM Generic Interrupt Controller v2.0 6 KVM_DEV_TYPE_ARM_VGIC_V3 ARM Generic Interrupt Controller v3.0 7 8Only one VGIC instance may be instantiated through either this API or the 9legacy KVM_CREATE_IRQCHIP api. The created VGIC will act as the VM interrupt 10controller, requiring emulated user-space devices to inject interrupts to the 11VGIC instead of directly to CPUs. 12 13Creating a guest GICv3 device requires a host GICv3 as well. 14GICv3 implementations with hardware compatibility support allow a guest GICv2 15as well. 16 17Groups: 18 KVM_DEV_ARM_VGIC_GRP_ADDR 19 Attributes: 20 KVM_VGIC_V2_ADDR_TYPE_DIST (rw, 64-bit) 21 Base address in the guest physical address space of the GIC distributor 22 register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V2. 23 This address needs to be 4K aligned and the region covers 4 KByte. 24 25 KVM_VGIC_V2_ADDR_TYPE_CPU (rw, 64-bit) 26 Base address in the guest physical address space of the GIC virtual cpu 27 interface register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V2. 28 This address needs to be 4K aligned and the region covers 4 KByte. 29 30 KVM_VGIC_V3_ADDR_TYPE_DIST (rw, 64-bit) 31 Base address in the guest physical address space of the GICv3 distributor 32 register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V3. 33 This address needs to be 64K aligned and the region covers 64 KByte. 34 35 KVM_VGIC_V3_ADDR_TYPE_REDIST (rw, 64-bit) 36 Base address in the guest physical address space of the GICv3 37 redistributor register mappings. There are two 64K pages for each 38 VCPU and all of the redistributor pages are contiguous. 39 Only valid for KVM_DEV_TYPE_ARM_VGIC_V3. 40 This address needs to be 64K aligned. 41 42 43 KVM_DEV_ARM_VGIC_GRP_DIST_REGS 44 Attributes: 45 The attr field of kvm_device_attr encodes two values: 46 bits: | 63 .... 40 | 39 .. 32 | 31 .... 0 | 47 values: | reserved | vcpu_index | offset | 48 49 All distributor regs are (rw, 32-bit) 50 51 The offset is relative to the "Distributor base address" as defined in the 52 GICv2 specs. Getting or setting such a register has the same effect as 53 reading or writing the register on the actual hardware from the cpu whose 54 index is specified with the vcpu_index field. Note that most distributor 55 fields are not banked, but return the same value regardless of the 56 vcpu_index used to access the register. 57 Limitations: 58 - Priorities are not implemented, and registers are RAZ/WI 59 - Currently only implemented for KVM_DEV_TYPE_ARM_VGIC_V2. 60 Errors: 61 -ENXIO: Getting or setting this register is not yet supported 62 -EBUSY: One or more VCPUs are running 63 -EINVAL: Invalid vcpu_index supplied 64 65 KVM_DEV_ARM_VGIC_GRP_CPU_REGS 66 Attributes: 67 The attr field of kvm_device_attr encodes two values: 68 bits: | 63 .... 40 | 39 .. 32 | 31 .... 0 | 69 values: | reserved | vcpu_index | offset | 70 71 All CPU interface regs are (rw, 32-bit) 72 73 The offset specifies the offset from the "CPU interface base address" as 74 defined in the GICv2 specs. Getting or setting such a register has the 75 same effect as reading or writing the register on the actual hardware. 76 77 The Active Priorities Registers APRn are implementation defined, so we set a 78 fixed format for our implementation that fits with the model of a "GICv2 79 implementation without the security extensions" which we present to the 80 guest. This interface always exposes four register APR[0-3] describing the 81 maximum possible 128 preemption levels. The semantics of the register 82 indicate if any interrupts in a given preemption level are in the active 83 state by setting the corresponding bit. 84 85 Thus, preemption level X has one or more active interrupts if and only if: 86 87 APRn[X mod 32] == 0b1, where n = X / 32 88 89 Bits for undefined preemption levels are RAZ/WI. 90 91 Limitations: 92 - Priorities are not implemented, and registers are RAZ/WI 93 - Currently only implemented for KVM_DEV_TYPE_ARM_VGIC_V2. 94 Errors: 95 -ENXIO: Getting or setting this register is not yet supported 96 -EBUSY: One or more VCPUs are running 97 -EINVAL: Invalid vcpu_index supplied 98 99 KVM_DEV_ARM_VGIC_GRP_NR_IRQS 100 Attributes: 101 A value describing the number of interrupts (SGI, PPI and SPI) for 102 this GIC instance, ranging from 64 to 1024, in increments of 32. 103 104 Errors: 105 -EINVAL: Value set is out of the expected range 106 -EBUSY: Value has already be set, or GIC has already been initialized 107 with default values. 108 109 KVM_DEV_ARM_VGIC_GRP_CTRL 110 Attributes: 111 KVM_DEV_ARM_VGIC_CTRL_INIT 112 request the initialization of the VGIC, no additional parameter in 113 kvm_device_attr.addr. 114 Errors: 115 -ENXIO: VGIC not properly configured as required prior to calling 116 this attribute 117 -ENODEV: no online VCPU 118 -ENOMEM: memory shortage when allocating vgic internal data 119