1An Intel MIC X100 device is a PCIe form factor add-in coprocessor 2card based on the Intel Many Integrated Core (MIC) architecture 3that runs a Linux OS. It is a PCIe endpoint in a platform and therefore 4implements the three required standard address spaces i.e. configuration, 5memory and I/O. The host OS loads a device driver as is typical for 6PCIe devices. The card itself runs a bootstrap after reset that 7transfers control to the card OS downloaded from the host driver. The 8host driver supports OSPM suspend and resume operations. It shuts down 9the card during suspend and reboots the card OS during resume. 10The card OS as shipped by Intel is a Linux kernel with modifications 11for the X100 devices. 12 13Since it is a PCIe card, it does not have the ability to host hardware 14devices for networking, storage and console. We provide these devices 15on X100 coprocessors thus enabling a self-bootable equivalent environment 16for applications. A key benefit of our solution is that it leverages 17the standard virtio framework for network, disk and console devices, 18though in our case the virtio framework is used across a PCIe bus. 19 20MIC PCIe card has a dma controller with 8 channels. These channels are 21shared between the host s/w and the card s/w. 0 to 3 are used by host 22and 4 to 7 by card. As the dma device doesn't show up as PCIe device, 23a virtual bus called mic bus is created and virtual dma devices are 24created on it by the host/card drivers. On host the channels are private 25and used only by the host driver to transfer data for the virtio devices. 26 27The Symmetric Communication Interface (SCIF (pronounced as skiff)) is a 28low level communications API across PCIe currently implemented for MIC. 29More details are available at scif_overview.txt. 30 31The Coprocessor State Management (COSM) driver on the host allows for 32boot, shutdown and reset of Intel MIC devices. It communicates with a COSM 33"client" driver on the MIC cards over SCIF to perform these functions. 34 35Here is a block diagram of the various components described above. The 36virtio backends are situated on the host rather than the card given better 37single threaded performance for the host compared to MIC, the ability of 38the host to initiate DMA's to/from the card using the MIC DMA engine and 39the fact that the virtio block storage backend can only be on the host. 40 41 | 42 +----------+ | +----------+ 43 | Card OS | | | Host OS | 44 +----------+ | +----------+ 45 | 46 +-------+ +--------+ +------+ | +---------+ +--------+ +--------+ 47 | Virtio| |Virtio | |Virtio| | |Virtio | |Virtio | |Virtio | 48 | Net | |Console | |Block | | |Net | |Console | |Block | 49 | Driver| |Driver | |Driver| | |backend | |backend | |backend | 50 +-------+ +--------+ +------+ | +---------+ +--------+ +--------+ 51 | | | | | | | 52 | | | |User | | | 53 | | | |------|------------|---------|------- 54 +-------------------+ |Kernel +--------------------------+ 55 | | | Virtio over PCIe IOCTLs | 56 | | +--------------------------+ 57+-----------+ | | | +-----------+ 58| MIC DMA | | +------+ | +------+ +------+ | | MIC DMA | 59| Driver | | | SCIF | | | SCIF | | COSM | | | Driver | 60+-----------+ | +------+ | +------+ +--+---+ | +-----------+ 61 | | | | | | | | 62+---------------+ | +------+ | +--+---+ +--+---+ | +----------------+ 63|MIC virtual Bus| | |SCIF | | |SCIF | | COSM | | |MIC virtual Bus | 64+---------------+ | |HW Bus| | |HW Bus| | Bus | | +----------------+ 65 | | +------+ | +--+---+ +------+ | | 66 | | | | | | | | 67 | +-----------+---+ | | | +---------------+ | 68 | |Intel MIC | | | | |Intel MIC | | 69 +---|Card Driver | | | | |Host Driver | | 70 +------------+--------+ | +----+---------------+-----+ 71 | | | 72 +-------------------------------------------------------------+ 73 | | 74 | PCIe Bus | 75 +-------------------------------------------------------------+ 76