1NVIDIA Tegra20 SFLASH controller.
2
3Required properties:
4- compatible : should be "nvidia,tegra20-sflash".
5- reg: Should contain SFLASH registers location and length.
6- interrupts: Should contain SFLASH interrupts.
7- clocks : Must contain one entry, for the module clock.
8  See ../clocks/clock-bindings.txt for details.
9- resets : Must contain an entry for each entry in reset-names.
10  See ../reset/reset.txt for details.
11- reset-names : Must include the following entries:
12  - spi
13- dmas : Must contain an entry for each entry in clock-names.
14  See ../dma/dma.txt for details.
15- dma-names : Must include the following entries:
16  - rx
17  - tx
18
19Recommended properties:
20- spi-max-frequency: Definition as per
21                     Documentation/devicetree/bindings/spi/spi-bus.txt
22
23Example:
24
25spi@7000c380 {
26	compatible = "nvidia,tegra20-sflash";
27	reg = <0x7000c380 0x80>;
28	interrupts = <0 39 0x04>;
29	spi-max-frequency = <25000000>;
30	#address-cells = <1>;
31	#size-cells = <0>;
32	clocks = <&tegra_car 43>;
33	resets = <&tegra_car 43>;
34	reset-names = "spi";
35	dmas = <&apbdma 11>, <&apbdma 11>;
36	dma-names = "rx", "tx";
37	status = "disabled";
38};
39