1MediaTek display PWM controller 2 3Required properties: 4 - compatible: should be "mediatek,<name>-disp-pwm": 5 - "mediatek,mt8173-disp-pwm": found on mt8173 SoC. 6 - "mediatek,mt6595-disp-pwm": found on mt6595 SoC. 7 - reg: physical base address and length of the controller's registers. 8 - #pwm-cells: must be 2. See pwm.txt in this directory for a description of 9 the cell format. 10 - clocks: phandle and clock specifier of the PWM reference clock. 11 - clock-names: must contain the following: 12 - "main": clock used to generate PWM signals. 13 - "mm": sync signals from the modules of mmsys. 14 - pinctrl-names: Must contain a "default" entry. 15 - pinctrl-0: One property must exist for each entry in pinctrl-names. 16 See pinctrl/pinctrl-bindings.txt for details of the property values. 17 18Example: 19 pwm0: pwm@1401e000 { 20 compatible = "mediatek,mt8173-disp-pwm", 21 "mediatek,mt6595-disp-pwm"; 22 reg = <0 0x1401e000 0 0x1000>; 23 #pwm-cells = <2>; 24 clocks = <&mmsys CLK_MM_DISP_PWM026M>, 25 <&mmsys CLK_MM_DISP_PWM0MM>; 26 clock-names = "main", "mm"; 27 pinctrl-names = "default"; 28 pinctrl-0 = <&disp_pwm0_pins>; 29 }; 30 31 backlight_lcd: backlight_lcd { 32 compatible = "pwm-backlight"; 33 pwms = <&pwm0 0 1000000>; 34 brightness-levels = < 35 0 16 32 48 64 80 96 112 36 128 144 160 176 192 208 224 240 37 255 38 >; 39 default-brightness-level = <9>; 40 power-supply = <&mt6397_vio18_reg>; 41 enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>; 42 }; 43