1NVIDIA Tegra210 pinmux controller
2
3Required properties:
4- compatible: "nvidia,tegra210-pinmux"
5- reg: Should contain a list of base address and size pairs for:
6  - first entry: The APB_MISC_GP_*_PADCTRL registers (pad control)
7  - second entry: The PINMUX_AUX_* registers (pinmux)
8
9Please refer to pinctrl-bindings.txt in this directory for details of the
10common pinctrl bindings used by client devices, including the meaning of the
11phrase "pin configuration node".
12
13Tegra's pin configuration nodes act as a container for an arbitrary number of
14subnodes. Each of these subnodes represents some desired configuration for a
15pin, a group, or a list of pins or groups. This configuration can include the
16mux function to select on those pin(s)/group(s), and various pin configuration
17parameters, such as pull-up, tristate, drive strength, etc.
18
19The name of each subnode is not important; all subnodes should be enumerated
20and processed purely based on their content.
21
22Each subnode only affects those parameters that are explicitly listed. In
23other words, a subnode that lists a mux function but no pin configuration
24parameters implies no information about any pin configuration parameters.
25Similarly, a pin subnode that describes a pullup parameter implies no
26information about e.g. the mux function or tristate parameter. For this
27reason, even seemingly boolean values are actually tristates in this binding:
28unspecified, off, or on. Unspecified is represented as an absent property,
29and off/on are represented as integer values 0 and 1.
30
31See the TRM to determine which properties and values apply to each pin/group.
32Macro values for property values are defined in
33include/dt-binding/pinctrl/pinctrl-tegra.h.
34
35Required subnode-properties:
36- nvidia,pins : An array of strings. Each string contains the name of a pin or
37    group. Valid values for these names are listed below.
38
39Optional subnode-properties:
40- nvidia,function: A string containing the name of the function to mux to the
41    pin or group.
42- nvidia,pull: Integer, representing the pull-down/up to apply to the pin.
43    0: none, 1: down, 2: up.
44- nvidia,tristate: Integer.
45    0: drive, 1: tristate.
46- nvidia,enable-input: Integer. Enable the pin's input path.
47    enable :TEGRA_PIN_ENABLE0 and
48    disable or output only: TEGRA_PIN_DISABLE.
49- nvidia,open-drain: Integer.
50    enable: TEGRA_PIN_ENABLE.
51    disable: TEGRA_PIN_DISABLE.
52- nvidia,lock: Integer. Lock the pin configuration against further changes
53    until reset.
54    enable: TEGRA_PIN_ENABLE.
55    disable: TEGRA_PIN_DISABLE.
56- nvidia,io-hv: Integer. Select high-voltage receivers.
57    normal: TEGRA_PIN_DISABLE
58    high: TEGRA_PIN_ENABLE
59- nvidia,high-speed-mode: Integer. Enable high speed mode the pins.
60    normal: TEGRA_PIN_DISABLE
61    high: TEGRA_PIN_ENABLE
62- nvidia,schmitt: Integer. Enables Schmitt Trigger on the input.
63    normal: TEGRA_PIN_DISABLE
64    high: TEGRA_PIN_ENABLE
65- nvidia,drive-type: Integer. Valid range 0...3.
66- nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest.
67    The range of valid values depends on the pingroup. See "CAL_DRVDN" in the
68    Tegra TRM.
69- nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest.
70    The range of valid values depends on the pingroup. See "CAL_DRVUP" in the
71    Tegra TRM.
72- nvidia,slew-rate-rising: Integer. Controls rising signal slew rate. 0 is
73    fastest. The range of valid values depends on the pingroup. See
74    "DRVDN_SLWR" in the Tegra TRM.
75- nvidia,slew-rate-falling: Integer. Controls falling signal slew rate. 0 is
76    fastest. The range of valid values depends on the pingroup. See
77    "DRVUP_SLWF" in the Tegra TRM.
78
79Valid values for pin and group names (nvidia,pin) are:
80
81  Mux groups:
82
83    These correspond to Tegra PINMUX_AUX_* (pinmux) registers. Any property
84    that exists in those registers may be set for the following pin names.
85
86    In Tegra210, many pins also have a dedicated APB_MISC_GP_*_PADCTRL
87    register. Where that is true, and property that exists in that register
88    may also be set on the following pin names.
89
90    als_prox_int_px3, ap_ready_pv5, ap_wake_bt_ph3, ap_wake_nfc_ph7,
91    aud_mclk_pbb0, batt_bcl, bt_rst_ph4, bt_wake_ap_ph5, button_home_py1,
92    button_power_on_px5, button_slide_sw_py0, button_vol_down_px7,
93    button_vol_up_px6, cam1_mclk_ps0, cam1_pwdn_ps7, cam1_strobe_pt1,
94    cam2_mclk_ps1, cam2_pwdn_pt0, cam_af_en_ps5, cam_flash_en_ps6,
95    cam_i2c_scl_ps2, cam_i2c_sda_ps3, cam_rst_ps4cam_rst_ps4, clk_32k_in,
96    clk_32k_out_py5, clk_req, core_pwr_req, cpu_pwr_req, dap1_din_pb1,
97    dap1_dout_pb2, dap1_fs_pb0, dap1_sclk_pb3, dap2_din_paa2, dap2_dout_paa3,
98    dap2_fs_paa0, dap2_sclk_paa1, dap4_din_pj5, dap4_dout_pj6, dap4_fs_pj4,
99    dap4_sclk_pj7, dmic1_clk_pe0, dmic1_dat_pe1, dmic2_clk_pe2, dmic2_dat_pe3,
100    dmic3_clk_pe4, dmic3_dat_pe5, dp_hpd0_pcc6, dvfs_clk_pbb2, dvfs_pwm_pbb1,
101    gen1_i2c_scl_pj1, gen1_i2c_sda_pj0, gen2_i2c_scl_pj2, gen2_i2c_sda_pj3,
102    gen3_i2c_scl_pf0, gen3_i2c_sda_pf1, gpio_x1_aud_pbb3, gpio_x3_aud_pbb4,
103    gps_en_pi2, gps_rst_pi3, hdmi_cec_pcc0, hdmi_int_dp_hpd_pcc1, jtag_rtck,
104    lcd_bl_en_pv1, lcd_bl_pwm_pv0, lcd_gpio1_pv3, lcd_gpio2_pv4, lcd_rst_pv2,
105    lcd_te_py2, modem_wake_ap_px0, motion_int_px2, nfc_en_pi0, nfc_int_pi1,
106    pa6, pcc7, pe6, pe7, pex_l0_clkreq_n_pa1, pex_l0_rst_n_pa0,
107    pex_l1_clkreq_n_pa4, pex_l1_rst_n_pa3, pex_wake_n_pa2, ph6, pk0, pk1, pk2,
108    pk3, pk4, pk5, pk6, pk7, pl0, pl1, pwr_i2c_scl_py3, pwr_i2c_sda_py4,
109    pwr_int_n, pz0, pz1, pz2, pz3, pz4, pz5, qspi_cs_n_pee1, qspi_io0_pee2,
110    qspi_io1_pee3, qspi_io2_pee4, qspi_io3_pee5, qspi_sck_pee0,
111    sata_led_active_pa5, sdmmc1_clk_pm0, sdmmc1_cmd_pm1, sdmmc1_dat0_pm5,
112    sdmmc1_dat1_pm4, sdmmc1_dat2_pm3, sdmmc1_dat3_pm2, sdmmc3_clk_pp0,
113    sdmmc3_cmd_pp1, sdmmc3_dat0_pp5, sdmmc3_dat1_pp4, sdmmc3_dat2_pp3,
114    sdmmc3_dat3_pp2, shutdown, spdif_in_pcc3, spdif_out_pcc2, spi1_cs0_pc3,
115    spi1_cs1_pc4, spi1_miso_pc1, spi1_mosi_pc0, spi1_sck_pc2, spi2_cs0_pb7,
116    spi2_cs1_pdd0, spi2_miso_pb5, spi2_mosi_pb4, spi2_sck_pb6, spi4_cs0_pc6,
117    spi4_miso_pd0, spi4_mosi_pc7, spi4_sck_pc5, temp_alert_px4, touch_clk_pv7,
118    touch_int_px1, touch_rst_pv6, uart1_cts_pu3, uart1_rts_pu2, uart1_rx_pu1,
119    uart1_tx_pu0, uart2_cts_pg3, uart2_rts_pg2, uart2_rx_pg1, uart2_tx_pg0,
120    uart3_cts_pd4, uart3_rts_pd3, uart3_rx_pd2, uart3_tx_pd1, uart4_cts_pi7,
121    uart4_rts_pi6, uart4_rx_pi5, uart4_tx_pi4, usb_vbus_en0_pcc4,
122    usb_vbus_en1_pcc5, wifi_en_ph0, wifi_rst_ph1, wifi_wake_ap_ph2
123
124  Drive groups:
125
126    These correspond to the Tegra APB_MISC_GP_*_PADCTRL (pad control)
127    registers. Note that where one of these registers controls a single pin
128    for which a PINMUX_AUX_* exists, see the list above for the pin name to
129    use when configuring the pinmux.
130
131    pa6, pcc7, pe6, pe7, ph6, pk0, pk1, pk2, pk3, pk4, pk5, pk6, pk7, pl0, pl1,
132    pz0, pz1, pz2, pz3, pz4, pz5, sdmmc1, sdmmc2, sdmmc3, sdmmc4
133
134Valid values for nvidia,functions are:
135
136    aud, bcl, blink, ccla, cec, cldvfs, clk, core, cpu, displaya, displayb,
137    dmic1, dmic2, dmic3, dp, dtv, extperiph3, i2c1, i2c2, i2c3, i2cpmu, i2cvi,
138    i2s1, i2s2, i2s3, i2s4a, i2s4b, i2s5a, i2s5b, iqc0, iqc1, jtag, pe, pe0,
139    pe1, pmi, pwm0, pwm1, pwm2, pwm3, qspi, rsvd0, rsvd1, rsvd2, rsvd3, sata,
140    sdmmc1, sdmmc3, shutdown, soc, sor0, sor1, spdif, spi1, spi2, spi3, spi4,
141    sys, touch, uart, uarta, uartb, uartc, uartd, usb, vgp1, vgp2, vgp3, vgp4,
142    vgp5, vgp6, vimclk, vimclk2
143
144Example:
145
146	pinmux: pinmux@70000800 {
147		compatible = "nvidia,tegra210-pinmux";
148		reg = <0x0 0x700008d4 0x0 0x2a8>, /* Pad control registers */
149		      <0x0 0x70003000 0x0 0x1000>; /* Mux registers */
150
151		pinctrl-names = "boot";
152		pinctrl-0 = <&state_boot>;
153
154		state_boot: pinmux {
155			gen1_i2c_scl_pj1 {
156				nvidia,pins = "gen1_i2c_scl_pj1",
157				nvidia,function = "i2c1";
158				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
159				nvidia,tristate = <TEGRA_PIN_DISABLE>;
160				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
161				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
162				nvidia,io-hv = <TEGRA_PIN_ENABLE>;
163			};
164		};
165	};
166};
167