1* Allwinner A1X Pin Controller 2 3The pins controlled by sunXi pin controller are organized in banks, 4each bank has 32 pins. Each pin has 7 multiplexing functions, with 5the first two functions being GPIO in and out. The configuration on 6the pins includes drive strength and pull-up. 7 8Required properties: 9- compatible: Should be one of the followings (depending on you SoC): 10 "allwinner,sun4i-a10-pinctrl" 11 "allwinner,sun5i-a10s-pinctrl" 12 "allwinner,sun5i-a13-pinctrl" 13 "allwinner,sun6i-a31-pinctrl" 14 "allwinner,sun6i-a31s-pinctrl" 15 "allwinner,sun6i-a31-r-pinctrl" 16 "allwinner,sun7i-a20-pinctrl" 17 "allwinner,sun8i-a23-pinctrl" 18 "allwinner,sun8i-a23-r-pinctrl" 19 "allwinner,sun8i-a33-pinctrl" 20 "allwinner,sun8i-a83t-pinctrl" 21 22- reg: Should contain the register physical address and length for the 23 pin controller. 24 25Please refer to pinctrl-bindings.txt in this directory for details of the 26common pinctrl bindings used by client devices. 27 28A pinctrl node should contain at least one subnodes representing the 29pinctrl groups available on the machine. Each subnode will list the 30pins it needs, and how they should be configured, with regard to muxer 31configuration, drive strength and pullups. If one of these options is 32not set, its actual value will be unspecified. 33 34Required subnode-properties: 35 36- allwinner,pins: List of strings containing the pin name. 37- allwinner,function: Function to mux the pins listed above to. 38 39Optional subnode-properties: 40- allwinner,drive: Integer. Represents the current sent to the pin 41 0: 10 mA 42 1: 20 mA 43 2: 30 mA 44 3: 40 mA 45- allwinner,pull: Integer. 46 0: No resistor 47 1: Pull-up resistor 48 2: Pull-down resistor 49 50Examples: 51 52pio: pinctrl@01c20800 { 53 compatible = "allwinner,sun5i-a13-pinctrl"; 54 reg = <0x01c20800 0x400>; 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 uart1_pins_a: uart1@0 { 59 allwinner,pins = "PE10", "PE11"; 60 allwinner,function = "uart1"; 61 allwinner,drive = <0>; 62 allwinner,pull = <0>; 63 }; 64 65 uart1_pins_b: uart1@1 { 66 allwinner,pins = "PG3", "PG4"; 67 allwinner,function = "uart1"; 68 allwinner,drive = <0>; 69 allwinner,pull = <0>; 70 }; 71}; 72 73 74GPIO and interrupt controller 75----------------------------- 76 77This hardware also acts as a GPIO controller and an interrupt 78controller. 79 80Consumers that would want to refer to one or the other (or both) 81should provide through the usual *-gpios and interrupts properties a 82cell with 3 arguments, first the number of the bank, then the pin 83inside that bank, and finally the flags for the GPIO/interrupts. 84 85Example: 86 87xio: gpio@38 { 88 compatible = "nxp,pcf8574a"; 89 reg = <0x38>; 90 91 gpio-controller; 92 #gpio-cells = <2>; 93 94 interrupt-parent = <&pio>; 95 interrupts = <6 0 IRQ_TYPE_EDGE_FALLING>; 96 interrupt-controller; 97 #interrupt-cells = <2>; 98}; 99 100reg_usb1_vbus: usb1-vbus { 101 compatible = "regulator-fixed"; 102 regulator-name = "usb1-vbus"; 103 regulator-min-microvolt = <5000000>; 104 regulator-max-microvolt = <5000000>; 105 gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; 106}; 107