1Xilinx Axi CAN/Zynq CANPS controller Device Tree Bindings
2---------------------------------------------------------
3
4Required properties:
5- compatible		: Should be "xlnx,zynq-can-1.0" for Zynq CAN
6			  controllers and "xlnx,axi-can-1.00.a" for Axi CAN
7			  controllers.
8- reg			: Physical base address and size of the Axi CAN/Zynq
9			  CANPS registers map.
10- interrupts		: Property with a value describing the interrupt
11			  number.
12- interrupt-parent	: Must be core interrupt controller
13- clock-names		: List of input clock names - "can_clk", "pclk"
14			  (For CANPS), "can_clk" , "s_axi_aclk"(For AXI CAN)
15			  (See clock bindings for details).
16- clocks		: Clock phandles (see clock bindings for details).
17- tx-fifo-depth		: Can Tx fifo depth.
18- rx-fifo-depth		: Can Rx fifo depth.
19
20
21Example:
22
23For Zynq CANPS Dts file:
24	zynq_can_0: can@e0008000 {
25			compatible = "xlnx,zynq-can-1.0";
26			clocks = <&clkc 19>, <&clkc 36>;
27			clock-names = "can_clk", "pclk";
28			reg = <0xe0008000 0x1000>;
29			interrupts = <0 28 4>;
30			interrupt-parent = <&intc>;
31			tx-fifo-depth = <0x40>;
32			rx-fifo-depth = <0x40>;
33		};
34For Axi CAN Dts file:
35	axi_can_0: axi-can@40000000 {
36			compatible = "xlnx,axi-can-1.00.a";
37			clocks = <&clkc 0>, <&clkc 1>;
38			clock-names = "can_clk","s_axi_aclk" ;
39			reg = <0x40000000 0x10000>;
40			interrupt-parent = <&intc>;
41			interrupts = <0 59 1>;
42			tx-fifo-depth = <0x40>;
43			rx-fifo-depth = <0x40>;
44		};
45