1Broadcom BCM3380-style Level 1 / Level 2 interrupt controller
2
3This interrupt controller shows up in various forms on many BCM338x/BCM63xx
4chipsets.  It has the following properties:
5
6- outputs a single interrupt signal to its interrupt controller parent
7
8- contains one or more enable/status word pairs, which often appear at
9  different offsets in different blocks
10
11- no atomic set/clear operations
12
13Required properties:
14
15- compatible: should be "brcm,bcm3380-l2-intc"
16- reg: specifies one or more enable/status pairs, in the following format:
17  <enable_reg 0x4 status_reg 0x4>...
18- interrupt-controller: identifies the node as an interrupt controller
19- #interrupt-cells: specifies the number of cells needed to encode an interrupt
20  source, should be 1.
21- interrupt-parent: specifies the phandle to the parent interrupt controller
22  this one is cascaded from
23- interrupts: specifies the interrupt line in the interrupt-parent controller
24  node, valid values depend on the type of parent interrupt controller
25
26Optional properties:
27
28- brcm,irq-can-wake: if present, this means the L2 controller can be used as a
29  wakeup source for system suspend/resume.
30
31Example:
32
33irq0_intc: interrupt-controller@10000020 {
34	compatible = "brcm,bcm3380-l2-intc";
35	reg = <0x10000024 0x4 0x1000002c 0x4>,
36	      <0x10000020 0x4 0x10000028 0x4>;
37	interrupt-controller;
38	#interrupt-cells = <1>;
39	interrupt-parent = <&cpu_intc>;
40	interrupts = <2>;
41};
42