1* TI - TSC ADC (Touschscreen and analog digital converter) 2~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3 4Required properties: 5- child "tsc" 6 ti,wires: Wires refer to application modes i.e. 4/5/8 wire touchscreen 7 support on the platform. 8 ti,x-plate-resistance: X plate resistance 9 ti,coordinate-readouts: The sequencer supports a total of 16 10 programmable steps each step is used to 11 read a single coordinate. A single 12 readout is enough but multiple reads can 13 increase the quality. 14 A value of 5 means, 5 reads for X, 5 for 15 Y and 2 for Z (always). This utilises 12 16 of the 16 software steps available. The 17 remaining 4 can be used by the ADC. 18 ti,wire-config: Different boards could have a different order for 19 connecting wires on touchscreen. We need to provide an 20 8 bit number where in the 1st four bits represent the 21 analog lines and the next 4 bits represent positive/ 22 negative terminal on that input line. Notations to 23 represent the input lines and terminals resoectively 24 is as follows: 25 AIN0 = 0, AIN1 = 1 and so on till AIN7 = 7. 26 XP = 0, XN = 1, YP = 2, YN = 3. 27- child "adc" 28 ti,adc-channels: List of analog inputs available for ADC. 29 AIN0 = 0, AIN1 = 1 and so on till AIN7 = 7. 30 31Optional properties: 32- child "tsc" 33 ti,charge-delay: Length of touch screen charge delay step in terms of 34 ADC clock cycles. Charge delay value should be large 35 in order to avoid false pen-up events. This value 36 effects the overall sampling speed, hence need to be 37 kept as low as possible, while avoiding false pen-up 38 event. Start from a lower value, say 0x400, and 39 increase value until false pen-up events are avoided. 40 The pen-up detection happens immediately after the 41 charge step, so this does in fact function as a 42 hardware knob for adjusting the amount of "settling 43 time". 44 45- child "adc" 46 ti,chan-step-opendelay: List of open delays for each channel of 47 ADC in the order of ti,adc-channels. The 48 value corresponds to the number of ADC 49 clock cycles to wait after applying the 50 step configuration registers and before 51 sending the start of ADC conversion. 52 Maximum value is 0x3FFFF. 53 ti,chan-step-sampledelay: List of sample delays for each channel 54 of ADC in the order of ti,adc-channels. 55 The value corresponds to the number of 56 ADC clock cycles to sample (to hold 57 start of conversion high). 58 Maximum value is 0xFF. 59 ti,chan-step-avg: Number of averages to be performed for each 60 channel of ADC. If average is 16 then input 61 is sampled 16 times and averaged to get more 62 accurate value. This increases the time taken 63 by ADC to generate a sample. Valid range is 0 64 average to 16 averages. Maximum value is 16. 65 66Example: 67 tscadc: tscadc@44e0d000 { 68 compatible = "ti,am3359-tscadc"; 69 tsc { 70 ti,wires = <4>; 71 ti,x-plate-resistance = <200>; 72 ti,coordiante-readouts = <5>; 73 ti,wire-config = <0x00 0x11 0x22 0x33>; 74 ti,charge-delay = <0x400>; 75 }; 76 77 adc { 78 ti,adc-channels = <4 5 6 7>; 79 ti,chan-step-opendelay = <0x098 0x3ffff 0x098 0x0>; 80 ti,chan-step-sampledelay = <0xff 0x0 0xf 0x0>; 81 ti,chan-step-avg = <16 2 4 8>; 82 }; 83 } 84