1Xilinx Zynq FPGA Manager
2
3Required properties:
4- compatible:		should contain "xlnx,zynq-devcfg-1.0"
5- reg:			base address and size for memory mapped io
6- interrupts:		interrupt for the FPGA manager device
7- clocks:		phandle for clocks required operation
8- clock-names:		name for the clock, should be "ref_clk"
9- syscon:		phandle for access to SLCR registers
10
11Example:
12	devcfg: devcfg@f8007000 {
13		compatible = "xlnx,zynq-devcfg-1.0";
14		reg = <0xf8007000 0x100>;
15		interrupts = <0 8 4>;
16		clocks = <&clkc 12>;
17		clock-names = "ref_clk";
18		syscon = <&slcr>;
19	};
20