1Qualcomm adreno/snapdragon display controller
2
3Required properties:
4- compatible:
5  * "qcom,mdp" - mdp4
6- reg: Physical base address and length of the controller's registers.
7- interrupts: The interrupt signal from the display controller.
8- connectors: array of phandles for output device(s)
9- clocks: device clocks
10  See ../clocks/clock-bindings.txt for details.
11- clock-names: the following clocks are required:
12  * "core_clk"
13  * "iface_clk"
14  * "src_clk"
15  * "hdmi_clk"
16  * "mpd_clk"
17
18Optional properties:
19- gpus: phandle for gpu device
20- clock-names: the following clocks are optional:
21  * "lut_clk"
22
23Example:
24
25/ {
26	...
27
28	mdp: qcom,mdp@5100000 {
29		compatible = "qcom,mdp";
30		reg = <0x05100000 0xf0000>;
31		interrupts = <GIC_SPI 75 0>;
32		connectors = <&hdmi>;
33		gpus = <&gpu>;
34		clock-names =
35		    "core_clk",
36		    "iface_clk",
37		    "lut_clk",
38		    "src_clk",
39		    "hdmi_clk",
40		    "mdp_clk";
41		clocks =
42		    <&mmcc MDP_SRC>,
43		    <&mmcc MDP_AHB_CLK>,
44		    <&mmcc MDP_LUT_CLK>,
45		    <&mmcc TV_SRC>,
46		    <&mmcc HDMI_TV_CLK>,
47		    <&mmcc MDP_TV_CLK>;
48	};
49};
50