1Qualcomm adreno/snapdragon hdmi output
2
3Required properties:
4- compatible: one of the following
5   * "qcom,hdmi-tx-8996"
6   * "qcom,hdmi-tx-8994"
7   * "qcom,hdmi-tx-8084"
8   * "qcom,hdmi-tx-8974"
9   * "qcom,hdmi-tx-8660"
10   * "qcom,hdmi-tx-8960"
11- reg: Physical base address and length of the controller's registers
12- reg-names: "core_physical"
13- interrupts: The interrupt signal from the hdmi block.
14- clocks: device clocks
15  See ../clocks/clock-bindings.txt for details.
16- qcom,hdmi-tx-ddc-clk-gpio: ddc clk pin
17- qcom,hdmi-tx-ddc-data-gpio: ddc data pin
18- qcom,hdmi-tx-hpd-gpio: hpd pin
19- core-vdda-supply: phandle to supply regulator
20- hdmi-mux-supply: phandle to mux regulator
21
22Optional properties:
23- qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin
24- qcom,hdmi-tx-mux-sel-gpio: hdmi mux select pin
25- power-domains: reference to the power domain(s), if available.
26- pinctrl-names: the pin control state names; should contain "default"
27- pinctrl-0: the default pinctrl state (active)
28- pinctrl-1: the "sleep" pinctrl state
29
30Example:
31
32/ {
33	...
34
35	hdmi: qcom,hdmi-tx-8960@4a00000 {
36		compatible = "qcom,hdmi-tx-8960";
37		reg-names = "core_physical";
38		reg = <0x04a00000 0x1000>;
39		interrupts = <GIC_SPI 79 0>;
40		power-domains = <&mmcc MDSS_GDSC>;
41		clock-names =
42		    "core_clk",
43		    "master_iface_clk",
44		    "slave_iface_clk";
45		clocks =
46		    <&mmcc HDMI_APP_CLK>,
47		    <&mmcc HDMI_M_AHB_CLK>,
48		    <&mmcc HDMI_S_AHB_CLK>;
49		qcom,hdmi-tx-ddc-clk = <&msmgpio 70 GPIO_ACTIVE_HIGH>;
50		qcom,hdmi-tx-ddc-data = <&msmgpio 71 GPIO_ACTIVE_HIGH>;
51		qcom,hdmi-tx-hpd = <&msmgpio 72 GPIO_ACTIVE_HIGH>;
52		core-vdda-supply = <&pm8921_hdmi_mvs>;
53		hdmi-mux-supply = <&ext_3p3v>;
54		pinctrl-names = "default", "sleep";
55		pinctrl-0 = <&hpd_active  &ddc_active  &cec_active>;
56		pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>;
57	};
58};
59