1* ARM PrimeCell Color LCD Controller PL110/PL111
2
3See also Documentation/devicetree/bindings/arm/primecell.txt
4
5Required properties:
6
7- compatible: must be one of:
8	"arm,pl110", "arm,primecell"
9	"arm,pl111", "arm,primecell"
10
11- reg: base address and size of the control registers block
12
13- interrupt-names: either the single entry "combined" representing a
14	combined interrupt output (CLCDINTR), or the four entries
15	"mbe", "vcomp", "lnbu", "fuf" representing the individual
16	CLCDMBEINTR, CLCDVCOMPINTR, CLCDLNBUINTR, CLCDFUFINTR interrupts
17
18- interrupts: contains an interrupt specifier for each entry in
19	interrupt-names
20
21- clock-names: should contain "clcdclk" and "apb_pclk"
22
23- clocks: contains phandle and clock specifier pairs for the entries
24	in the clock-names property. See
25	Documentation/devicetree/binding/clock/clock-bindings.txt
26
27Optional properties:
28
29- memory-region: phandle to a node describing memory (see
30	Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
31	to be used for the framebuffer; if not present, the framebuffer
32	may be located anywhere in the memory
33
34- max-memory-bandwidth: maximum bandwidth in bytes per second that the
35	cell's memory interface can handle; if not present, the memory
36	interface is fast enough to handle all possible video modes
37
38Required sub-nodes:
39
40- port: describes LCD panel signals, following the common binding
41	for video transmitter interfaces; see
42	Documentation/devicetree/bindings/media/video-interfaces.txt;
43	when it is a TFT panel, the port's endpoint must define the
44	following property:
45
46	- arm,pl11x,tft-r0g0b0-pads: an array of three 32-bit values,
47		defining the way CLD pads are wired up; first value
48		contains index of the "CLD" external pin (pad) used
49		as R0 (first bit of the red component), second value
50	        index of the pad used as G0, third value index of the
51		pad used as B0, see also "LCD panel signal multiplexing
52		details" paragraphs in the PL110/PL111 Technical
53		Reference Manuals; this implicitly defines available
54		color modes, for example:
55		- PL111 TFT 4:4:4 panel:
56			arm,pl11x,tft-r0g0b0-pads = <4 15 20>;
57		- PL110 TFT (1:)5:5:5 panel:
58			arm,pl11x,tft-r0g0b0-pads = <1 7 13>;
59		- PL111 TFT (1:)5:5:5 panel:
60			arm,pl11x,tft-r0g0b0-pads = <3 11 19>;
61		- PL111 TFT 5:6:5 panel:
62			arm,pl11x,tft-r0g0b0-pads = <3 10 19>;
63		- PL110 and PL111 TFT 8:8:8 panel:
64			arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
65		- PL110 and PL111 TFT 8:8:8 panel, R & B components swapped:
66			arm,pl11x,tft-r0g0b0-pads = <16 8 0>;
67
68
69Example:
70
71	clcd@10020000 {
72		compatible = "arm,pl111", "arm,primecell";
73		reg = <0x10020000 0x1000>;
74		interrupt-names = "combined";
75		interrupts = <0 44 4>;
76		clocks = <&oscclk1>, <&oscclk2>;
77		clock-names = "clcdclk", "apb_pclk";
78		max-memory-bandwidth = <94371840>; /* Bps, 1024x768@60 16bpp */
79
80		port {
81			clcd_pads: endpoint {
82				remote-endpoint = <&clcd_panel>;
83				arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
84			};
85		};
86
87	};
88
89	panel {
90		compatible = "panel-dpi";
91
92		port {
93			clcd_panel: endpoint {
94				remote-endpoint = <&clcd_pads>;
95			};
96		};
97
98		panel-timing {
99			clock-frequency = <25175000>;
100			hactive = <640>;
101			hback-porch = <40>;
102			hfront-porch = <24>;
103			hsync-len = <96>;
104			vactive = <480>;
105			vback-porch = <32>;
106			vfront-porch = <11>;
107			vsync-len = <2>;
108		};
109	};
110