1=====================================================================
2SEC 4 Device Tree Binding
3Copyright (C) 2008-2011 Freescale Semiconductor Inc.
4
5 CONTENTS
6   -Overview
7   -SEC 4 Node
8   -Job Ring Node
9   -Run Time Integrity Check (RTIC) Node
10   -Run Time Integrity Check (RTIC) Memory Node
11   -Secure Non-Volatile Storage (SNVS) Node
12   -Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
13   -Full Example
14
15NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
16Accelerator and Assurance Module (CAAM).
17
18=====================================================================
19Overview
20
21DESCRIPTION
22
23SEC 4 h/w can process requests from 2 types of sources.
241. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
252. Job Rings (HW interface between cores & SEC 4 registers).
26
27High Speed Data Path Configuration:
28
29HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
30such as the P4080.  The number of simultaneous dequeues the QI can make is
31equal to the number of Descriptor Controller (DECO) engines in a particular
32SEC version.  E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
33dequeue from 5 subportals simultaneously.
34
35Job Ring Data Path Configuration:
36
37Each JR is located on a separate 4k page, they may (or may not) be made visible
38in the memory partition devoted to a particular core.  The P4080 has 4 JRs, so
39up to 4 JRs can be configured; and all 4 JRs process requests in parallel.
40
41=====================================================================
42SEC 4 Node
43
44Description
45
46    Node defines the base address of the SEC 4 block.
47    This block specifies the address range of all global
48    configuration registers for the SEC 4 block.  It
49    also receives interrupts from the Run Time Integrity Check
50    (RTIC) function within the SEC 4 block.
51
52PROPERTIES
53
54   - compatible
55      Usage: required
56      Value type: <string>
57      Definition: Must include "fsl,sec-v4.0"
58
59   - fsl,sec-era
60      Usage: optional
61      Value type: <u32>
62      Definition: A standard property. Define the 'ERA' of the SEC
63          device.
64
65   - #address-cells
66       Usage: required
67       Value type: <u32>
68       Definition: A standard property.  Defines the number of cells
69           for representing physical addresses in child nodes.
70
71   - #size-cells
72       Usage: required
73       Value type: <u32>
74       Definition: A standard property.  Defines the number of cells
75           for representing the size of physical addresses in
76           child nodes.
77
78   - reg
79      Usage: required
80      Value type: <prop-encoded-array>
81      Definition: A standard property.  Specifies the physical
82          address and length of the SEC4 configuration registers.
83          registers
84
85   - ranges
86       Usage: required
87       Value type: <prop-encoded-array>
88       Definition: A standard property.  Specifies the physical address
89           range of the SEC 4.0 register space (-SNVS not included).  A
90           triplet that includes the child address, parent address, &
91           length.
92
93   - interrupts
94      Usage: required
95      Value type: <prop_encoded-array>
96      Definition:  Specifies the interrupts generated by this
97           device.  The value of the interrupts property
98           consists of one interrupt specifier. The format
99           of the specifier is defined by the binding document
100           describing the node's interrupt parent.
101
102   - interrupt-parent
103      Usage: (required if interrupt property is defined)
104      Value type: <phandle>
105      Definition: A single <phandle> value that points
106          to the interrupt parent to which the child domain
107          is being mapped.
108
109   - clocks
110      Usage: required if SEC 4.0 requires explicit enablement of clocks
111      Value type: <prop_encoded-array>
112      Definition:  A list of phandle and clock specifier pairs describing
113          the clocks required for enabling and disabling SEC 4.0.
114
115   - clock-names
116      Usage: required if SEC 4.0 requires explicit enablement of clocks
117      Value type: <string>
118      Definition: A list of clock name strings in the same order as the
119          clocks property.
120
121   Note: All other standard properties (see the ePAPR) are allowed
122   but are optional.
123
124
125EXAMPLE
126	crypto@300000 {
127		compatible = "fsl,sec-v4.0";
128		fsl,sec-era = <2>;
129		#address-cells = <1>;
130		#size-cells = <1>;
131		reg = <0x300000 0x10000>;
132		ranges = <0 0x300000 0x10000>;
133		interrupt-parent = <&mpic>;
134		interrupts = <92 2>;
135		clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
136			 <&clks IMX6QDL_CLK_CAAM_ACLK>,
137			 <&clks IMX6QDL_CLK_CAAM_IPG>,
138			 <&clks IMX6QDL_CLK_EIM_SLOW>;
139		clock-names = "mem", "aclk", "ipg", "emi_slow";
140	};
141
142=====================================================================
143Job Ring (JR) Node
144
145    Child of the crypto node defines data processing interface to SEC 4
146    across the peripheral bus for purposes of processing
147    cryptographic descriptors. The specified address
148    range can be made visible to one (or more) cores.
149    The interrupt defined for this node is controlled within
150    the address range of this node.
151
152  - compatible
153      Usage: required
154      Value type: <string>
155      Definition: Must include "fsl,sec-v4.0-job-ring"
156
157  - reg
158      Usage: required
159      Value type: <prop-encoded-array>
160      Definition: Specifies a two JR parameters:  an offset from
161          the parent physical address and the length the JR registers.
162
163   - fsl,liodn
164       Usage: optional-but-recommended
165       Value type: <prop-encoded-array>
166       Definition:
167           Specifies the LIODN to be used in conjunction with
168           the ppid-to-liodn table that specifies the PPID to LIODN mapping.
169           Needed if the PAMU is used.  Value is a 12 bit value
170           where value is a LIODN ID for this JR. This property is
171           normally set by boot firmware.
172
173   - interrupts
174      Usage: required
175      Value type: <prop_encoded-array>
176      Definition:  Specifies the interrupts generated by this
177           device.  The value of the interrupts property
178           consists of one interrupt specifier. The format
179           of the specifier is defined by the binding document
180           describing the node's interrupt parent.
181
182   - interrupt-parent
183      Usage: (required if interrupt property is defined)
184      Value type: <phandle>
185      Definition: A single <phandle> value that points
186          to the interrupt parent to which the child domain
187          is being mapped.
188
189EXAMPLE
190	jr@1000 {
191		compatible = "fsl,sec-v4.0-job-ring";
192		reg = <0x1000 0x1000>;
193		fsl,liodn = <0x081>;
194		interrupt-parent = <&mpic>;
195		interrupts = <88 2>;
196	};
197
198
199=====================================================================
200Run Time Integrity Check (RTIC) Node
201
202  Child node of the crypto node.  Defines a register space that
203  contains up to 5 sets of addresses and their lengths (sizes) that
204  will be checked at run time.  After an initial hash result is
205  calculated, these addresses are checked by HW to monitor any
206  change.  If any memory is modified, a Security Violation is
207  triggered (see SNVS definition).
208
209
210  - compatible
211      Usage: required
212      Value type: <string>
213      Definition: Must include "fsl,sec-v4.0-rtic".
214
215   - #address-cells
216       Usage: required
217       Value type: <u32>
218       Definition: A standard property.  Defines the number of cells
219           for representing physical addresses in child nodes.  Must
220           have a value of 1.
221
222   - #size-cells
223       Usage: required
224       Value type: <u32>
225       Definition: A standard property.  Defines the number of cells
226           for representing the size of physical addresses in
227           child nodes.  Must have a value of 1.
228
229  - reg
230      Usage: required
231      Value type: <prop-encoded-array>
232      Definition: A standard property.  Specifies a two parameters:
233          an offset from the parent physical address and the length
234          the SEC4 registers.
235
236   - ranges
237       Usage: required
238       Value type: <prop-encoded-array>
239       Definition: A standard property.  Specifies the physical address
240           range of the SEC 4 register space (-SNVS not included).  A
241           triplet that includes the child address, parent address, &
242           length.
243
244EXAMPLE
245	rtic@6000 {
246		compatible = "fsl,sec-v4.0-rtic";
247		#address-cells = <1>;
248		#size-cells = <1>;
249		reg = <0x6000 0x100>;
250		ranges = <0x0 0x6100 0xe00>;
251	};
252
253=====================================================================
254Run Time Integrity Check (RTIC) Memory Node
255  A child node that defines individual RTIC memory regions that are used to
256  perform run-time integrity check of memory areas that should not modified.
257  The node defines a register that contains the memory address &
258  length (combined) and a second register that contains the hash result
259  in big endian format.
260
261  - compatible
262      Usage: required
263      Value type: <string>
264      Definition: Must include "fsl,sec-v4.0-rtic-memory".
265
266  - reg
267      Usage: required
268      Value type: <prop-encoded-array>
269      Definition: A standard property.  Specifies two parameters:
270          an offset from the parent physical address and the length:
271
272          1. The location of the RTIC memory address & length registers.
273          2. The location RTIC hash result.
274
275  - fsl,rtic-region
276       Usage: optional-but-recommended
277       Value type: <prop-encoded-array>
278       Definition:
279           Specifies the HW address (36 bit address) for this region
280           followed by the length of the HW partition to be checked;
281           the address is represented as a 64 bit quantity followed
282           by a 32 bit length.
283
284   - fsl,liodn
285       Usage: optional-but-recommended
286       Value type: <prop-encoded-array>
287       Definition:
288           Specifies the LIODN to be used in conjunction with
289           the ppid-to-liodn table that specifies the PPID to LIODN
290           mapping.  Needed if the PAMU is used.  Value is a 12 bit value
291           where value is a LIODN ID for this RTIC memory region. This
292           property is normally set by boot firmware.
293
294EXAMPLE
295	rtic-a@0 {
296		compatible = "fsl,sec-v4.0-rtic-memory";
297		reg = <0x00 0x20 0x100 0x80>;
298		fsl,liodn   = <0x03c>;
299		fsl,rtic-region  = <0x12345678 0x12345678 0x12345678>;
300	};
301
302=====================================================================
303Secure Non-Volatile Storage (SNVS) Node
304
305    Node defines address range and the associated
306    interrupt for the SNVS function.  This function
307    monitors security state information & reports
308    security violations. This also included rtc,
309    system power off and ON/OFF key.
310
311  - compatible
312      Usage: required
313      Value type: <string>
314      Definition: Must include "fsl,sec-v4.0-mon" and "syscon".
315
316  - reg
317      Usage: required
318      Value type: <prop-encoded-array>
319      Definition: A standard property.  Specifies the physical
320          address and length of the SEC4 configuration
321          registers.
322
323   - #address-cells
324       Usage: required
325       Value type: <u32>
326       Definition: A standard property.  Defines the number of cells
327           for representing physical addresses in child nodes.  Must
328           have a value of 1.
329
330   - #size-cells
331       Usage: required
332       Value type: <u32>
333       Definition: A standard property.  Defines the number of cells
334           for representing the size of physical addresses in
335           child nodes.  Must have a value of 1.
336
337   - ranges
338       Usage: required
339       Value type: <prop-encoded-array>
340       Definition: A standard property.  Specifies the physical address
341           range of the SNVS register space.  A triplet that includes
342           the child address, parent address, & length.
343
344   - interrupts
345      Usage: optional
346      Value type: <prop_encoded-array>
347      Definition:  Specifies the interrupts generated by this
348           device.  The value of the interrupts property
349           consists of one interrupt specifier. The format
350           of the specifier is defined by the binding document
351           describing the node's interrupt parent.
352
353   - interrupt-parent
354      Usage: (required if interrupt property is defined)
355      Value type: <phandle>
356      Definition: A single <phandle> value that points
357          to the interrupt parent to which the child domain
358          is being mapped.
359
360EXAMPLE
361	sec_mon@314000 {
362		compatible = "fsl,sec-v4.0-mon", "syscon";
363		reg = <0x314000 0x1000>;
364		ranges = <0 0x314000 0x1000>;
365		interrupt-parent = <&mpic>;
366		interrupts = <93 2>;
367	};
368
369=====================================================================
370Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
371
372  A SNVS child node that defines SNVS LP RTC.
373
374  - compatible
375      Usage: required
376      Value type: <string>
377      Definition: Must include "fsl,sec-v4.0-mon-rtc-lp".
378
379  - interrupts
380      Usage: required
381      Value type: <prop_encoded-array>
382      Definition: Specifies the interrupts generated by this
383	   device.  The value of the interrupts property
384	   consists of one interrupt specifier. The format
385	   of the specifier is defined by the binding document
386	   describing the node's interrupt parent.
387
388 - regmap
389	Usage: required
390	Value type: <phandle>
391	Definition: this is phandle to the register map node.
392
393 - offset
394	Usage: option
395	value type: <u32>
396	Definition: LP register offset. default it is 0x34.
397
398EXAMPLE
399	sec_mon_rtc_lp@1 {
400		compatible = "fsl,sec-v4.0-mon-rtc-lp";
401		interrupts = <93 2>;
402		regmap = <&snvs>;
403		offset = <0x34>;
404	};
405
406=====================================================================
407System ON/OFF key driver
408
409  The snvs-pwrkey is designed to enable POWER key function which controlled
410  by SNVS ONOFF, the driver can report the status of POWER key and wakeup
411  system if pressed after system suspend.
412
413  - compatible:
414      Usage: required
415      Value type: <string>
416      Definition: Mush include "fsl,sec-v4.0-pwrkey".
417
418  - interrupts:
419      Usage: required
420      Value type: <prop_encoded-array>
421      Definition: The SNVS ON/OFF interrupt number to the CPU(s).
422
423  - linux,keycode:
424      Usage: option
425      Value type: <int>
426      Definition: Keycode to emit, KEY_POWER by default.
427
428  - wakeup-source:
429      Usage: option
430      Value type: <boo>
431      Definition: Button can wake-up the system.
432
433 - regmap:
434      Usage: required:
435      Value type: <phandle>
436      Definition: this is phandle to the register map node.
437
438EXAMPLE:
439	snvs-pwrkey@0x020cc000 {
440		compatible = "fsl,sec-v4.0-pwrkey";
441		regmap = <&snvs>;
442		interrupts = <0 4 0x4>
443	        linux,keycode = <116>; /* KEY_POWER */
444		wakeup-source;
445	};
446
447=====================================================================
448FULL EXAMPLE
449
450	crypto: crypto@300000 {
451		compatible = "fsl,sec-v4.0";
452		#address-cells = <1>;
453		#size-cells = <1>;
454		reg = <0x300000 0x10000>;
455		ranges = <0 0x300000 0x10000>;
456		interrupt-parent = <&mpic>;
457		interrupts = <92 2>;
458
459		sec_jr0: jr@1000 {
460			compatible = "fsl,sec-v4.0-job-ring";
461			reg = <0x1000 0x1000>;
462			interrupt-parent = <&mpic>;
463			interrupts = <88 2>;
464		};
465
466		sec_jr1: jr@2000 {
467			compatible = "fsl,sec-v4.0-job-ring";
468			reg = <0x2000 0x1000>;
469			interrupt-parent = <&mpic>;
470			interrupts = <89 2>;
471		};
472
473		sec_jr2: jr@3000 {
474			compatible = "fsl,sec-v4.0-job-ring";
475			reg = <0x3000 0x1000>;
476			interrupt-parent = <&mpic>;
477			interrupts = <90 2>;
478		};
479
480		sec_jr3: jr@4000 {
481			compatible = "fsl,sec-v4.0-job-ring";
482			reg = <0x4000 0x1000>;
483			interrupt-parent = <&mpic>;
484			interrupts = <91 2>;
485		};
486
487		rtic@6000 {
488			compatible = "fsl,sec-v4.0-rtic";
489			#address-cells = <1>;
490			#size-cells = <1>;
491			reg = <0x6000 0x100>;
492			ranges = <0x0 0x6100 0xe00>;
493
494			rtic_a: rtic-a@0 {
495				compatible = "fsl,sec-v4.0-rtic-memory";
496				reg = <0x00 0x20 0x100 0x80>;
497			};
498
499			rtic_b: rtic-b@20 {
500				compatible = "fsl,sec-v4.0-rtic-memory";
501				reg = <0x20 0x20 0x200 0x80>;
502			};
503
504			rtic_c: rtic-c@40 {
505				compatible = "fsl,sec-v4.0-rtic-memory";
506				reg = <0x40 0x20 0x300 0x80>;
507			};
508
509			rtic_d: rtic-d@60 {
510				compatible = "fsl,sec-v4.0-rtic-memory";
511				reg = <0x60 0x20 0x500 0x80>;
512			};
513		};
514	};
515
516	sec_mon: sec_mon@314000 {
517		compatible = "fsl,sec-v4.0-mon";
518		reg = <0x314000 0x1000>;
519		ranges = <0 0x314000 0x1000>;
520
521		sec_mon_rtc_lp@34 {
522			compatible = "fsl,sec-v4.0-mon-rtc-lp";
523			regmap = <&sec_mon>;
524			offset = <0x34>;
525			interrupts = <93 2>;
526		};
527
528		snvs-pwrkey@0x020cc000 {
529			compatible = "fsl,sec-v4.0-pwrkey";
530			regmap = <&sec_mon>;
531			interrupts = <0 4 0x4>;
532			linux,keycode = <116>; /* KEY_POWER */
533			wakeup-source;
534		};
535	};
536
537=====================================================================
538