1* Clock bindings for Freescale i.MX25
2
3Required properties:
4- compatible: Should be "fsl,imx25-ccm"
5- reg: Address and length of the register set
6- interrupts: Should contain CCM interrupt
7- #clock-cells: Should be <1>
8
9The clock consumer should specify the desired clock by having the clock
10ID in its "clocks" phandle cell.  The following is a full list of i.MX25
11clocks and IDs.
12
13	Clock			ID
14	---------------------------
15	dummy			0
16	osc			1
17	mpll			2
18	upll			3
19	mpll_cpu_3_4		4
20	cpu_sel			5
21	cpu			6
22	ahb			7
23	usb_div			8
24	ipg			9
25	per0_sel		10
26	per1_sel		11
27	per2_sel		12
28	per3_sel		13
29	per4_sel		14
30	per5_sel		15
31	per6_sel		16
32	per7_sel		17
33	per8_sel		18
34	per9_sel		19
35	per10_sel		20
36	per11_sel		21
37	per12_sel		22
38	per13_sel		23
39	per14_sel		24
40	per15_sel		25
41	per0			26
42	per1			27
43	per2			28
44	per3			29
45	per4			30
46	per5			31
47	per6			32
48	per7			33
49	per8			34
50	per9			35
51	per10			36
52	per11			37
53	per12			38
54	per13			39
55	per14			40
56	per15			41
57	csi_ipg_per		42
58	epit_ipg_per		43
59	esai_ipg_per		44
60	esdhc1_ipg_per		45
61	esdhc2_ipg_per		46
62	gpt_ipg_per		47
63	i2c_ipg_per		48
64	lcdc_ipg_per		49
65	nfc_ipg_per		50
66	owire_ipg_per		51
67	pwm_ipg_per		52
68	sim1_ipg_per		53
69	sim2_ipg_per		54
70	ssi1_ipg_per		55
71	ssi2_ipg_per		56
72	uart_ipg_per		57
73	ata_ahb			58
74	reserved		59
75	csi_ahb			60
76	emi_ahb			61
77	esai_ahb		62
78	esdhc1_ahb		63
79	esdhc2_ahb		64
80	fec_ahb			65
81	lcdc_ahb		66
82	rtic_ahb		67
83	sdma_ahb		68
84	slcdc_ahb		69
85	usbotg_ahb		70
86	reserved		71
87	reserved		72
88	reserved		73
89	reserved		74
90	can1_ipg		75
91	can2_ipg		76
92	csi_ipg			77
93	cspi1_ipg		78
94	cspi2_ipg		79
95	cspi3_ipg		80
96	dryice_ipg		81
97	ect_ipg			82
98	epit1_ipg		83
99	epit2_ipg		84
100	reserved		85
101	esdhc1_ipg		86
102	esdhc2_ipg		87
103	fec_ipg			88
104	reserved		89
105	reserved		90
106	reserved		91
107	gpt1_ipg		92
108	gpt2_ipg		93
109	gpt3_ipg		94
110	gpt4_ipg		95
111	reserved		96
112	reserved		97
113	reserved		98
114	iim_ipg			99
115	reserved		100
116	reserved		101
117	kpp_ipg			102
118	lcdc_ipg		103
119	reserved		104
120	pwm1_ipg		105
121	pwm2_ipg		106
122	pwm3_ipg		107
123	pwm4_ipg		108
124	rngb_ipg		109
125	reserved		110
126	scc_ipg			111
127	sdma_ipg		112
128	sim1_ipg		113
129	sim2_ipg		114
130	slcdc_ipg		115
131	spba_ipg		116
132	ssi1_ipg		117
133	ssi2_ipg		118
134	tsc_ipg			119
135	uart1_ipg		120
136	uart2_ipg		121
137	uart3_ipg		122
138	uart4_ipg		123
139	uart5_ipg		124
140	reserved		125
141	wdt_ipg			126
142	cko_div			127
143	cko_sel			128
144	cko			129
145
146Examples:
147
148clks: ccm@53f80000 {
149	compatible = "fsl,imx25-ccm";
150	reg = <0x53f80000 0x4000>;
151	interrupts = <31>;
152};
153
154uart1: serial@43f90000 {
155	compatible = "fsl,imx25-uart", "fsl,imx21-uart";
156	reg = <0x43f90000 0x4000>;
157	interrupts = <45>;
158	clocks = <&clks 79>, <&clks 50>;
159	clock-names = "ipg", "per";
160	status = "disabled";
161};
162