1NVIDIA Tegra Power Management Controller (PMC)
2
3The PMC block interacts with an external Power Management Unit. The PMC
4mostly controls the entry and exit of the system from different sleep
5modes. It provides power-gating controllers for SoC and CPU power-islands.
6
7Required properties:
8- name : Should be pmc
9- compatible : For Tegra20, must contain "nvidia,tegra20-pmc".  For Tegra30,
10  must contain "nvidia,tegra30-pmc".  For Tegra114, must contain
11  "nvidia,tegra114-pmc".  For Tegra124, must contain "nvidia,tegra124-pmc".
12  Otherwise, must contain "nvidia,<chip>-pmc", plus at least one of the
13  above, where <chip> is tegra132.
14- reg : Offset and length of the register set for the device
15- clocks : Must contain an entry for each entry in clock-names.
16  See ../clocks/clock-bindings.txt for details.
17- clock-names : Must include the following entries:
18  "pclk" (The Tegra clock of that name),
19  "clk32k_in" (The 32KHz clock input to Tegra).
20
21Optional properties:
22- nvidia,invert-interrupt : If present, inverts the PMU interrupt signal.
23  The PMU is an external Power Management Unit, whose interrupt output
24  signal is fed into the PMC. This signal is optionally inverted, and then
25  fed into the ARM GIC. The PMC is not involved in the detection or
26  handling of this interrupt signal, merely its inversion.
27- nvidia,suspend-mode : The suspend mode that the platform should use.
28  Valid values are 0, 1 and 2:
29  0 (LP0): CPU + Core voltage off and DRAM in self-refresh
30  1 (LP1): CPU voltage off and DRAM in self-refresh
31  2 (LP2): CPU voltage off
32- nvidia,core-power-req-active-high : Boolean, core power request active-high
33- nvidia,sys-clock-req-active-high : Boolean, system clock request active-high
34- nvidia,combined-power-req : Boolean, combined power request for CPU & Core
35- nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC)
36			   is enabled.
37
38Required properties when nvidia,suspend-mode is specified:
39- nvidia,cpu-pwr-good-time : CPU power good time in uS.
40- nvidia,cpu-pwr-off-time : CPU power off time in uS.
41- nvidia,core-pwr-good-time : <Oscillator-stable-time Power-stable-time>
42			      Core power good time in uS.
43- nvidia,core-pwr-off-time : Core power off time in uS.
44
45Required properties when nvidia,suspend-mode=<0>:
46- nvidia,lp0-vec : <start length> Starting address and length of LP0 vector
47  The LP0 vector contains the warm boot code that is executed by AVP when
48  resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7
49  processor and always being the first boot processor when chip is power on
50  or resume from deep sleep mode. When the system is resumed from the deep
51  sleep mode, the warm boot code will restore some PLLs, clocks and then
52  bring up CPU0 for resuming the system.
53
54Hardware-triggered thermal reset:
55On Tegra30, Tegra114 and Tegra124, if the 'i2c-thermtrip' subnode exists,
56hardware-triggered thermal reset will be enabled.
57
58Required properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'):
59- nvidia,i2c-controller-id : ID of I2C controller to send poweroff command to. Valid values are
60                             described in section 9.2.148 "APBDEV_PMC_SCRATCH53_0" of the
61                             Tegra K1 Technical Reference Manual.
62- nvidia,bus-addr : Bus address of the PMU on the I2C bus
63- nvidia,reg-addr : I2C register address to write poweroff command to
64- nvidia,reg-data : Poweroff command to write to PMU
65
66Optional properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'):
67- nvidia,pinmux-id : Pinmux used by the hardware when issuing poweroff command.
68                     Defaults to 0. Valid values are described in section 12.5.2
69                     "Pinmux Support" of the Tegra4 Technical Reference Manual.
70
71Example:
72
73/ SoC dts including file
74pmc@7000f400 {
75	compatible = "nvidia,tegra20-pmc";
76	reg = <0x7000e400 0x400>;
77	clocks = <&tegra_car 110>, <&clk32k_in>;
78	clock-names = "pclk", "clk32k_in";
79	nvidia,invert-interrupt;
80	nvidia,suspend-mode = <1>;
81	nvidia,cpu-pwr-good-time = <2000>;
82	nvidia,cpu-pwr-off-time = <100>;
83	nvidia,core-pwr-good-time = <3845 3845>;
84	nvidia,core-pwr-off-time = <458>;
85	nvidia,core-power-req-active-high;
86	nvidia,sys-clock-req-active-high;
87	nvidia,lp0-vec = <0xbdffd000 0x2000>;
88};
89
90/ Tegra board dts file
91{
92	...
93	pmc@7000f400 {
94		i2c-thermtrip {
95			nvidia,i2c-controller-id = <4>;
96			nvidia,bus-addr = <0x40>;
97			nvidia,reg-addr = <0x36>;
98			nvidia,reg-data = <0x2>;
99		};
100	};
101	...
102	clocks {
103		compatible = "simple-bus";
104		#address-cells = <1>;
105		#size-cells = <0>;
106
107		clk32k_in: clock {
108			compatible = "fixed-clock";
109			reg=<0>;
110			#clock-cells = <0>;
111			clock-frequency = <32768>;
112		};
113	};
114	...
115};
116