1Embedded Memory Controller
2
3Properties:
4- name : Should be emc
5- #address-cells : Should be 1
6- #size-cells : Should be 0
7- compatible : Should contain "nvidia,tegra20-emc".
8- reg : Offset and length of the register set for the device
9- nvidia,use-ram-code : If present, the sub-nodes will be addressed
10  and chosen using the ramcode board selector. If omitted, only one
11  set of tables can be present and said tables will be used
12  irrespective of ram-code configuration.
13
14Child device nodes describe the memory settings for different configurations and clock rates.
15
16Example:
17
18	memory-controller@7000f400 {
19		#address-cells = < 1 >;
20		#size-cells = < 0 >;
21		compatible = "nvidia,tegra20-emc";
22		reg = <0x7000f4000 0x200>;
23	}
24
25
26Embedded Memory Controller ram-code table
27
28If the emc node has the nvidia,use-ram-code property present, then the
29next level of nodes below the emc table are used to specify which settings
30apply for which ram-code settings.
31
32If the emc node lacks the nvidia,use-ram-code property, this level is omitted
33and the tables are stored directly under the emc node (see below).
34
35Properties:
36
37- name : Should be emc-tables
38- nvidia,ram-code : the binary representation of the ram-code board strappings
39  for which this node (and children) are valid.
40
41
42
43Embedded Memory Controller configuration table
44
45This is a table containing the EMC register settings for the various
46operating speeds of the memory controller. They are always located as
47subnodes of the emc controller node.
48
49There are two ways of specifying which tables to use:
50
51* The simplest is if there is just one set of tables in the device tree,
52  and they will always be used (based on which frequency is used).
53  This is the preferred method, especially when firmware can fill in
54  this information based on the specific system information and just
55  pass it on to the kernel.
56
57* The slightly more complex one is when more than one memory configuration
58  might exist on the system.  The Tegra20 platform handles this during
59  early boot by selecting one out of possible 4 memory settings based
60  on a 2-pin "ram code" bootstrap setting on the board. The values of
61  these strappings can be read through a register in the SoC, and thus
62  used to select which tables to use.
63
64Properties:
65- name : Should be emc-table
66- compatible : Should contain "nvidia,tegra20-emc-table".
67- reg : either an opaque enumerator to tell different tables apart, or
68  the valid frequency for which the table should be used (in kHz).
69- clock-frequency : the clock frequency for the EMC at which this
70  table should be used (in kHz).
71- nvidia,emc-registers : a 46 word array of EMC registers to be programmed
72  for operation at the 'clock-frequency' setting.
73  The order and contents of the registers are:
74    RC, RFC, RAS, RP, R2W, W2R, R2P, W2P, RD_RCD, WR_RCD, RRD, REXT,
75    WDV, QUSE, QRST, QSAFE, RDV, REFRESH, BURST_REFRESH_NUM, PDEX2WR,
76    PDEX2RD, PCHG2PDEN, ACT2PDEN, AR2PDEN, RW2PDEN, TXSR, TCKE, TFAW,
77    TRPAB, TCLKSTABLE, TCLKSTOP, TREFBW, QUSE_EXTRA, FBIO_CFG6, ODT_WRITE,
78    ODT_READ, FBIO_CFG5, CFG_DIG_DLL, DLL_XFORM_DQS, DLL_XFORM_QUSE,
79    ZCAL_REF_CNT, ZCAL_WAIT_CNT, AUTO_CAL_INTERVAL, CFG_CLKTRIM_0,
80    CFG_CLKTRIM_1, CFG_CLKTRIM_2
81
82		emc-table@166000 {
83			reg = <166000>;
84			compatible = "nvidia,tegra20-emc-table";
85			clock-frequency = < 166000 >;
86			nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0
87						 0 0 0 0 0 0 0 0 0 0 0 0 0 0
88						 0 0 0 0 0 0 0 0 0 0 0 0 0 0
89						 0 0 0 0 >;
90		};
91
92		emc-table@333000 {
93			reg = <333000>;
94			compatible = "nvidia,tegra20-emc-table";
95			clock-frequency = < 333000 >;
96			nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0
97						 0 0 0 0 0 0 0 0 0 0 0 0 0 0
98						 0 0 0 0 0 0 0 0 0 0 0 0 0 0
99						 0 0 0 0 >;
100		};
101