1* ARM Performance Monitor Units 2 3ARM cores often have a PMU for counting cpu and cache events like cache misses 4and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU 5representation in the device tree should be done as under:- 6 7Required properties: 8 9- compatible : should be one of 10 "apm,potenza-pmu" 11 "arm,armv8-pmuv3" 12 "arm.cortex-a57-pmu" 13 "arm.cortex-a53-pmu" 14 "arm,cortex-a17-pmu" 15 "arm,cortex-a15-pmu" 16 "arm,cortex-a12-pmu" 17 "arm,cortex-a9-pmu" 18 "arm,cortex-a8-pmu" 19 "arm,cortex-a7-pmu" 20 "arm,cortex-a5-pmu" 21 "arm,arm11mpcore-pmu" 22 "arm,arm1176-pmu" 23 "arm,arm1136-pmu" 24 "qcom,scorpion-pmu" 25 "qcom,scorpion-mp-pmu" 26 "qcom,krait-pmu" 27- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu 28 interrupt (PPI) then 1 interrupt should be specified. 29 30Optional properties: 31 32- interrupt-affinity : When using SPIs, specifies a list of phandles to CPU 33 nodes corresponding directly to the affinity of 34 the SPIs listed in the interrupts property. 35 36 When using a PPI, specifies a list of phandles to CPU 37 nodes corresponding to the set of CPUs which have 38 a PMU of this type signalling the PPI listed in the 39 interrupts property. 40 41 This property should be present when there is more than 42 a single SPI. 43 44 45- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd 46 events. 47 48Example: 49 50pmu { 51 compatible = "arm,cortex-a9-pmu"; 52 interrupts = <100 101>; 53}; 54