1Hisilicon Platforms Device Tree Bindings
2----------------------------------------------------
3Hi6220 SoC
4Required root node properties:
5	- compatible = "hisilicon,hi6220";
6
7Hi4511 Board
8Required root node properties:
9	- compatible = "hisilicon,hi3620-hi4511";
10
11HiP04 D01 Board
12Required root node properties:
13	- compatible = "hisilicon,hip04-d01";
14
15HiP01 ca9x2 Board
16Required root node properties:
17	- compatible = "hisilicon,hip01-ca9x2";
18
19HiKey Board
20Required root node properties:
21	- compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
22
23HiP05 D02 Board
24Required root node properties:
25	- compatible = "hisilicon,hip05-d02";
26
27Hisilicon system controller
28
29Required properties:
30- compatible : "hisilicon,sysctrl"
31- reg : Register address and size
32
33Optional properties:
34- smp-offset : offset in sysctrl for notifying slave cpu booting
35		cpu 1, reg;
36		cpu 2, reg + 0x4;
37		cpu 3, reg + 0x8;
38		If reg value is not zero, cpun exit wfi and go
39- resume-offset : offset in sysctrl for notifying cpu0 when resume
40- reboot-offset : offset in sysctrl for system reboot
41
42Example:
43
44	/* for Hi3620 */
45	sysctrl: system-controller@fc802000 {
46		compatible = "hisilicon,sysctrl";
47		reg = <0xfc802000 0x1000>;
48		smp-offset = <0x31c>;
49		resume-offset = <0x308>;
50		reboot-offset = <0x4>;
51	};
52
53-----------------------------------------------------------------------
54Hisilicon Hi6220 system controller
55
56Required properties:
57- compatible : "hisilicon,hi6220-sysctrl"
58- reg : Register address and size
59- #clock-cells: should be set to 1, many clock registers are defined
60  under this controller and this property must be present.
61
62Hisilicon designs this controller as one of the system controllers,
63its main functions are the same as Hisilicon system controller, but
64the register offset of some core modules are different.
65
66Example:
67	/*for Hi6220*/
68	sys_ctrl: sys_ctrl@f7030000 {
69		compatible = "hisilicon,hi6220-sysctrl", "syscon";
70		reg = <0x0 0xf7030000 0x0 0x2000>;
71		#clock-cells = <1>;
72	};
73
74
75Hisilicon Hi6220 Power Always ON domain controller
76
77Required properties:
78- compatible : "hisilicon,hi6220-aoctrl"
79- reg : Register address and size
80- #clock-cells: should be set to 1, many clock registers are defined
81  under this controller and this property must be present.
82
83Hisilicon designs this system controller to control the power always
84on domain for mobile platform.
85
86Example:
87	/*for Hi6220*/
88	ao_ctrl: ao_ctrl@f7800000 {
89		compatible = "hisilicon,hi6220-aoctrl", "syscon";
90		reg = <0x0 0xf7800000 0x0 0x2000>;
91		#clock-cells = <1>;
92	};
93
94
95Hisilicon Hi6220 Media domain controller
96
97Required properties:
98- compatible : "hisilicon,hi6220-mediactrl"
99- reg : Register address and size
100- #clock-cells: should be set to 1, many clock registers are defined
101  under this controller and this property must be present.
102
103Hisilicon designs this system controller to control the multimedia
104domain(e.g. codec, G3D ...) for mobile platform.
105
106Example:
107	/*for Hi6220*/
108	media_ctrl: media_ctrl@f4410000 {
109		compatible = "hisilicon,hi6220-mediactrl", "syscon";
110		reg = <0x0 0xf4410000 0x0 0x1000>;
111		#clock-cells = <1>;
112	};
113
114
115Hisilicon Hi6220 Power Management domain controller
116
117Required properties:
118- compatible : "hisilicon,hi6220-pmctrl"
119- reg : Register address and size
120- #clock-cells: should be set to 1, some clock registers are define
121  under this controller and this property must be present.
122
123Hisilicon designs this system controller to control the power management
124domain for mobile platform.
125
126Example:
127	/*for Hi6220*/
128	pm_ctrl: pm_ctrl@f7032000 {
129		compatible = "hisilicon,hi6220-pmctrl", "syscon";
130		reg = <0x0 0xf7032000 0x0 0x1000>;
131		#clock-cells = <1>;
132	};
133
134
135Hisilicon Hi6220 SRAM controller
136
137Required properties:
138- compatible : "hisilicon,hi6220-sramctrl", "syscon"
139- reg : Register address and size
140
141Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several
142SRAM banks for power management, modem, security, etc. Further, use "syscon"
143managing the common sram which can be shared by multiple modules.
144
145Example:
146	/*for Hi6220*/
147	sram: sram@fff80000 {
148		compatible = "hisilicon,hi6220-sramctrl", "syscon";
149		reg = <0x0 0xfff80000 0x0 0x12000>;
150	};
151
152-----------------------------------------------------------------------
153Hisilicon HiP01 system controller
154
155Required properties:
156- compatible : "hisilicon,hip01-sysctrl"
157- reg : Register address and size
158
159The HiP01 system controller is mostly compatible with hisilicon
160system controller,but it has some specific control registers for
161HIP01 SoC family, such as slave core boot, and also some same
162registers located at different offset.
163
164Example:
165
166	/* for hip01-ca9x2 */
167	sysctrl: system-controller@10000000 {
168		compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
169		reg = <0x10000000 0x1000>;
170		reboot-offset = <0x4>;
171	};
172
173-----------------------------------------------------------------------
174Hisilicon HiP05 PCIe-SAS system controller
175
176Required properties:
177- compatible : "hisilicon,pcie-sas-subctrl", "syscon";
178- reg : Register address and size
179
180The HiP05 PCIe-SAS system controller is shared by PCIe and SAS controllers in
181HiP05 Soc to implement some basic configurations.
182
183Example:
184	/* for HiP05 PCIe-SAS system */
185	pcie_sas: system_controller@0xb0000000 {
186		compatible = "hisilicon,pcie-sas-subctrl", "syscon";
187		reg = <0xb0000000 0x10000>;
188	};
189
190-----------------------------------------------------------------------
191Hisilicon CPU controller
192
193Required properties:
194- compatible : "hisilicon,cpuctrl"
195- reg : Register address and size
196
197The clock registers and power registers of secondary cores are defined
198in CPU controller, especially in HIX5HD2 SoC.
199
200-----------------------------------------------------------------------
201PCTRL: Peripheral misc control register
202
203Required Properties:
204- compatible: "hisilicon,pctrl"
205- reg: Address and size of pctrl.
206
207Example:
208
209	/* for Hi3620 */
210	pctrl: pctrl@fca09000 {
211		compatible = "hisilicon,pctrl";
212		reg = <0xfca09000 0x1000>;
213	};
214
215-----------------------------------------------------------------------
216Fabric:
217
218Required Properties:
219- compatible: "hisilicon,hip04-fabric";
220- reg: Address and size of Fabric
221
222-----------------------------------------------------------------------
223Bootwrapper boot method (software protocol on SMP):
224
225Required Properties:
226- compatible: "hisilicon,hip04-bootwrapper";
227- boot-method: Address and size of boot method.
228  [0]: bootwrapper physical address
229  [1]: bootwrapper size
230  [2]: relocation physical address
231  [3]: relocation size
232