1================= 2ARM CPUs bindings 3================= 4 5The device tree allows to describe the layout of CPUs in a system through 6the "cpus" node, which in turn contains a number of subnodes (ie "cpu") 7defining properties for every cpu. 8 9Bindings for CPU nodes follow the ePAPR v1.1 standard, available from: 10 11https://www.power.org/documentation/epapr-version-1-1/ 12 13with updates for 32-bit and 64-bit ARM systems provided in this document. 14 15================================ 16Convention used in this document 17================================ 18 19This document follows the conventions described in the ePAPR v1.1, with 20the addition: 21 22- square brackets define bitfields, eg reg[7:0] value of the bitfield in 23 the reg property contained in bits 7 down to 0 24 25===================================== 26cpus and cpu node bindings definition 27===================================== 28 29The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu 30nodes to be present and contain the properties described below. 31 32- cpus node 33 34 Description: Container of cpu nodes 35 36 The node name must be "cpus". 37 38 A cpus node must define the following properties: 39 40 - #address-cells 41 Usage: required 42 Value type: <u32> 43 44 Definition depends on ARM architecture version and 45 configuration: 46 47 # On uniprocessor ARM architectures previous to v7 48 value must be 1, to enable a simple enumeration 49 scheme for processors that do not have a HW CPU 50 identification register. 51 # On 32-bit ARM 11 MPcore, ARM v7 or later systems 52 value must be 1, that corresponds to CPUID/MPIDR 53 registers sizes. 54 # On ARM v8 64-bit systems value should be set to 2, 55 that corresponds to the MPIDR_EL1 register size. 56 If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 57 in the system, #address-cells can be set to 1, since 58 MPIDR_EL1[63:32] bits are not used for CPUs 59 identification. 60 - #size-cells 61 Usage: required 62 Value type: <u32> 63 Definition: must be set to 0 64 65- cpu node 66 67 Description: Describes a CPU in an ARM based system 68 69 PROPERTIES 70 71 - device_type 72 Usage: required 73 Value type: <string> 74 Definition: must be "cpu" 75 - reg 76 Usage and definition depend on ARM architecture version and 77 configuration: 78 79 # On uniprocessor ARM architectures previous to v7 80 this property is required and must be set to 0. 81 82 # On ARM 11 MPcore based systems this property is 83 required and matches the CPUID[11:0] register bits. 84 85 Bits [11:0] in the reg cell must be set to 86 bits [11:0] in CPU ID register. 87 88 All other bits in the reg cell must be set to 0. 89 90 # On 32-bit ARM v7 or later systems this property is 91 required and matches the CPU MPIDR[23:0] register 92 bits. 93 94 Bits [23:0] in the reg cell must be set to 95 bits [23:0] in MPIDR. 96 97 All other bits in the reg cell must be set to 0. 98 99 # On ARM v8 64-bit systems this property is required 100 and matches the MPIDR_EL1 register affinity bits. 101 102 * If cpus node's #address-cells property is set to 2 103 104 The first reg cell bits [7:0] must be set to 105 bits [39:32] of MPIDR_EL1. 106 107 The second reg cell bits [23:0] must be set to 108 bits [23:0] of MPIDR_EL1. 109 110 * If cpus node's #address-cells property is set to 1 111 112 The reg cell bits [23:0] must be set to bits [23:0] 113 of MPIDR_EL1. 114 115 All other bits in the reg cells must be set to 0. 116 117 - compatible: 118 Usage: required 119 Value type: <string> 120 Definition: should be one of: 121 "arm,arm710t" 122 "arm,arm720t" 123 "arm,arm740t" 124 "arm,arm7ej-s" 125 "arm,arm7tdmi" 126 "arm,arm7tdmi-s" 127 "arm,arm9es" 128 "arm,arm9ej-s" 129 "arm,arm920t" 130 "arm,arm922t" 131 "arm,arm925" 132 "arm,arm926e-s" 133 "arm,arm926ej-s" 134 "arm,arm940t" 135 "arm,arm946e-s" 136 "arm,arm966e-s" 137 "arm,arm968e-s" 138 "arm,arm9tdmi" 139 "arm,arm1020e" 140 "arm,arm1020t" 141 "arm,arm1022e" 142 "arm,arm1026ej-s" 143 "arm,arm1136j-s" 144 "arm,arm1136jf-s" 145 "arm,arm1156t2-s" 146 "arm,arm1156t2f-s" 147 "arm,arm1176jzf" 148 "arm,arm1176jz-s" 149 "arm,arm1176jzf-s" 150 "arm,arm11mpcore" 151 "arm,cortex-a5" 152 "arm,cortex-a7" 153 "arm,cortex-a8" 154 "arm,cortex-a9" 155 "arm,cortex-a12" 156 "arm,cortex-a15" 157 "arm,cortex-a17" 158 "arm,cortex-a53" 159 "arm,cortex-a57" 160 "arm,cortex-m0" 161 "arm,cortex-m0+" 162 "arm,cortex-m1" 163 "arm,cortex-m3" 164 "arm,cortex-m4" 165 "arm,cortex-r4" 166 "arm,cortex-r5" 167 "arm,cortex-r7" 168 "brcm,brahma-b15" 169 "cavium,thunder" 170 "faraday,fa526" 171 "intel,sa110" 172 "intel,sa1100" 173 "marvell,feroceon" 174 "marvell,mohawk" 175 "marvell,pj4a" 176 "marvell,pj4b" 177 "marvell,sheeva-v5" 178 "nvidia,tegra132-denver" 179 "qcom,krait" 180 "qcom,scorpion" 181 - enable-method 182 Value type: <stringlist> 183 Usage and definition depend on ARM architecture version. 184 # On ARM v8 64-bit this property is required and must 185 be one of: 186 "psci" 187 "spin-table" 188 # On ARM 32-bit systems this property is optional and 189 can be one of: 190 "allwinner,sun6i-a31" 191 "allwinner,sun8i-a23" 192 "arm,psci" 193 "brcm,brahma-b15" 194 "marvell,armada-375-smp" 195 "marvell,armada-380-smp" 196 "marvell,armada-390-smp" 197 "marvell,armada-xp-smp" 198 "mediatek,mt6589-smp" 199 "mediatek,mt81xx-tz-smp" 200 "qcom,gcc-msm8660" 201 "qcom,kpss-acc-v1" 202 "qcom,kpss-acc-v2" 203 "rockchip,rk3066-smp" 204 "ste,dbx500-smp" 205 206 - cpu-release-addr 207 Usage: required for systems that have an "enable-method" 208 property value of "spin-table". 209 Value type: <prop-encoded-array> 210 Definition: 211 # On ARM v8 64-bit systems must be a two cell 212 property identifying a 64-bit zero-initialised 213 memory location. 214 215 - qcom,saw 216 Usage: required for systems that have an "enable-method" 217 property value of "qcom,kpss-acc-v1" or 218 "qcom,kpss-acc-v2" 219 Value type: <phandle> 220 Definition: Specifies the SAW[1] node associated with this CPU. 221 222 - qcom,acc 223 Usage: required for systems that have an "enable-method" 224 property value of "qcom,kpss-acc-v1" or 225 "qcom,kpss-acc-v2" 226 Value type: <phandle> 227 Definition: Specifies the ACC[2] node associated with this CPU. 228 229 - cpu-idle-states 230 Usage: Optional 231 Value type: <prop-encoded-array> 232 Definition: 233 # List of phandles to idle state nodes supported 234 by this cpu [3]. 235 236 - rockchip,pmu 237 Usage: optional for systems that have an "enable-method" 238 property value of "rockchip,rk3066-smp" 239 While optional, it is the preferred way to get access to 240 the cpu-core power-domains. 241 Value type: <phandle> 242 Definition: Specifies the syscon node controlling the cpu core 243 power domains. 244 245Example 1 (dual-cluster big.LITTLE system 32-bit): 246 247 cpus { 248 #size-cells = <0>; 249 #address-cells = <1>; 250 251 cpu@0 { 252 device_type = "cpu"; 253 compatible = "arm,cortex-a15"; 254 reg = <0x0>; 255 }; 256 257 cpu@1 { 258 device_type = "cpu"; 259 compatible = "arm,cortex-a15"; 260 reg = <0x1>; 261 }; 262 263 cpu@100 { 264 device_type = "cpu"; 265 compatible = "arm,cortex-a7"; 266 reg = <0x100>; 267 }; 268 269 cpu@101 { 270 device_type = "cpu"; 271 compatible = "arm,cortex-a7"; 272 reg = <0x101>; 273 }; 274 }; 275 276Example 2 (Cortex-A8 uniprocessor 32-bit system): 277 278 cpus { 279 #size-cells = <0>; 280 #address-cells = <1>; 281 282 cpu@0 { 283 device_type = "cpu"; 284 compatible = "arm,cortex-a8"; 285 reg = <0x0>; 286 }; 287 }; 288 289Example 3 (ARM 926EJ-S uniprocessor 32-bit system): 290 291 cpus { 292 #size-cells = <0>; 293 #address-cells = <1>; 294 295 cpu@0 { 296 device_type = "cpu"; 297 compatible = "arm,arm926ej-s"; 298 reg = <0x0>; 299 }; 300 }; 301 302Example 4 (ARM Cortex-A57 64-bit system): 303 304cpus { 305 #size-cells = <0>; 306 #address-cells = <2>; 307 308 cpu@0 { 309 device_type = "cpu"; 310 compatible = "arm,cortex-a57"; 311 reg = <0x0 0x0>; 312 enable-method = "spin-table"; 313 cpu-release-addr = <0 0x20000000>; 314 }; 315 316 cpu@1 { 317 device_type = "cpu"; 318 compatible = "arm,cortex-a57"; 319 reg = <0x0 0x1>; 320 enable-method = "spin-table"; 321 cpu-release-addr = <0 0x20000000>; 322 }; 323 324 cpu@100 { 325 device_type = "cpu"; 326 compatible = "arm,cortex-a57"; 327 reg = <0x0 0x100>; 328 enable-method = "spin-table"; 329 cpu-release-addr = <0 0x20000000>; 330 }; 331 332 cpu@101 { 333 device_type = "cpu"; 334 compatible = "arm,cortex-a57"; 335 reg = <0x0 0x101>; 336 enable-method = "spin-table"; 337 cpu-release-addr = <0 0x20000000>; 338 }; 339 340 cpu@10000 { 341 device_type = "cpu"; 342 compatible = "arm,cortex-a57"; 343 reg = <0x0 0x10000>; 344 enable-method = "spin-table"; 345 cpu-release-addr = <0 0x20000000>; 346 }; 347 348 cpu@10001 { 349 device_type = "cpu"; 350 compatible = "arm,cortex-a57"; 351 reg = <0x0 0x10001>; 352 enable-method = "spin-table"; 353 cpu-release-addr = <0 0x20000000>; 354 }; 355 356 cpu@10100 { 357 device_type = "cpu"; 358 compatible = "arm,cortex-a57"; 359 reg = <0x0 0x10100>; 360 enable-method = "spin-table"; 361 cpu-release-addr = <0 0x20000000>; 362 }; 363 364 cpu@10101 { 365 device_type = "cpu"; 366 compatible = "arm,cortex-a57"; 367 reg = <0x0 0x10101>; 368 enable-method = "spin-table"; 369 cpu-release-addr = <0 0x20000000>; 370 }; 371 372 cpu@100000000 { 373 device_type = "cpu"; 374 compatible = "arm,cortex-a57"; 375 reg = <0x1 0x0>; 376 enable-method = "spin-table"; 377 cpu-release-addr = <0 0x20000000>; 378 }; 379 380 cpu@100000001 { 381 device_type = "cpu"; 382 compatible = "arm,cortex-a57"; 383 reg = <0x1 0x1>; 384 enable-method = "spin-table"; 385 cpu-release-addr = <0 0x20000000>; 386 }; 387 388 cpu@100000100 { 389 device_type = "cpu"; 390 compatible = "arm,cortex-a57"; 391 reg = <0x1 0x100>; 392 enable-method = "spin-table"; 393 cpu-release-addr = <0 0x20000000>; 394 }; 395 396 cpu@100000101 { 397 device_type = "cpu"; 398 compatible = "arm,cortex-a57"; 399 reg = <0x1 0x101>; 400 enable-method = "spin-table"; 401 cpu-release-addr = <0 0x20000000>; 402 }; 403 404 cpu@100010000 { 405 device_type = "cpu"; 406 compatible = "arm,cortex-a57"; 407 reg = <0x1 0x10000>; 408 enable-method = "spin-table"; 409 cpu-release-addr = <0 0x20000000>; 410 }; 411 412 cpu@100010001 { 413 device_type = "cpu"; 414 compatible = "arm,cortex-a57"; 415 reg = <0x1 0x10001>; 416 enable-method = "spin-table"; 417 cpu-release-addr = <0 0x20000000>; 418 }; 419 420 cpu@100010100 { 421 device_type = "cpu"; 422 compatible = "arm,cortex-a57"; 423 reg = <0x1 0x10100>; 424 enable-method = "spin-table"; 425 cpu-release-addr = <0 0x20000000>; 426 }; 427 428 cpu@100010101 { 429 device_type = "cpu"; 430 compatible = "arm,cortex-a57"; 431 reg = <0x1 0x10101>; 432 enable-method = "spin-table"; 433 cpu-release-addr = <0 0x20000000>; 434 }; 435}; 436 437-- 438[1] arm/msm/qcom,saw2.txt 439[2] arm/msm/qcom,kpss-acc.txt 440[3] ARM Linux kernel documentation - idle states bindings 441 Documentation/devicetree/bindings/arm/idle-states.txt 442