1 Booting AArch64 Linux 2 ===================== 3 4Author: Will Deacon <will.deacon@arm.com> 5Date : 07 September 2012 6 7This document is based on the ARM booting document by Russell King and 8is relevant to all public releases of the AArch64 Linux kernel. 9 10The AArch64 exception model is made up of a number of exception levels 11(EL0 - EL3), with EL0 and EL1 having a secure and a non-secure 12counterpart. EL2 is the hypervisor level and exists only in non-secure 13mode. EL3 is the highest priority level and exists only in secure mode. 14 15For the purposes of this document, we will use the term `boot loader' 16simply to define all software that executes on the CPU(s) before control 17is passed to the Linux kernel. This may include secure monitor and 18hypervisor code, or it may just be a handful of instructions for 19preparing a minimal boot environment. 20 21Essentially, the boot loader should provide (as a minimum) the 22following: 23 241. Setup and initialise the RAM 252. Setup the device tree 263. Decompress the kernel image 274. Call the kernel image 28 29 301. Setup and initialise RAM 31--------------------------- 32 33Requirement: MANDATORY 34 35The boot loader is expected to find and initialise all RAM that the 36kernel will use for volatile data storage in the system. It performs 37this in a machine dependent manner. (It may use internal algorithms 38to automatically locate and size all RAM, or it may use knowledge of 39the RAM in the machine, or any other method the boot loader designer 40sees fit.) 41 42 432. Setup the device tree 44------------------------- 45 46Requirement: MANDATORY 47 48The device tree blob (dtb) must be placed on an 8-byte boundary and must 49not exceed 2 megabytes in size. Since the dtb will be mapped cacheable 50using blocks of up to 2 megabytes in size, it must not be placed within 51any 2M region which must be mapped with any specific attributes. 52 53NOTE: versions prior to v4.2 also require that the DTB be placed within 54the 512 MB region starting at text_offset bytes below the kernel Image. 55 563. Decompress the kernel image 57------------------------------ 58 59Requirement: OPTIONAL 60 61The AArch64 kernel does not currently provide a decompressor and 62therefore requires decompression (gzip etc.) to be performed by the boot 63loader if a compressed Image target (e.g. Image.gz) is used. For 64bootloaders that do not implement this requirement, the uncompressed 65Image target is available instead. 66 67 684. Call the kernel image 69------------------------ 70 71Requirement: MANDATORY 72 73The decompressed kernel image contains a 64-byte header as follows: 74 75 u32 code0; /* Executable code */ 76 u32 code1; /* Executable code */ 77 u64 text_offset; /* Image load offset, little endian */ 78 u64 image_size; /* Effective Image size, little endian */ 79 u64 flags; /* kernel flags, little endian */ 80 u64 res2 = 0; /* reserved */ 81 u64 res3 = 0; /* reserved */ 82 u64 res4 = 0; /* reserved */ 83 u32 magic = 0x644d5241; /* Magic number, little endian, "ARM\x64" */ 84 u32 res5; /* reserved (used for PE COFF offset) */ 85 86 87Header notes: 88 89- As of v3.17, all fields are little endian unless stated otherwise. 90 91- code0/code1 are responsible for branching to stext. 92 93- when booting through EFI, code0/code1 are initially skipped. 94 res5 is an offset to the PE header and the PE header has the EFI 95 entry point (efi_stub_entry). When the stub has done its work, it 96 jumps to code0 to resume the normal boot process. 97 98- Prior to v3.17, the endianness of text_offset was not specified. In 99 these cases image_size is zero and text_offset is 0x80000 in the 100 endianness of the kernel. Where image_size is non-zero image_size is 101 little-endian and must be respected. Where image_size is zero, 102 text_offset can be assumed to be 0x80000. 103 104- The flags field (introduced in v3.17) is a little-endian 64-bit field 105 composed as follows: 106 Bit 0: Kernel endianness. 1 if BE, 0 if LE. 107 Bit 1-2: Kernel Page size. 108 0 - Unspecified. 109 1 - 4K 110 2 - 16K 111 3 - 64K 112 Bits 3-63: Reserved. 113 114- When image_size is zero, a bootloader should attempt to keep as much 115 memory as possible free for use by the kernel immediately after the 116 end of the kernel image. The amount of space required will vary 117 depending on selected features, and is effectively unbound. 118 119The Image must be placed text_offset bytes from a 2MB aligned base 120address near the start of usable system RAM and called there. Memory 121below that base address is currently unusable by Linux, and therefore it 122is strongly recommended that this location is the start of system RAM. 123The region between the 2 MB aligned base address and the start of the 124image has no special significance to the kernel, and may be used for 125other purposes. 126At least image_size bytes from the start of the image must be free for 127use by the kernel. 128 129Any memory described to the kernel (even that below the start of the 130image) which is not marked as reserved from the kernel (e.g., with a 131memreserve region in the device tree) will be considered as available to 132the kernel. 133 134Before jumping into the kernel, the following conditions must be met: 135 136- Quiesce all DMA capable devices so that memory does not get 137 corrupted by bogus network packets or disk data. This will save 138 you many hours of debug. 139 140- Primary CPU general-purpose register settings 141 x0 = physical address of device tree blob (dtb) in system RAM. 142 x1 = 0 (reserved for future use) 143 x2 = 0 (reserved for future use) 144 x3 = 0 (reserved for future use) 145 146- CPU mode 147 All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError, 148 IRQ and FIQ). 149 The CPU must be in either EL2 (RECOMMENDED in order to have access to 150 the virtualisation extensions) or non-secure EL1. 151 152- Caches, MMUs 153 The MMU must be off. 154 Instruction cache may be on or off. 155 The address range corresponding to the loaded kernel image must be 156 cleaned to the PoC. In the presence of a system cache or other 157 coherent masters with caches enabled, this will typically require 158 cache maintenance by VA rather than set/way operations. 159 System caches which respect the architected cache maintenance by VA 160 operations must be configured and may be enabled. 161 System caches which do not respect architected cache maintenance by VA 162 operations (not recommended) must be configured and disabled. 163 164- Architected timers 165 CNTFRQ must be programmed with the timer frequency and CNTVOFF must 166 be programmed with a consistent value on all CPUs. If entering the 167 kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0) set where 168 available. 169 170- Coherency 171 All CPUs to be booted by the kernel must be part of the same coherency 172 domain on entry to the kernel. This may require IMPLEMENTATION DEFINED 173 initialisation to enable the receiving of maintenance operations on 174 each CPU. 175 176- System registers 177 All writable architected system registers at the exception level where 178 the kernel image will be entered must be initialised by software at a 179 higher exception level to prevent execution in an UNKNOWN state. 180 181 For systems with a GICv3 interrupt controller to be used in v3 mode: 182 - If EL3 is present: 183 ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1. 184 ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1. 185 - If the kernel is entered at EL1: 186 ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1 187 ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1. 188 - The DT or ACPI tables must describe a GICv3 interrupt controller. 189 190 For systems with a GICv3 interrupt controller to be used in 191 compatibility (v2) mode: 192 - If EL3 is present: 193 ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b0. 194 - If the kernel is entered at EL1: 195 ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b0. 196 - The DT or ACPI tables must describe a GICv2 interrupt controller. 197 198The requirements described above for CPU mode, caches, MMUs, architected 199timers, coherency and system registers apply to all CPUs. All CPUs must 200enter the kernel in the same exception level. 201 202The boot loader is expected to enter the kernel on each CPU in the 203following manner: 204 205- The primary CPU must jump directly to the first instruction of the 206 kernel image. The device tree blob passed by this CPU must contain 207 an 'enable-method' property for each cpu node. The supported 208 enable-methods are described below. 209 210 It is expected that the bootloader will generate these device tree 211 properties and insert them into the blob prior to kernel entry. 212 213- CPUs with a "spin-table" enable-method must have a 'cpu-release-addr' 214 property in their cpu node. This property identifies a 215 naturally-aligned 64-bit zero-initalised memory location. 216 217 These CPUs should spin outside of the kernel in a reserved area of 218 memory (communicated to the kernel by a /memreserve/ region in the 219 device tree) polling their cpu-release-addr location, which must be 220 contained in the reserved region. A wfe instruction may be inserted 221 to reduce the overhead of the busy-loop and a sev will be issued by 222 the primary CPU. When a read of the location pointed to by the 223 cpu-release-addr returns a non-zero value, the CPU must jump to this 224 value. The value will be written as a single 64-bit little-endian 225 value, so CPUs must convert the read value to their native endianness 226 before jumping to it. 227 228- CPUs with a "psci" enable method should remain outside of 229 the kernel (i.e. outside of the regions of memory described to the 230 kernel in the memory node, or in a reserved area of memory described 231 to the kernel by a /memreserve/ region in the device tree). The 232 kernel will issue CPU_ON calls as described in ARM document number ARM 233 DEN 0022A ("Power State Coordination Interface System Software on ARM 234 processors") to bring CPUs into the kernel. 235 236 The device tree should contain a 'psci' node, as described in 237 Documentation/devicetree/bindings/arm/psci.txt. 238 239- Secondary CPU general-purpose register settings 240 x0 = 0 (reserved for future use) 241 x1 = 0 (reserved for future use) 242 x2 = 0 (reserved for future use) 243 x3 = 0 (reserved for future use) 244