1/* 2 * Copyright 2012-2013 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9#ifndef __FSL_SAI_H 10#define __FSL_SAI_H 11 12#include <sound/dmaengine_pcm.h> 13 14#define FSL_SAI_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 15 SNDRV_PCM_FMTBIT_S20_3LE |\ 16 SNDRV_PCM_FMTBIT_S24_LE) 17 18/* SAI Register Map Register */ 19#define FSL_SAI_TCSR 0x00 /* SAI Transmit Control */ 20#define FSL_SAI_TCR1 0x04 /* SAI Transmit Configuration 1 */ 21#define FSL_SAI_TCR2 0x08 /* SAI Transmit Configuration 2 */ 22#define FSL_SAI_TCR3 0x0c /* SAI Transmit Configuration 3 */ 23#define FSL_SAI_TCR4 0x10 /* SAI Transmit Configuration 4 */ 24#define FSL_SAI_TCR5 0x14 /* SAI Transmit Configuration 5 */ 25#define FSL_SAI_TDR 0x20 /* SAI Transmit Data */ 26#define FSL_SAI_TFR 0x40 /* SAI Transmit FIFO */ 27#define FSL_SAI_TMR 0x60 /* SAI Transmit Mask */ 28#define FSL_SAI_RCSR 0x80 /* SAI Receive Control */ 29#define FSL_SAI_RCR1 0x84 /* SAI Receive Configuration 1 */ 30#define FSL_SAI_RCR2 0x88 /* SAI Receive Configuration 2 */ 31#define FSL_SAI_RCR3 0x8c /* SAI Receive Configuration 3 */ 32#define FSL_SAI_RCR4 0x90 /* SAI Receive Configuration 4 */ 33#define FSL_SAI_RCR5 0x94 /* SAI Receive Configuration 5 */ 34#define FSL_SAI_RDR 0xa0 /* SAI Receive Data */ 35#define FSL_SAI_RFR 0xc0 /* SAI Receive FIFO */ 36#define FSL_SAI_RMR 0xe0 /* SAI Receive Mask */ 37 38#define FSL_SAI_xCSR(tx) (tx ? FSL_SAI_TCSR : FSL_SAI_RCSR) 39#define FSL_SAI_xCR1(tx) (tx ? FSL_SAI_TCR1 : FSL_SAI_RCR1) 40#define FSL_SAI_xCR2(tx) (tx ? FSL_SAI_TCR2 : FSL_SAI_RCR2) 41#define FSL_SAI_xCR3(tx) (tx ? FSL_SAI_TCR3 : FSL_SAI_RCR3) 42#define FSL_SAI_xCR4(tx) (tx ? FSL_SAI_TCR4 : FSL_SAI_RCR4) 43#define FSL_SAI_xCR5(tx) (tx ? FSL_SAI_TCR5 : FSL_SAI_RCR5) 44#define FSL_SAI_xDR(tx) (tx ? FSL_SAI_TDR : FSL_SAI_RDR) 45#define FSL_SAI_xFR(tx) (tx ? FSL_SAI_TFR : FSL_SAI_RFR) 46#define FSL_SAI_xMR(tx) (tx ? FSL_SAI_TMR : FSL_SAI_RMR) 47 48/* SAI Transmit/Recieve Control Register */ 49#define FSL_SAI_CSR_TERE BIT(31) 50#define FSL_SAI_CSR_FR BIT(25) 51#define FSL_SAI_CSR_SR BIT(24) 52#define FSL_SAI_CSR_xF_SHIFT 16 53#define FSL_SAI_CSR_xF_W_SHIFT 18 54#define FSL_SAI_CSR_xF_MASK (0x1f << FSL_SAI_CSR_xF_SHIFT) 55#define FSL_SAI_CSR_xF_W_MASK (0x7 << FSL_SAI_CSR_xF_W_SHIFT) 56#define FSL_SAI_CSR_WSF BIT(20) 57#define FSL_SAI_CSR_SEF BIT(19) 58#define FSL_SAI_CSR_FEF BIT(18) 59#define FSL_SAI_CSR_FWF BIT(17) 60#define FSL_SAI_CSR_FRF BIT(16) 61#define FSL_SAI_CSR_xIE_SHIFT 8 62#define FSL_SAI_CSR_xIE_MASK (0x1f << FSL_SAI_CSR_xIE_SHIFT) 63#define FSL_SAI_CSR_WSIE BIT(12) 64#define FSL_SAI_CSR_SEIE BIT(11) 65#define FSL_SAI_CSR_FEIE BIT(10) 66#define FSL_SAI_CSR_FWIE BIT(9) 67#define FSL_SAI_CSR_FRIE BIT(8) 68#define FSL_SAI_CSR_FRDE BIT(0) 69 70/* SAI Transmit and Recieve Configuration 1 Register */ 71#define FSL_SAI_CR1_RFW_MASK 0x1f 72 73/* SAI Transmit and Recieve Configuration 2 Register */ 74#define FSL_SAI_CR2_SYNC BIT(30) 75#define FSL_SAI_CR2_MSEL_MASK (0xff << 26) 76#define FSL_SAI_CR2_MSEL_BUS 0 77#define FSL_SAI_CR2_MSEL_MCLK1 BIT(26) 78#define FSL_SAI_CR2_MSEL_MCLK2 BIT(27) 79#define FSL_SAI_CR2_MSEL_MCLK3 (BIT(26) | BIT(27)) 80#define FSL_SAI_CR2_BCP BIT(25) 81#define FSL_SAI_CR2_BCD_MSTR BIT(24) 82 83/* SAI Transmit and Recieve Configuration 3 Register */ 84#define FSL_SAI_CR3_TRCE BIT(16) 85#define FSL_SAI_CR3_WDFL(x) (x) 86#define FSL_SAI_CR3_WDFL_MASK 0x1f 87 88/* SAI Transmit and Recieve Configuration 4 Register */ 89#define FSL_SAI_CR4_FRSZ(x) (((x) - 1) << 16) 90#define FSL_SAI_CR4_FRSZ_MASK (0x1f << 16) 91#define FSL_SAI_CR4_SYWD(x) (((x) - 1) << 8) 92#define FSL_SAI_CR4_SYWD_MASK (0x1f << 8) 93#define FSL_SAI_CR4_MF BIT(4) 94#define FSL_SAI_CR4_FSE BIT(3) 95#define FSL_SAI_CR4_FSP BIT(1) 96#define FSL_SAI_CR4_FSD_MSTR BIT(0) 97 98/* SAI Transmit and Recieve Configuration 5 Register */ 99#define FSL_SAI_CR5_WNW(x) (((x) - 1) << 24) 100#define FSL_SAI_CR5_WNW_MASK (0x1f << 24) 101#define FSL_SAI_CR5_W0W(x) (((x) - 1) << 16) 102#define FSL_SAI_CR5_W0W_MASK (0x1f << 16) 103#define FSL_SAI_CR5_FBT(x) ((x) << 8) 104#define FSL_SAI_CR5_FBT_MASK (0x1f << 8) 105 106/* SAI type */ 107#define FSL_SAI_DMA BIT(0) 108#define FSL_SAI_USE_AC97 BIT(1) 109#define FSL_SAI_NET BIT(2) 110#define FSL_SAI_TRA_SYN BIT(3) 111#define FSL_SAI_REC_SYN BIT(4) 112#define FSL_SAI_USE_I2S_SLAVE BIT(5) 113 114#define FSL_FMT_TRANSMITTER 0 115#define FSL_FMT_RECEIVER 1 116 117/* SAI clock sources */ 118#define FSL_SAI_CLK_BUS 0 119#define FSL_SAI_CLK_MAST1 1 120#define FSL_SAI_CLK_MAST2 2 121#define FSL_SAI_CLK_MAST3 3 122 123#define FSL_SAI_MCLK_MAX 3 124 125/* SAI data transfer numbers per DMA request */ 126#define FSL_SAI_MAXBURST_TX 6 127#define FSL_SAI_MAXBURST_RX 6 128 129struct fsl_sai { 130 struct platform_device *pdev; 131 struct regmap *regmap; 132 struct clk *bus_clk; 133 struct clk *mclk_clk[FSL_SAI_MCLK_MAX]; 134 135 bool is_lsb_first; 136 bool is_dsp_mode; 137 bool sai_on_imx; 138 bool synchronous[2]; 139 140 struct snd_dmaengine_dai_dma_data dma_params_rx; 141 struct snd_dmaengine_dai_dma_data dma_params_tx; 142}; 143 144#define TX 1 145#define RX 0 146 147#endif /* __FSL_SAI_H */ 148