1/* 2 * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver 3 * 4 * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11#include <linux/module.h> 12#include <linux/moduleparam.h> 13#include <linux/init.h> 14#include <linux/delay.h> 15#include <linux/slab.h> 16#include <linux/pm.h> 17#include <linux/i2c.h> 18#include <linux/clk.h> 19#include <linux/log2.h> 20#include <linux/regmap.h> 21#include <linux/regulator/driver.h> 22#include <linux/regulator/machine.h> 23#include <linux/regulator/consumer.h> 24#include <linux/of_device.h> 25#include <sound/core.h> 26#include <sound/tlv.h> 27#include <sound/pcm.h> 28#include <sound/pcm_params.h> 29#include <sound/soc.h> 30#include <sound/soc-dapm.h> 31#include <sound/initval.h> 32 33#include "sgtl5000.h" 34 35#define SGTL5000_DAP_REG_OFFSET 0x0100 36#define SGTL5000_MAX_REG_OFFSET 0x013A 37 38/* default value of sgtl5000 registers */ 39static const struct reg_default sgtl5000_reg_defaults[] = { 40 { SGTL5000_CHIP_DIG_POWER, 0x0000 }, 41 { SGTL5000_CHIP_CLK_CTRL, 0x0008 }, 42 { SGTL5000_CHIP_I2S_CTRL, 0x0010 }, 43 { SGTL5000_CHIP_SSS_CTRL, 0x0010 }, 44 { SGTL5000_CHIP_ADCDAC_CTRL, 0x020c }, 45 { SGTL5000_CHIP_DAC_VOL, 0x3c3c }, 46 { SGTL5000_CHIP_PAD_STRENGTH, 0x015f }, 47 { SGTL5000_CHIP_ANA_ADC_CTRL, 0x0000 }, 48 { SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 }, 49 { SGTL5000_CHIP_ANA_CTRL, 0x0111 }, 50 { SGTL5000_CHIP_LINREG_CTRL, 0x0000 }, 51 { SGTL5000_CHIP_REF_CTRL, 0x0000 }, 52 { SGTL5000_CHIP_MIC_CTRL, 0x0000 }, 53 { SGTL5000_CHIP_LINE_OUT_CTRL, 0x0000 }, 54 { SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 }, 55 { SGTL5000_CHIP_ANA_POWER, 0x7060 }, 56 { SGTL5000_CHIP_PLL_CTRL, 0x5000 }, 57 { SGTL5000_CHIP_CLK_TOP_CTRL, 0x0000 }, 58 { SGTL5000_CHIP_ANA_STATUS, 0x0000 }, 59 { SGTL5000_CHIP_SHORT_CTRL, 0x0000 }, 60 { SGTL5000_CHIP_ANA_TEST2, 0x0000 }, 61 { SGTL5000_DAP_CTRL, 0x0000 }, 62 { SGTL5000_DAP_PEQ, 0x0000 }, 63 { SGTL5000_DAP_BASS_ENHANCE, 0x0040 }, 64 { SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f }, 65 { SGTL5000_DAP_AUDIO_EQ, 0x0000 }, 66 { SGTL5000_DAP_SURROUND, 0x0040 }, 67 { SGTL5000_DAP_EQ_BASS_BAND0, 0x002f }, 68 { SGTL5000_DAP_EQ_BASS_BAND1, 0x002f }, 69 { SGTL5000_DAP_EQ_BASS_BAND2, 0x002f }, 70 { SGTL5000_DAP_EQ_BASS_BAND3, 0x002f }, 71 { SGTL5000_DAP_EQ_BASS_BAND4, 0x002f }, 72 { SGTL5000_DAP_MAIN_CHAN, 0x8000 }, 73 { SGTL5000_DAP_MIX_CHAN, 0x0000 }, 74 { SGTL5000_DAP_AVC_CTRL, 0x0510 }, 75 { SGTL5000_DAP_AVC_THRESHOLD, 0x1473 }, 76 { SGTL5000_DAP_AVC_ATTACK, 0x0028 }, 77 { SGTL5000_DAP_AVC_DECAY, 0x0050 }, 78}; 79 80/* regulator supplies for sgtl5000, VDDD is an optional external supply */ 81enum sgtl5000_regulator_supplies { 82 VDDA, 83 VDDIO, 84 VDDD, 85 SGTL5000_SUPPLY_NUM 86}; 87 88/* vddd is optional supply */ 89static const char *supply_names[SGTL5000_SUPPLY_NUM] = { 90 "VDDA", 91 "VDDIO", 92 "VDDD" 93}; 94 95#define LDO_CONSUMER_NAME "VDDD_LDO" 96#define LDO_VOLTAGE 1200000 97 98static struct regulator_consumer_supply ldo_consumer[] = { 99 REGULATOR_SUPPLY(LDO_CONSUMER_NAME, NULL), 100}; 101 102static struct regulator_init_data ldo_init_data = { 103 .constraints = { 104 .min_uV = 1200000, 105 .max_uV = 1200000, 106 .valid_modes_mask = REGULATOR_MODE_NORMAL, 107 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 108 }, 109 .num_consumer_supplies = 1, 110 .consumer_supplies = &ldo_consumer[0], 111}; 112 113/* 114 * sgtl5000 internal ldo regulator, 115 * enabled when VDDD not provided 116 */ 117struct ldo_regulator { 118 struct regulator_desc desc; 119 struct regulator_dev *dev; 120 int voltage; 121 void *codec_data; 122 bool enabled; 123}; 124 125enum sgtl5000_micbias_resistor { 126 SGTL5000_MICBIAS_OFF = 0, 127 SGTL5000_MICBIAS_2K = 2, 128 SGTL5000_MICBIAS_4K = 4, 129 SGTL5000_MICBIAS_8K = 8, 130}; 131 132/* sgtl5000 private structure in codec */ 133struct sgtl5000_priv { 134 int sysclk; /* sysclk rate */ 135 int master; /* i2s master or not */ 136 int fmt; /* i2s data format */ 137 struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM]; 138 struct ldo_regulator *ldo; 139 struct regmap *regmap; 140 struct clk *mclk; 141 int revision; 142 u8 micbias_resistor; 143 u8 micbias_voltage; 144}; 145 146/* 147 * mic_bias power on/off share the same register bits with 148 * output impedance of mic bias, when power on mic bias, we 149 * need reclaim it to impedance value. 150 * 0x0 = Powered off 151 * 0x1 = 2Kohm 152 * 0x2 = 4Kohm 153 * 0x3 = 8Kohm 154 */ 155static int mic_bias_event(struct snd_soc_dapm_widget *w, 156 struct snd_kcontrol *kcontrol, int event) 157{ 158 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 159 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 160 161 switch (event) { 162 case SND_SOC_DAPM_POST_PMU: 163 /* change mic bias resistor */ 164 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL, 165 SGTL5000_BIAS_R_MASK, 166 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT); 167 break; 168 169 case SND_SOC_DAPM_PRE_PMD: 170 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL, 171 SGTL5000_BIAS_R_MASK, 0); 172 break; 173 } 174 return 0; 175} 176 177/* 178 * As manual described, ADC/DAC only works when VAG powerup, 179 * So enabled VAG before ADC/DAC up. 180 * In power down case, we need wait 400ms when vag fully ramped down. 181 */ 182static int power_vag_event(struct snd_soc_dapm_widget *w, 183 struct snd_kcontrol *kcontrol, int event) 184{ 185 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 186 const u32 mask = SGTL5000_DAC_POWERUP | SGTL5000_ADC_POWERUP; 187 188 switch (event) { 189 case SND_SOC_DAPM_POST_PMU: 190 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 191 SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP); 192 break; 193 194 case SND_SOC_DAPM_PRE_PMD: 195 /* 196 * Don't clear VAG_POWERUP, when both DAC and ADC are 197 * operational to prevent inadvertently starving the 198 * other one of them. 199 */ 200 if ((snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER) & 201 mask) != mask) { 202 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 203 SGTL5000_VAG_POWERUP, 0); 204 msleep(400); 205 } 206 break; 207 default: 208 break; 209 } 210 211 return 0; 212} 213 214/* input sources for ADC */ 215static const char *adc_mux_text[] = { 216 "MIC_IN", "LINE_IN" 217}; 218 219static SOC_ENUM_SINGLE_DECL(adc_enum, 220 SGTL5000_CHIP_ANA_CTRL, 2, 221 adc_mux_text); 222 223static const struct snd_kcontrol_new adc_mux = 224SOC_DAPM_ENUM("Capture Mux", adc_enum); 225 226/* input sources for DAC */ 227static const char *dac_mux_text[] = { 228 "DAC", "LINE_IN" 229}; 230 231static SOC_ENUM_SINGLE_DECL(dac_enum, 232 SGTL5000_CHIP_ANA_CTRL, 6, 233 dac_mux_text); 234 235static const struct snd_kcontrol_new dac_mux = 236SOC_DAPM_ENUM("Headphone Mux", dac_enum); 237 238static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = { 239 SND_SOC_DAPM_INPUT("LINE_IN"), 240 SND_SOC_DAPM_INPUT("MIC_IN"), 241 242 SND_SOC_DAPM_OUTPUT("HP_OUT"), 243 SND_SOC_DAPM_OUTPUT("LINE_OUT"), 244 245 SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0, 246 mic_bias_event, 247 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 248 249 SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0), 250 SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0), 251 252 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux), 253 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux), 254 255 /* aif for i2s input */ 256 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback", 257 0, SGTL5000_CHIP_DIG_POWER, 258 0, 0), 259 260 /* aif for i2s output */ 261 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture", 262 0, SGTL5000_CHIP_DIG_POWER, 263 1, 0), 264 265 SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0), 266 SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0), 267 268 SND_SOC_DAPM_PRE("VAG_POWER_PRE", power_vag_event), 269 SND_SOC_DAPM_POST("VAG_POWER_POST", power_vag_event), 270}; 271 272/* routes for sgtl5000 */ 273static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = { 274 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */ 275 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */ 276 277 {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */ 278 {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */ 279 280 {"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */ 281 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */ 282 {"LO", NULL, "DAC"}, /* dac --> line_out */ 283 284 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */ 285 {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */ 286 287 {"LINE_OUT", NULL, "LO"}, 288 {"HP_OUT", NULL, "HP"}, 289}; 290 291/* custom function to fetch info of PCM playback volume */ 292static int dac_info_volsw(struct snd_kcontrol *kcontrol, 293 struct snd_ctl_elem_info *uinfo) 294{ 295 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 296 uinfo->count = 2; 297 uinfo->value.integer.min = 0; 298 uinfo->value.integer.max = 0xfc - 0x3c; 299 return 0; 300} 301 302/* 303 * custom function to get of PCM playback volume 304 * 305 * dac volume register 306 * 15-------------8-7--------------0 307 * | R channel vol | L channel vol | 308 * ------------------------------- 309 * 310 * PCM volume with 0.5017 dB steps from 0 to -90 dB 311 * 312 * register values map to dB 313 * 0x3B and less = Reserved 314 * 0x3C = 0 dB 315 * 0x3D = -0.5 dB 316 * 0xF0 = -90 dB 317 * 0xFC and greater = Muted 318 * 319 * register value map to userspace value 320 * 321 * register value 0x3c(0dB) 0xf0(-90dB)0xfc 322 * ------------------------------ 323 * userspace value 0xc0 0 324 */ 325static int dac_get_volsw(struct snd_kcontrol *kcontrol, 326 struct snd_ctl_elem_value *ucontrol) 327{ 328 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 329 int reg; 330 int l; 331 int r; 332 333 reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL); 334 335 /* get left channel volume */ 336 l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT; 337 338 /* get right channel volume */ 339 r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT; 340 341 /* make sure value fall in (0x3c,0xfc) */ 342 l = clamp(l, 0x3c, 0xfc); 343 r = clamp(r, 0x3c, 0xfc); 344 345 /* invert it and map to userspace value */ 346 l = 0xfc - l; 347 r = 0xfc - r; 348 349 ucontrol->value.integer.value[0] = l; 350 ucontrol->value.integer.value[1] = r; 351 352 return 0; 353} 354 355/* 356 * custom function to put of PCM playback volume 357 * 358 * dac volume register 359 * 15-------------8-7--------------0 360 * | R channel vol | L channel vol | 361 * ------------------------------- 362 * 363 * PCM volume with 0.5017 dB steps from 0 to -90 dB 364 * 365 * register values map to dB 366 * 0x3B and less = Reserved 367 * 0x3C = 0 dB 368 * 0x3D = -0.5 dB 369 * 0xF0 = -90 dB 370 * 0xFC and greater = Muted 371 * 372 * userspace value map to register value 373 * 374 * userspace value 0xc0 0 375 * ------------------------------ 376 * register value 0x3c(0dB) 0xf0(-90dB)0xfc 377 */ 378static int dac_put_volsw(struct snd_kcontrol *kcontrol, 379 struct snd_ctl_elem_value *ucontrol) 380{ 381 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 382 int reg; 383 int l; 384 int r; 385 386 l = ucontrol->value.integer.value[0]; 387 r = ucontrol->value.integer.value[1]; 388 389 /* make sure userspace volume fall in (0, 0xfc-0x3c) */ 390 l = clamp(l, 0, 0xfc - 0x3c); 391 r = clamp(r, 0, 0xfc - 0x3c); 392 393 /* invert it, get the value can be set to register */ 394 l = 0xfc - l; 395 r = 0xfc - r; 396 397 /* shift to get the register value */ 398 reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT | 399 r << SGTL5000_DAC_VOL_RIGHT_SHIFT; 400 401 snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg); 402 403 return 0; 404} 405 406static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0); 407 408/* tlv for mic gain, 0db 20db 30db 40db */ 409static const unsigned int mic_gain_tlv[] = { 410 TLV_DB_RANGE_HEAD(2), 411 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 412 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0), 413}; 414 415/* tlv for hp volume, -51.5db to 12.0db, step .5db */ 416static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0); 417 418static const struct snd_kcontrol_new sgtl5000_snd_controls[] = { 419 /* SOC_DOUBLE_S8_TLV with invert */ 420 { 421 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 422 .name = "PCM Playback Volume", 423 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | 424 SNDRV_CTL_ELEM_ACCESS_READWRITE, 425 .info = dac_info_volsw, 426 .get = dac_get_volsw, 427 .put = dac_put_volsw, 428 }, 429 430 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0), 431 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)", 432 SGTL5000_CHIP_ANA_ADC_CTRL, 433 8, 1, 0, capture_6db_attenuate), 434 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0), 435 436 SOC_DOUBLE_TLV("Headphone Playback Volume", 437 SGTL5000_CHIP_ANA_HP_CTRL, 438 0, 8, 439 0x7f, 1, 440 headphone_volume), 441 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL, 442 5, 1, 0), 443 444 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL, 445 0, 3, 0, mic_gain_tlv), 446}; 447 448/* mute the codec used by alsa core */ 449static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute) 450{ 451 struct snd_soc_codec *codec = codec_dai->codec; 452 u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT; 453 454 snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL, 455 adcdac_ctrl, mute ? adcdac_ctrl : 0); 456 457 return 0; 458} 459 460/* set codec format */ 461static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 462{ 463 struct snd_soc_codec *codec = codec_dai->codec; 464 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 465 u16 i2sctl = 0; 466 467 sgtl5000->master = 0; 468 /* 469 * i2s clock and frame master setting. 470 * ONLY support: 471 * - clock and frame slave, 472 * - clock and frame master 473 */ 474 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 475 case SND_SOC_DAIFMT_CBS_CFS: 476 break; 477 case SND_SOC_DAIFMT_CBM_CFM: 478 i2sctl |= SGTL5000_I2S_MASTER; 479 sgtl5000->master = 1; 480 break; 481 default: 482 return -EINVAL; 483 } 484 485 /* setting i2s data format */ 486 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 487 case SND_SOC_DAIFMT_DSP_A: 488 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT; 489 break; 490 case SND_SOC_DAIFMT_DSP_B: 491 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT; 492 i2sctl |= SGTL5000_I2S_LRALIGN; 493 break; 494 case SND_SOC_DAIFMT_I2S: 495 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT; 496 break; 497 case SND_SOC_DAIFMT_RIGHT_J: 498 i2sctl |= SGTL5000_I2S_MODE_RJ << SGTL5000_I2S_MODE_SHIFT; 499 i2sctl |= SGTL5000_I2S_LRPOL; 500 break; 501 case SND_SOC_DAIFMT_LEFT_J: 502 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT; 503 i2sctl |= SGTL5000_I2S_LRALIGN; 504 break; 505 default: 506 return -EINVAL; 507 } 508 509 sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 510 511 /* Clock inversion */ 512 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 513 case SND_SOC_DAIFMT_NB_NF: 514 break; 515 case SND_SOC_DAIFMT_IB_NF: 516 i2sctl |= SGTL5000_I2S_SCLK_INV; 517 break; 518 default: 519 return -EINVAL; 520 } 521 522 snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl); 523 524 return 0; 525} 526 527/* set codec sysclk */ 528static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai, 529 int clk_id, unsigned int freq, int dir) 530{ 531 struct snd_soc_codec *codec = codec_dai->codec; 532 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 533 534 switch (clk_id) { 535 case SGTL5000_SYSCLK: 536 sgtl5000->sysclk = freq; 537 break; 538 default: 539 return -EINVAL; 540 } 541 542 return 0; 543} 544 545/* 546 * set clock according to i2s frame clock, 547 * sgtl5000 provides 2 clock sources: 548 * 1. sys_mclk: sample freq can only be configured to 549 * 1/256, 1/384, 1/512 of sys_mclk. 550 * 2. pll: can derive any audio clocks. 551 * 552 * clock setting rules: 553 * 1. in slave mode, only sys_mclk can be used 554 * 2. as constraint by sys_mclk, sample freq should be set to 32 kHz, 44.1 kHz 555 * and above. 556 * 3. usage of sys_mclk is preferred over pll to save power. 557 */ 558static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate) 559{ 560 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 561 int clk_ctl = 0; 562 int sys_fs; /* sample freq */ 563 564 /* 565 * sample freq should be divided by frame clock, 566 * if frame clock is lower than 44.1 kHz, sample freq should be set to 567 * 32 kHz or 44.1 kHz. 568 */ 569 switch (frame_rate) { 570 case 8000: 571 case 16000: 572 sys_fs = 32000; 573 break; 574 case 11025: 575 case 22050: 576 sys_fs = 44100; 577 break; 578 default: 579 sys_fs = frame_rate; 580 break; 581 } 582 583 /* set divided factor of frame clock */ 584 switch (sys_fs / frame_rate) { 585 case 4: 586 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT; 587 break; 588 case 2: 589 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT; 590 break; 591 case 1: 592 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT; 593 break; 594 default: 595 return -EINVAL; 596 } 597 598 /* set the sys_fs according to frame rate */ 599 switch (sys_fs) { 600 case 32000: 601 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT; 602 break; 603 case 44100: 604 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT; 605 break; 606 case 48000: 607 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT; 608 break; 609 case 96000: 610 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT; 611 break; 612 default: 613 dev_err(codec->dev, "frame rate %d not supported\n", 614 frame_rate); 615 return -EINVAL; 616 } 617 618 /* 619 * calculate the divider of mclk/sample_freq, 620 * factor of freq = 96 kHz can only be 256, since mclk is in the range 621 * of 8 MHz - 27 MHz 622 */ 623 switch (sgtl5000->sysclk / frame_rate) { 624 case 256: 625 clk_ctl |= SGTL5000_MCLK_FREQ_256FS << 626 SGTL5000_MCLK_FREQ_SHIFT; 627 break; 628 case 384: 629 clk_ctl |= SGTL5000_MCLK_FREQ_384FS << 630 SGTL5000_MCLK_FREQ_SHIFT; 631 break; 632 case 512: 633 clk_ctl |= SGTL5000_MCLK_FREQ_512FS << 634 SGTL5000_MCLK_FREQ_SHIFT; 635 break; 636 default: 637 /* if mclk does not satisfy the divider, use pll */ 638 if (sgtl5000->master) { 639 clk_ctl |= SGTL5000_MCLK_FREQ_PLL << 640 SGTL5000_MCLK_FREQ_SHIFT; 641 } else { 642 dev_err(codec->dev, 643 "PLL not supported in slave mode\n"); 644 dev_err(codec->dev, "%d ratio is not supported. " 645 "SYS_MCLK needs to be 256, 384 or 512 * fs\n", 646 sgtl5000->sysclk / frame_rate); 647 return -EINVAL; 648 } 649 } 650 651 /* if using pll, please check manual 6.4.2 for detail */ 652 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) { 653 u64 out, t; 654 int div2; 655 int pll_ctl; 656 unsigned int in, int_div, frac_div; 657 658 if (sgtl5000->sysclk > 17000000) { 659 div2 = 1; 660 in = sgtl5000->sysclk / 2; 661 } else { 662 div2 = 0; 663 in = sgtl5000->sysclk; 664 } 665 if (sys_fs == 44100) 666 out = 180633600; 667 else 668 out = 196608000; 669 t = do_div(out, in); 670 int_div = out; 671 t *= 2048; 672 do_div(t, in); 673 frac_div = t; 674 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT | 675 frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT; 676 677 snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl); 678 if (div2) 679 snd_soc_update_bits(codec, 680 SGTL5000_CHIP_CLK_TOP_CTRL, 681 SGTL5000_INPUT_FREQ_DIV2, 682 SGTL5000_INPUT_FREQ_DIV2); 683 else 684 snd_soc_update_bits(codec, 685 SGTL5000_CHIP_CLK_TOP_CTRL, 686 SGTL5000_INPUT_FREQ_DIV2, 687 0); 688 689 /* power up pll */ 690 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 691 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP, 692 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP); 693 694 /* if using pll, clk_ctrl must be set after pll power up */ 695 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl); 696 } else { 697 /* otherwise, clk_ctrl must be set before pll power down */ 698 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl); 699 700 /* power down pll */ 701 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 702 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP, 703 0); 704 } 705 706 return 0; 707} 708 709/* 710 * Set PCM DAI bit size and sample rate. 711 * input: params_rate, params_fmt 712 */ 713static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream, 714 struct snd_pcm_hw_params *params, 715 struct snd_soc_dai *dai) 716{ 717 struct snd_soc_codec *codec = dai->codec; 718 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 719 int channels = params_channels(params); 720 int i2s_ctl = 0; 721 int stereo; 722 int ret; 723 724 /* sysclk should already set */ 725 if (!sgtl5000->sysclk) { 726 dev_err(codec->dev, "%s: set sysclk first!\n", __func__); 727 return -EFAULT; 728 } 729 730 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 731 stereo = SGTL5000_DAC_STEREO; 732 else 733 stereo = SGTL5000_ADC_STEREO; 734 735 /* set mono to save power */ 736 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo, 737 channels == 1 ? 0 : stereo); 738 739 /* set codec clock base on lrclk */ 740 ret = sgtl5000_set_clock(codec, params_rate(params)); 741 if (ret) 742 return ret; 743 744 /* set i2s data format */ 745 switch (params_width(params)) { 746 case 16: 747 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J) 748 return -EINVAL; 749 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT; 750 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS << 751 SGTL5000_I2S_SCLKFREQ_SHIFT; 752 break; 753 case 20: 754 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT; 755 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << 756 SGTL5000_I2S_SCLKFREQ_SHIFT; 757 break; 758 case 24: 759 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT; 760 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << 761 SGTL5000_I2S_SCLKFREQ_SHIFT; 762 break; 763 case 32: 764 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J) 765 return -EINVAL; 766 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT; 767 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << 768 SGTL5000_I2S_SCLKFREQ_SHIFT; 769 break; 770 default: 771 return -EINVAL; 772 } 773 774 snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL, 775 SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK, 776 i2s_ctl); 777 778 return 0; 779} 780 781#ifdef CONFIG_REGULATOR 782static int ldo_regulator_is_enabled(struct regulator_dev *dev) 783{ 784 struct ldo_regulator *ldo = rdev_get_drvdata(dev); 785 786 return ldo->enabled; 787} 788 789static int ldo_regulator_enable(struct regulator_dev *dev) 790{ 791 struct ldo_regulator *ldo = rdev_get_drvdata(dev); 792 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data; 793 int reg; 794 795 if (ldo_regulator_is_enabled(dev)) 796 return 0; 797 798 /* set regulator value firstly */ 799 reg = (1600 - ldo->voltage / 1000) / 50; 800 reg = clamp(reg, 0x0, 0xf); 801 802 /* amend the voltage value, unit: uV */ 803 ldo->voltage = (1600 - reg * 50) * 1000; 804 805 /* set voltage to register */ 806 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL, 807 SGTL5000_LINREG_VDDD_MASK, reg); 808 809 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 810 SGTL5000_LINEREG_D_POWERUP, 811 SGTL5000_LINEREG_D_POWERUP); 812 813 /* when internal ldo is enabled, simple digital power can be disabled */ 814 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 815 SGTL5000_LINREG_SIMPLE_POWERUP, 816 0); 817 818 ldo->enabled = 1; 819 return 0; 820} 821 822static int ldo_regulator_disable(struct regulator_dev *dev) 823{ 824 struct ldo_regulator *ldo = rdev_get_drvdata(dev); 825 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data; 826 827 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 828 SGTL5000_LINEREG_D_POWERUP, 829 0); 830 831 /* clear voltage info */ 832 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL, 833 SGTL5000_LINREG_VDDD_MASK, 0); 834 835 ldo->enabled = 0; 836 837 return 0; 838} 839 840static int ldo_regulator_get_voltage(struct regulator_dev *dev) 841{ 842 struct ldo_regulator *ldo = rdev_get_drvdata(dev); 843 844 return ldo->voltage; 845} 846 847static struct regulator_ops ldo_regulator_ops = { 848 .is_enabled = ldo_regulator_is_enabled, 849 .enable = ldo_regulator_enable, 850 .disable = ldo_regulator_disable, 851 .get_voltage = ldo_regulator_get_voltage, 852}; 853 854static int ldo_regulator_register(struct snd_soc_codec *codec, 855 struct regulator_init_data *init_data, 856 int voltage) 857{ 858 struct ldo_regulator *ldo; 859 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 860 struct regulator_config config = { }; 861 862 ldo = kzalloc(sizeof(struct ldo_regulator), GFP_KERNEL); 863 864 if (!ldo) 865 return -ENOMEM; 866 867 ldo->desc.name = kstrdup(dev_name(codec->dev), GFP_KERNEL); 868 if (!ldo->desc.name) { 869 kfree(ldo); 870 dev_err(codec->dev, "failed to allocate decs name memory\n"); 871 return -ENOMEM; 872 } 873 874 ldo->desc.type = REGULATOR_VOLTAGE; 875 ldo->desc.owner = THIS_MODULE; 876 ldo->desc.ops = &ldo_regulator_ops; 877 ldo->desc.n_voltages = 1; 878 879 ldo->codec_data = codec; 880 ldo->voltage = voltage; 881 882 config.dev = codec->dev; 883 config.driver_data = ldo; 884 config.init_data = init_data; 885 886 ldo->dev = regulator_register(&ldo->desc, &config); 887 if (IS_ERR(ldo->dev)) { 888 int ret = PTR_ERR(ldo->dev); 889 890 dev_err(codec->dev, "failed to register regulator\n"); 891 kfree(ldo->desc.name); 892 kfree(ldo); 893 894 return ret; 895 } 896 sgtl5000->ldo = ldo; 897 898 return 0; 899} 900 901static int ldo_regulator_remove(struct snd_soc_codec *codec) 902{ 903 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 904 struct ldo_regulator *ldo = sgtl5000->ldo; 905 906 if (!ldo) 907 return 0; 908 909 regulator_unregister(ldo->dev); 910 kfree(ldo->desc.name); 911 kfree(ldo); 912 913 return 0; 914} 915#else 916static int ldo_regulator_register(struct snd_soc_codec *codec, 917 struct regulator_init_data *init_data, 918 int voltage) 919{ 920 dev_err(codec->dev, "this setup needs regulator support in the kernel\n"); 921 return -EINVAL; 922} 923 924static int ldo_regulator_remove(struct snd_soc_codec *codec) 925{ 926 return 0; 927} 928#endif 929 930/* 931 * set dac bias 932 * common state changes: 933 * startup: 934 * off --> standby --> prepare --> on 935 * standby --> prepare --> on 936 * 937 * stop: 938 * on --> prepare --> standby 939 */ 940static int sgtl5000_set_bias_level(struct snd_soc_codec *codec, 941 enum snd_soc_bias_level level) 942{ 943 int ret; 944 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 945 946 switch (level) { 947 case SND_SOC_BIAS_ON: 948 case SND_SOC_BIAS_PREPARE: 949 break; 950 case SND_SOC_BIAS_STANDBY: 951 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 952 ret = regulator_bulk_enable( 953 ARRAY_SIZE(sgtl5000->supplies), 954 sgtl5000->supplies); 955 if (ret) 956 return ret; 957 udelay(10); 958 959 regcache_cache_only(sgtl5000->regmap, false); 960 961 ret = regcache_sync(sgtl5000->regmap); 962 if (ret != 0) { 963 dev_err(codec->dev, 964 "Failed to restore cache: %d\n", ret); 965 966 regcache_cache_only(sgtl5000->regmap, true); 967 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 968 sgtl5000->supplies); 969 970 return ret; 971 } 972 } 973 974 break; 975 case SND_SOC_BIAS_OFF: 976 regcache_cache_only(sgtl5000->regmap, true); 977 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 978 sgtl5000->supplies); 979 break; 980 } 981 982 codec->dapm.bias_level = level; 983 return 0; 984} 985 986#define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 987 SNDRV_PCM_FMTBIT_S20_3LE |\ 988 SNDRV_PCM_FMTBIT_S24_LE |\ 989 SNDRV_PCM_FMTBIT_S32_LE) 990 991static const struct snd_soc_dai_ops sgtl5000_ops = { 992 .hw_params = sgtl5000_pcm_hw_params, 993 .digital_mute = sgtl5000_digital_mute, 994 .set_fmt = sgtl5000_set_dai_fmt, 995 .set_sysclk = sgtl5000_set_dai_sysclk, 996}; 997 998static struct snd_soc_dai_driver sgtl5000_dai = { 999 .name = "sgtl5000", 1000 .playback = { 1001 .stream_name = "Playback", 1002 .channels_min = 1, 1003 .channels_max = 2, 1004 /* 1005 * only support 8~48K + 96K, 1006 * TODO modify hw_param to support more 1007 */ 1008 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000, 1009 .formats = SGTL5000_FORMATS, 1010 }, 1011 .capture = { 1012 .stream_name = "Capture", 1013 .channels_min = 1, 1014 .channels_max = 2, 1015 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000, 1016 .formats = SGTL5000_FORMATS, 1017 }, 1018 .ops = &sgtl5000_ops, 1019 .symmetric_rates = 1, 1020}; 1021 1022static bool sgtl5000_volatile(struct device *dev, unsigned int reg) 1023{ 1024 switch (reg) { 1025 case SGTL5000_CHIP_ID: 1026 case SGTL5000_CHIP_ADCDAC_CTRL: 1027 case SGTL5000_CHIP_ANA_STATUS: 1028 return true; 1029 } 1030 1031 return false; 1032} 1033 1034static bool sgtl5000_readable(struct device *dev, unsigned int reg) 1035{ 1036 switch (reg) { 1037 case SGTL5000_CHIP_ID: 1038 case SGTL5000_CHIP_DIG_POWER: 1039 case SGTL5000_CHIP_CLK_CTRL: 1040 case SGTL5000_CHIP_I2S_CTRL: 1041 case SGTL5000_CHIP_SSS_CTRL: 1042 case SGTL5000_CHIP_ADCDAC_CTRL: 1043 case SGTL5000_CHIP_DAC_VOL: 1044 case SGTL5000_CHIP_PAD_STRENGTH: 1045 case SGTL5000_CHIP_ANA_ADC_CTRL: 1046 case SGTL5000_CHIP_ANA_HP_CTRL: 1047 case SGTL5000_CHIP_ANA_CTRL: 1048 case SGTL5000_CHIP_LINREG_CTRL: 1049 case SGTL5000_CHIP_REF_CTRL: 1050 case SGTL5000_CHIP_MIC_CTRL: 1051 case SGTL5000_CHIP_LINE_OUT_CTRL: 1052 case SGTL5000_CHIP_LINE_OUT_VOL: 1053 case SGTL5000_CHIP_ANA_POWER: 1054 case SGTL5000_CHIP_PLL_CTRL: 1055 case SGTL5000_CHIP_CLK_TOP_CTRL: 1056 case SGTL5000_CHIP_ANA_STATUS: 1057 case SGTL5000_CHIP_SHORT_CTRL: 1058 case SGTL5000_CHIP_ANA_TEST2: 1059 case SGTL5000_DAP_CTRL: 1060 case SGTL5000_DAP_PEQ: 1061 case SGTL5000_DAP_BASS_ENHANCE: 1062 case SGTL5000_DAP_BASS_ENHANCE_CTRL: 1063 case SGTL5000_DAP_AUDIO_EQ: 1064 case SGTL5000_DAP_SURROUND: 1065 case SGTL5000_DAP_FLT_COEF_ACCESS: 1066 case SGTL5000_DAP_COEF_WR_B0_MSB: 1067 case SGTL5000_DAP_COEF_WR_B0_LSB: 1068 case SGTL5000_DAP_EQ_BASS_BAND0: 1069 case SGTL5000_DAP_EQ_BASS_BAND1: 1070 case SGTL5000_DAP_EQ_BASS_BAND2: 1071 case SGTL5000_DAP_EQ_BASS_BAND3: 1072 case SGTL5000_DAP_EQ_BASS_BAND4: 1073 case SGTL5000_DAP_MAIN_CHAN: 1074 case SGTL5000_DAP_MIX_CHAN: 1075 case SGTL5000_DAP_AVC_CTRL: 1076 case SGTL5000_DAP_AVC_THRESHOLD: 1077 case SGTL5000_DAP_AVC_ATTACK: 1078 case SGTL5000_DAP_AVC_DECAY: 1079 case SGTL5000_DAP_COEF_WR_B1_MSB: 1080 case SGTL5000_DAP_COEF_WR_B1_LSB: 1081 case SGTL5000_DAP_COEF_WR_B2_MSB: 1082 case SGTL5000_DAP_COEF_WR_B2_LSB: 1083 case SGTL5000_DAP_COEF_WR_A1_MSB: 1084 case SGTL5000_DAP_COEF_WR_A1_LSB: 1085 case SGTL5000_DAP_COEF_WR_A2_MSB: 1086 case SGTL5000_DAP_COEF_WR_A2_LSB: 1087 return true; 1088 1089 default: 1090 return false; 1091 } 1092} 1093 1094/* 1095 * sgtl5000 has 3 internal power supplies: 1096 * 1. VAG, normally set to vdda/2 1097 * 2. charge pump, set to different value 1098 * according to voltage of vdda and vddio 1099 * 3. line out VAG, normally set to vddio/2 1100 * 1101 * and should be set according to: 1102 * 1. vddd provided by external or not 1103 * 2. vdda and vddio voltage value. > 3.1v or not 1104 * 3. chip revision >=0x11 or not. If >=0x11, not use external vddd. 1105 */ 1106static int sgtl5000_set_power_regs(struct snd_soc_codec *codec) 1107{ 1108 int vddd; 1109 int vdda; 1110 int vddio; 1111 u16 ana_pwr; 1112 u16 lreg_ctrl; 1113 int vag; 1114 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1115 1116 vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer); 1117 vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer); 1118 vddd = regulator_get_voltage(sgtl5000->supplies[VDDD].consumer); 1119 1120 vdda = vdda / 1000; 1121 vddio = vddio / 1000; 1122 vddd = vddd / 1000; 1123 1124 if (vdda <= 0 || vddio <= 0 || vddd < 0) { 1125 dev_err(codec->dev, "regulator voltage not set correctly\n"); 1126 1127 return -EINVAL; 1128 } 1129 1130 /* according to datasheet, maximum voltage of supplies */ 1131 if (vdda > 3600 || vddio > 3600 || vddd > 1980) { 1132 dev_err(codec->dev, 1133 "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n", 1134 vdda, vddio, vddd); 1135 1136 return -EINVAL; 1137 } 1138 1139 /* reset value */ 1140 ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER); 1141 ana_pwr |= SGTL5000_DAC_STEREO | 1142 SGTL5000_ADC_STEREO | 1143 SGTL5000_REFTOP_POWERUP; 1144 lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL); 1145 1146 if (vddio < 3100 && vdda < 3100) { 1147 /* enable internal oscillator used for charge pump */ 1148 snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL, 1149 SGTL5000_INT_OSC_EN, 1150 SGTL5000_INT_OSC_EN); 1151 /* Enable VDDC charge pump */ 1152 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP; 1153 } else if (vddio >= 3100 && vdda >= 3100) { 1154 ana_pwr &= ~SGTL5000_VDDC_CHRGPMP_POWERUP; 1155 /* VDDC use VDDIO rail */ 1156 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD; 1157 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO << 1158 SGTL5000_VDDC_MAN_ASSN_SHIFT; 1159 } 1160 1161 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl); 1162 1163 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr); 1164 1165 /* set voltage to register */ 1166 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL, 1167 SGTL5000_LINREG_VDDD_MASK, 0x8); 1168 1169 /* 1170 * if vddd linear reg has been enabled, 1171 * simple digital supply should be clear to get 1172 * proper VDDD voltage. 1173 */ 1174 if (ana_pwr & SGTL5000_LINEREG_D_POWERUP) 1175 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 1176 SGTL5000_LINREG_SIMPLE_POWERUP, 1177 0); 1178 else 1179 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 1180 SGTL5000_LINREG_SIMPLE_POWERUP | 1181 SGTL5000_STARTUP_POWERUP, 1182 0); 1183 1184 /* 1185 * set ADC/DAC VAG to vdda / 2, 1186 * should stay in range (0.8v, 1.575v) 1187 */ 1188 vag = vdda / 2; 1189 if (vag <= SGTL5000_ANA_GND_BASE) 1190 vag = 0; 1191 else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP * 1192 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT)) 1193 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT; 1194 else 1195 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP; 1196 1197 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL, 1198 SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT); 1199 1200 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */ 1201 vag = vddio / 2; 1202 if (vag <= SGTL5000_LINE_OUT_GND_BASE) 1203 vag = 0; 1204 else if (vag >= SGTL5000_LINE_OUT_GND_BASE + 1205 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX) 1206 vag = SGTL5000_LINE_OUT_GND_MAX; 1207 else 1208 vag = (vag - SGTL5000_LINE_OUT_GND_BASE) / 1209 SGTL5000_LINE_OUT_GND_STP; 1210 1211 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL, 1212 SGTL5000_LINE_OUT_CURRENT_MASK | 1213 SGTL5000_LINE_OUT_GND_MASK, 1214 vag << SGTL5000_LINE_OUT_GND_SHIFT | 1215 SGTL5000_LINE_OUT_CURRENT_360u << 1216 SGTL5000_LINE_OUT_CURRENT_SHIFT); 1217 1218 return 0; 1219} 1220 1221static int sgtl5000_replace_vddd_with_ldo(struct snd_soc_codec *codec) 1222{ 1223 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1224 int ret; 1225 1226 /* set internal ldo to 1.2v */ 1227 ret = ldo_regulator_register(codec, &ldo_init_data, LDO_VOLTAGE); 1228 if (ret) { 1229 dev_err(codec->dev, 1230 "Failed to register vddd internal supplies: %d\n", ret); 1231 return ret; 1232 } 1233 1234 sgtl5000->supplies[VDDD].supply = LDO_CONSUMER_NAME; 1235 1236 dev_info(codec->dev, "Using internal LDO instead of VDDD\n"); 1237 return 0; 1238} 1239 1240static int sgtl5000_enable_regulators(struct snd_soc_codec *codec) 1241{ 1242 int ret; 1243 int i; 1244 int external_vddd = 0; 1245 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1246 struct regulator *vddd; 1247 1248 for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++) 1249 sgtl5000->supplies[i].supply = supply_names[i]; 1250 1251 /* External VDDD only works before revision 0x11 */ 1252 if (sgtl5000->revision < 0x11) { 1253 vddd = regulator_get_optional(codec->dev, "VDDD"); 1254 if (IS_ERR(vddd)) { 1255 /* See if it's just not registered yet */ 1256 if (PTR_ERR(vddd) == -EPROBE_DEFER) 1257 return -EPROBE_DEFER; 1258 } else { 1259 external_vddd = 1; 1260 regulator_put(vddd); 1261 } 1262 } 1263 1264 if (!external_vddd) { 1265 ret = sgtl5000_replace_vddd_with_ldo(codec); 1266 if (ret) 1267 return ret; 1268 } 1269 1270 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies), 1271 sgtl5000->supplies); 1272 if (ret) 1273 goto err_ldo_remove; 1274 1275 ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies), 1276 sgtl5000->supplies); 1277 if (ret) 1278 goto err_regulator_free; 1279 1280 /* wait for all power rails bring up */ 1281 udelay(10); 1282 1283 return 0; 1284 1285err_regulator_free: 1286 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies), 1287 sgtl5000->supplies); 1288err_ldo_remove: 1289 if (!external_vddd) 1290 ldo_regulator_remove(codec); 1291 return ret; 1292 1293} 1294 1295static int sgtl5000_probe(struct snd_soc_codec *codec) 1296{ 1297 int ret; 1298 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1299 1300 ret = sgtl5000_enable_regulators(codec); 1301 if (ret) 1302 return ret; 1303 1304 /* power up sgtl5000 */ 1305 ret = sgtl5000_set_power_regs(codec); 1306 if (ret) 1307 goto err; 1308 1309 /* enable small pop, introduce 400ms delay in turning off */ 1310 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL, 1311 SGTL5000_SMALL_POP, 1); 1312 1313 /* disable short cut detector */ 1314 snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0); 1315 1316 /* 1317 * set i2s as default input of sound switch 1318 * TODO: add sound switch to control and dapm widge. 1319 */ 1320 snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL, 1321 SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT); 1322 snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER, 1323 SGTL5000_ADC_EN | SGTL5000_DAC_EN); 1324 1325 /* enable dac volume ramp by default */ 1326 snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL, 1327 SGTL5000_DAC_VOL_RAMP_EN | 1328 SGTL5000_DAC_MUTE_RIGHT | 1329 SGTL5000_DAC_MUTE_LEFT); 1330 1331 snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f); 1332 1333 snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL, 1334 SGTL5000_HP_ZCD_EN | 1335 SGTL5000_ADC_ZCD_EN); 1336 1337 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL, 1338 SGTL5000_BIAS_R_MASK, 1339 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT); 1340 1341 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL, 1342 SGTL5000_BIAS_VOLT_MASK, 1343 sgtl5000->micbias_voltage << SGTL5000_BIAS_VOLT_SHIFT); 1344 /* 1345 * disable DAP 1346 * TODO: 1347 * Enable DAP in kcontrol and dapm. 1348 */ 1349 snd_soc_write(codec, SGTL5000_DAP_CTRL, 0); 1350 1351 return 0; 1352 1353err: 1354 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 1355 sgtl5000->supplies); 1356 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies), 1357 sgtl5000->supplies); 1358 ldo_regulator_remove(codec); 1359 1360 return ret; 1361} 1362 1363static int sgtl5000_remove(struct snd_soc_codec *codec) 1364{ 1365 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1366 1367 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 1368 sgtl5000->supplies); 1369 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies), 1370 sgtl5000->supplies); 1371 ldo_regulator_remove(codec); 1372 1373 return 0; 1374} 1375 1376static struct snd_soc_codec_driver sgtl5000_driver = { 1377 .probe = sgtl5000_probe, 1378 .remove = sgtl5000_remove, 1379 .set_bias_level = sgtl5000_set_bias_level, 1380 .suspend_bias_off = true, 1381 .controls = sgtl5000_snd_controls, 1382 .num_controls = ARRAY_SIZE(sgtl5000_snd_controls), 1383 .dapm_widgets = sgtl5000_dapm_widgets, 1384 .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets), 1385 .dapm_routes = sgtl5000_dapm_routes, 1386 .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes), 1387}; 1388 1389static const struct regmap_config sgtl5000_regmap = { 1390 .reg_bits = 16, 1391 .val_bits = 16, 1392 .reg_stride = 2, 1393 1394 .max_register = SGTL5000_MAX_REG_OFFSET, 1395 .volatile_reg = sgtl5000_volatile, 1396 .readable_reg = sgtl5000_readable, 1397 1398 .cache_type = REGCACHE_RBTREE, 1399 .reg_defaults = sgtl5000_reg_defaults, 1400 .num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults), 1401}; 1402 1403/* 1404 * Write all the default values from sgtl5000_reg_defaults[] array into the 1405 * sgtl5000 registers, to make sure we always start with the sane registers 1406 * values as stated in the datasheet. 1407 * 1408 * Since sgtl5000 does not have a reset line, nor a reset command in software, 1409 * we follow this approach to guarantee we always start from the default values 1410 * and avoid problems like, not being able to probe after an audio playback 1411 * followed by a system reset or a 'reboot' command in Linux 1412 */ 1413static int sgtl5000_fill_defaults(struct sgtl5000_priv *sgtl5000) 1414{ 1415 int i, ret, val, index; 1416 1417 for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) { 1418 val = sgtl5000_reg_defaults[i].def; 1419 index = sgtl5000_reg_defaults[i].reg; 1420 ret = regmap_write(sgtl5000->regmap, index, val); 1421 if (ret) 1422 return ret; 1423 } 1424 1425 return 0; 1426} 1427 1428static int sgtl5000_i2c_probe(struct i2c_client *client, 1429 const struct i2c_device_id *id) 1430{ 1431 struct sgtl5000_priv *sgtl5000; 1432 int ret, reg, rev; 1433 struct device_node *np = client->dev.of_node; 1434 u32 value; 1435 1436 sgtl5000 = devm_kzalloc(&client->dev, sizeof(*sgtl5000), GFP_KERNEL); 1437 if (!sgtl5000) 1438 return -ENOMEM; 1439 1440 sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap); 1441 if (IS_ERR(sgtl5000->regmap)) { 1442 ret = PTR_ERR(sgtl5000->regmap); 1443 dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret); 1444 return ret; 1445 } 1446 1447 sgtl5000->mclk = devm_clk_get(&client->dev, NULL); 1448 if (IS_ERR(sgtl5000->mclk)) { 1449 ret = PTR_ERR(sgtl5000->mclk); 1450 dev_err(&client->dev, "Failed to get mclock: %d\n", ret); 1451 /* Defer the probe to see if the clk will be provided later */ 1452 if (ret == -ENOENT) 1453 return -EPROBE_DEFER; 1454 return ret; 1455 } 1456 1457 ret = clk_prepare_enable(sgtl5000->mclk); 1458 if (ret) 1459 return ret; 1460 1461 /* Need 8 clocks before I2C accesses */ 1462 udelay(1); 1463 1464 /* read chip information */ 1465 ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, ®); 1466 if (ret) 1467 goto disable_clk; 1468 1469 if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) != 1470 SGTL5000_PARTID_PART_ID) { 1471 dev_err(&client->dev, 1472 "Device with ID register %x is not a sgtl5000\n", reg); 1473 ret = -ENODEV; 1474 goto disable_clk; 1475 } 1476 1477 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT; 1478 dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev); 1479 sgtl5000->revision = rev; 1480 1481 if (np) { 1482 if (!of_property_read_u32(np, 1483 "micbias-resistor-k-ohms", &value)) { 1484 switch (value) { 1485 case SGTL5000_MICBIAS_OFF: 1486 sgtl5000->micbias_resistor = 0; 1487 break; 1488 case SGTL5000_MICBIAS_2K: 1489 sgtl5000->micbias_resistor = 1; 1490 break; 1491 case SGTL5000_MICBIAS_4K: 1492 sgtl5000->micbias_resistor = 2; 1493 break; 1494 case SGTL5000_MICBIAS_8K: 1495 sgtl5000->micbias_resistor = 3; 1496 break; 1497 default: 1498 sgtl5000->micbias_resistor = 2; 1499 dev_err(&client->dev, 1500 "Unsuitable MicBias resistor\n"); 1501 } 1502 } else { 1503 /* default is 4Kohms */ 1504 sgtl5000->micbias_resistor = 2; 1505 } 1506 if (!of_property_read_u32(np, 1507 "micbias-voltage-m-volts", &value)) { 1508 /* 1250mV => 0 */ 1509 /* steps of 250mV */ 1510 if ((value >= 1250) && (value <= 3000)) 1511 sgtl5000->micbias_voltage = (value / 250) - 5; 1512 else { 1513 sgtl5000->micbias_voltage = 0; 1514 dev_err(&client->dev, 1515 "Unsuitable MicBias resistor\n"); 1516 } 1517 } else { 1518 sgtl5000->micbias_voltage = 0; 1519 } 1520 } 1521 1522 i2c_set_clientdata(client, sgtl5000); 1523 1524 /* Ensure sgtl5000 will start with sane register values */ 1525 ret = sgtl5000_fill_defaults(sgtl5000); 1526 if (ret) 1527 goto disable_clk; 1528 1529 ret = snd_soc_register_codec(&client->dev, 1530 &sgtl5000_driver, &sgtl5000_dai, 1); 1531 if (ret) 1532 goto disable_clk; 1533 1534 return 0; 1535 1536disable_clk: 1537 clk_disable_unprepare(sgtl5000->mclk); 1538 return ret; 1539} 1540 1541static int sgtl5000_i2c_remove(struct i2c_client *client) 1542{ 1543 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client); 1544 1545 snd_soc_unregister_codec(&client->dev); 1546 clk_disable_unprepare(sgtl5000->mclk); 1547 return 0; 1548} 1549 1550static const struct i2c_device_id sgtl5000_id[] = { 1551 {"sgtl5000", 0}, 1552 {}, 1553}; 1554 1555MODULE_DEVICE_TABLE(i2c, sgtl5000_id); 1556 1557static const struct of_device_id sgtl5000_dt_ids[] = { 1558 { .compatible = "fsl,sgtl5000", }, 1559 { /* sentinel */ } 1560}; 1561MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids); 1562 1563static struct i2c_driver sgtl5000_i2c_driver = { 1564 .driver = { 1565 .name = "sgtl5000", 1566 .owner = THIS_MODULE, 1567 .of_match_table = sgtl5000_dt_ids, 1568 }, 1569 .probe = sgtl5000_i2c_probe, 1570 .remove = sgtl5000_i2c_remove, 1571 .id_table = sgtl5000_id, 1572}; 1573 1574module_i2c_driver(sgtl5000_i2c_driver); 1575 1576MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver"); 1577MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>"); 1578MODULE_LICENSE("GPL"); 1579