1/* 2 * rt5645.h -- RT5645 ALSA SoC audio driver 3 * 4 * Copyright 2013 Realtek Microelectronics 5 * Author: Bard Liao <bardliao@realtek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12#ifndef __RT5645_H__ 13#define __RT5645_H__ 14 15#include <sound/rt5645.h> 16 17/* Info */ 18#define RT5645_RESET 0x00 19#define RT5645_VENDOR_ID 0xfd 20#define RT5645_VENDOR_ID1 0xfe 21#define RT5645_VENDOR_ID2 0xff 22/* I/O - Output */ 23#define RT5645_SPK_VOL 0x01 24#define RT5645_HP_VOL 0x02 25#define RT5645_LOUT1 0x03 26#define RT5645_LOUT_CTRL 0x05 27/* I/O - Input */ 28#define RT5645_IN1_CTRL1 0x0a 29#define RT5645_IN1_CTRL2 0x0b 30#define RT5645_IN1_CTRL3 0x0c 31#define RT5645_IN2_CTRL 0x0d 32#define RT5645_INL1_INR1_VOL 0x0f 33#define RT5645_SPK_FUNC_LIM 0x14 34#define RT5645_ADJ_HPF_CTRL 0x16 35/* I/O - ADC/DAC/DMIC */ 36#define RT5645_DAC1_DIG_VOL 0x19 37#define RT5645_DAC2_DIG_VOL 0x1a 38#define RT5645_DAC_CTRL 0x1b 39#define RT5645_STO1_ADC_DIG_VOL 0x1c 40#define RT5645_MONO_ADC_DIG_VOL 0x1d 41#define RT5645_ADC_BST_VOL1 0x1e 42/* Mixer - D-D */ 43#define RT5645_ADC_BST_VOL2 0x20 44#define RT5645_STO1_ADC_MIXER 0x27 45#define RT5645_MONO_ADC_MIXER 0x28 46#define RT5645_AD_DA_MIXER 0x29 47#define RT5645_STO_DAC_MIXER 0x2a 48#define RT5645_MONO_DAC_MIXER 0x2b 49#define RT5645_DIG_MIXER 0x2c 50#define RT5650_A_DAC_SOUR 0x2d 51#define RT5645_DIG_INF1_DATA 0x2f 52/* Mixer - PDM */ 53#define RT5645_PDM_OUT_CTRL 0x31 54/* Mixer - ADC */ 55#define RT5645_REC_L1_MIXER 0x3b 56#define RT5645_REC_L2_MIXER 0x3c 57#define RT5645_REC_R1_MIXER 0x3d 58#define RT5645_REC_R2_MIXER 0x3e 59/* Mixer - DAC */ 60#define RT5645_HPMIXL_CTRL 0x3f 61#define RT5645_HPOMIXL_CTRL 0x40 62#define RT5645_HPMIXR_CTRL 0x41 63#define RT5645_HPOMIXR_CTRL 0x42 64#define RT5645_HPO_MIXER 0x45 65#define RT5645_SPK_L_MIXER 0x46 66#define RT5645_SPK_R_MIXER 0x47 67#define RT5645_SPO_MIXER 0x48 68#define RT5645_SPO_CLSD_RATIO 0x4a 69#define RT5645_OUT_L_GAIN1 0x4d 70#define RT5645_OUT_L_GAIN2 0x4e 71#define RT5645_OUT_L1_MIXER 0x4f 72#define RT5645_OUT_R_GAIN1 0x50 73#define RT5645_OUT_R_GAIN2 0x51 74#define RT5645_OUT_R1_MIXER 0x52 75#define RT5645_LOUT_MIXER 0x53 76/* Haptic */ 77#define RT5645_HAPTIC_CTRL1 0x56 78#define RT5645_HAPTIC_CTRL2 0x57 79#define RT5645_HAPTIC_CTRL3 0x58 80#define RT5645_HAPTIC_CTRL4 0x59 81#define RT5645_HAPTIC_CTRL5 0x5a 82#define RT5645_HAPTIC_CTRL6 0x5b 83#define RT5645_HAPTIC_CTRL7 0x5c 84#define RT5645_HAPTIC_CTRL8 0x5d 85#define RT5645_HAPTIC_CTRL9 0x5e 86#define RT5645_HAPTIC_CTRL10 0x5f 87/* Power */ 88#define RT5645_PWR_DIG1 0x61 89#define RT5645_PWR_DIG2 0x62 90#define RT5645_PWR_ANLG1 0x63 91#define RT5645_PWR_ANLG2 0x64 92#define RT5645_PWR_MIXER 0x65 93#define RT5645_PWR_VOL 0x66 94/* Private Register Control */ 95#define RT5645_PRIV_INDEX 0x6a 96#define RT5645_PRIV_DATA 0x6c 97/* Format - ADC/DAC */ 98#define RT5645_I2S1_SDP 0x70 99#define RT5645_I2S2_SDP 0x71 100#define RT5645_ADDA_CLK1 0x73 101#define RT5645_ADDA_CLK2 0x74 102#define RT5645_DMIC_CTRL1 0x75 103#define RT5645_DMIC_CTRL2 0x76 104/* Format - TDM Control */ 105#define RT5645_TDM_CTRL_1 0x77 106#define RT5645_TDM_CTRL_2 0x78 107#define RT5645_TDM_CTRL_3 0x79 108 109/* Function - Analog */ 110#define RT5645_GLB_CLK 0x80 111#define RT5645_PLL_CTRL1 0x81 112#define RT5645_PLL_CTRL2 0x82 113#define RT5645_ASRC_1 0x83 114#define RT5645_ASRC_2 0x84 115#define RT5645_ASRC_3 0x85 116#define RT5645_ASRC_4 0x8a 117#define RT5645_DEPOP_M1 0x8e 118#define RT5645_DEPOP_M2 0x8f 119#define RT5645_DEPOP_M3 0x90 120#define RT5645_CHARGE_PUMP 0x91 121#define RT5645_MICBIAS 0x93 122#define RT5645_A_JD_CTRL1 0x94 123#define RT5645_VAD_CTRL4 0x9d 124#define RT5645_CLSD_OUT_CTRL 0xa0 125/* Function - Digital */ 126#define RT5645_ADC_EQ_CTRL1 0xae 127#define RT5645_ADC_EQ_CTRL2 0xaf 128#define RT5645_EQ_CTRL1 0xb0 129#define RT5645_EQ_CTRL2 0xb1 130#define RT5645_ALC_CTRL_1 0xb3 131#define RT5645_ALC_CTRL_2 0xb4 132#define RT5645_ALC_CTRL_3 0xb5 133#define RT5645_ALC_CTRL_4 0xb6 134#define RT5645_ALC_CTRL_5 0xb7 135#define RT5645_JD_CTRL 0xbb 136#define RT5645_IRQ_CTRL1 0xbc 137#define RT5645_IRQ_CTRL2 0xbd 138#define RT5645_IRQ_CTRL3 0xbe 139#define RT5645_INT_IRQ_ST 0xbf 140#define RT5645_GPIO_CTRL1 0xc0 141#define RT5645_GPIO_CTRL2 0xc1 142#define RT5645_GPIO_CTRL3 0xc2 143#define RT5645_BASS_BACK 0xcf 144#define RT5645_MP3_PLUS1 0xd0 145#define RT5645_MP3_PLUS2 0xd1 146#define RT5645_ADJ_HPF1 0xd3 147#define RT5645_ADJ_HPF2 0xd4 148#define RT5645_HP_CALIB_AMP_DET 0xd6 149#define RT5645_SV_ZCD1 0xd9 150#define RT5645_SV_ZCD2 0xda 151#define RT5645_IL_CMD 0xdb 152#define RT5645_IL_CMD2 0xdc 153#define RT5645_IL_CMD3 0xdd 154#define RT5650_4BTN_IL_CMD1 0xdf 155#define RT5650_4BTN_IL_CMD2 0xe0 156#define RT5645_DRC1_HL_CTRL1 0xe7 157#define RT5645_DRC2_HL_CTRL1 0xe9 158#define RT5645_MUTI_DRC_CTRL1 0xea 159#define RT5645_ADC_MONO_HP_CTRL1 0xec 160#define RT5645_ADC_MONO_HP_CTRL2 0xed 161#define RT5645_DRC2_CTRL1 0xf0 162#define RT5645_DRC2_CTRL2 0xf1 163#define RT5645_DRC2_CTRL3 0xf2 164#define RT5645_DRC2_CTRL4 0xf3 165#define RT5645_DRC2_CTRL5 0xf4 166#define RT5645_JD_CTRL3 0xf8 167#define RT5645_JD_CTRL4 0xf9 168/* General Control */ 169#define RT5645_GEN_CTRL1 0xfa 170#define RT5645_GEN_CTRL2 0xfb 171#define RT5645_GEN_CTRL3 0xfc 172 173 174/* Index of Codec Private Register definition */ 175#define RT5645_DIG_VOL 0x00 176#define RT5645_PR_ALC_CTRL_1 0x01 177#define RT5645_PR_ALC_CTRL_2 0x02 178#define RT5645_PR_ALC_CTRL_3 0x03 179#define RT5645_PR_ALC_CTRL_4 0x04 180#define RT5645_PR_ALC_CTRL_5 0x05 181#define RT5645_PR_ALC_CTRL_6 0x06 182#define RT5645_BIAS_CUR1 0x12 183#define RT5645_BIAS_CUR3 0x14 184#define RT5645_CLSD_INT_REG1 0x1c 185#define RT5645_MAMP_INT_REG2 0x37 186#define RT5645_CHOP_DAC_ADC 0x3d 187#define RT5645_MIXER_INT_REG 0x3f 188#define RT5645_3D_SPK 0x63 189#define RT5645_WND_1 0x6c 190#define RT5645_WND_2 0x6d 191#define RT5645_WND_3 0x6e 192#define RT5645_WND_4 0x6f 193#define RT5645_WND_5 0x70 194#define RT5645_WND_8 0x73 195#define RT5645_DIP_SPK_INF 0x75 196#define RT5645_HP_DCC_INT1 0x77 197#define RT5645_EQ_BW_LOP 0xa0 198#define RT5645_EQ_GN_LOP 0xa1 199#define RT5645_EQ_FC_BP1 0xa2 200#define RT5645_EQ_BW_BP1 0xa3 201#define RT5645_EQ_GN_BP1 0xa4 202#define RT5645_EQ_FC_BP2 0xa5 203#define RT5645_EQ_BW_BP2 0xa6 204#define RT5645_EQ_GN_BP2 0xa7 205#define RT5645_EQ_FC_BP3 0xa8 206#define RT5645_EQ_BW_BP3 0xa9 207#define RT5645_EQ_GN_BP3 0xaa 208#define RT5645_EQ_FC_BP4 0xab 209#define RT5645_EQ_BW_BP4 0xac 210#define RT5645_EQ_GN_BP4 0xad 211#define RT5645_EQ_FC_HIP1 0xae 212#define RT5645_EQ_GN_HIP1 0xaf 213#define RT5645_EQ_FC_HIP2 0xb0 214#define RT5645_EQ_BW_HIP2 0xb1 215#define RT5645_EQ_GN_HIP2 0xb2 216#define RT5645_EQ_PRE_VOL 0xb3 217#define RT5645_EQ_PST_VOL 0xb4 218 219 220/* global definition */ 221#define RT5645_L_MUTE (0x1 << 15) 222#define RT5645_L_MUTE_SFT 15 223#define RT5645_VOL_L_MUTE (0x1 << 14) 224#define RT5645_VOL_L_SFT 14 225#define RT5645_R_MUTE (0x1 << 7) 226#define RT5645_R_MUTE_SFT 7 227#define RT5645_VOL_R_MUTE (0x1 << 6) 228#define RT5645_VOL_R_SFT 6 229#define RT5645_L_VOL_MASK (0x3f << 8) 230#define RT5645_L_VOL_SFT 8 231#define RT5645_R_VOL_MASK (0x3f) 232#define RT5645_R_VOL_SFT 0 233 234/* IN1 Control 1 (0x0a) */ 235#define RT5645_CBJ_BST1_MASK (0xf << 12) 236#define RT5645_CBJ_BST1_SFT (12) 237#define RT5645_CBJ_JD_HP_EN (0x1 << 9) 238#define RT5645_CBJ_JD_MIC_EN (0x1 << 8) 239#define RT5645_CBJ_JD_MIC_SW_EN (0x1 << 7) 240#define RT5645_CBJ_MIC_SEL_R (0x1 << 6) 241#define RT5645_CBJ_MIC_SEL_L (0x1 << 5) 242#define RT5645_CBJ_MIC_SW (0x1 << 4) 243#define RT5645_CBJ_BST1_EN (0x1 << 2) 244 245/* IN1 Control 2 (0x0b) */ 246#define RT5645_CBJ_MN_JD (0x1 << 12) 247#define RT5645_CAPLESS_EN (0x1 << 11) 248#define RT5645_CBJ_DET_MODE (0x1 << 7) 249 250/* IN1 Control 3 (0x0c) */ 251#define RT5645_CBJ_TIE_G_L (0x1 << 15) 252#define RT5645_CBJ_TIE_G_R (0x1 << 14) 253 254/* IN2 Control (0x0d) */ 255#define RT5645_BST_MASK1 (0xf<<12) 256#define RT5645_BST_SFT1 12 257#define RT5645_BST_MASK2 (0xf<<8) 258#define RT5645_BST_SFT2 8 259#define RT5645_IN_DF2 (0x1 << 6) 260#define RT5645_IN_SFT2 6 261 262/* INL and INR Volume Control (0x0f) */ 263#define RT5645_INL_SEL_MASK (0x1 << 15) 264#define RT5645_INL_SEL_SFT 15 265#define RT5645_INL_SEL_IN4P (0x0 << 15) 266#define RT5645_INL_SEL_MONOP (0x1 << 15) 267#define RT5645_INL_VOL_MASK (0x1f << 8) 268#define RT5645_INL_VOL_SFT 8 269#define RT5645_INR_SEL_MASK (0x1 << 7) 270#define RT5645_INR_SEL_SFT 7 271#define RT5645_INR_SEL_IN4N (0x0 << 7) 272#define RT5645_INR_SEL_MONON (0x1 << 7) 273#define RT5645_INR_VOL_MASK (0x1f) 274#define RT5645_INR_VOL_SFT 0 275 276/* DAC1 Digital Volume (0x19) */ 277#define RT5645_DAC_L1_VOL_MASK (0xff << 8) 278#define RT5645_DAC_L1_VOL_SFT 8 279#define RT5645_DAC_R1_VOL_MASK (0xff) 280#define RT5645_DAC_R1_VOL_SFT 0 281 282/* DAC2 Digital Volume (0x1a) */ 283#define RT5645_DAC_L2_VOL_MASK (0xff << 8) 284#define RT5645_DAC_L2_VOL_SFT 8 285#define RT5645_DAC_R2_VOL_MASK (0xff) 286#define RT5645_DAC_R2_VOL_SFT 0 287 288/* DAC2 Control (0x1b) */ 289#define RT5645_M_DAC_L2_VOL (0x1 << 13) 290#define RT5645_M_DAC_L2_VOL_SFT 13 291#define RT5645_M_DAC_R2_VOL (0x1 << 12) 292#define RT5645_M_DAC_R2_VOL_SFT 12 293#define RT5645_DAC2_L_SEL_MASK (0x7 << 4) 294#define RT5645_DAC2_L_SEL_SFT 4 295#define RT5645_DAC2_R_SEL_MASK (0x7 << 0) 296#define RT5645_DAC2_R_SEL_SFT 0 297 298/* ADC Digital Volume Control (0x1c) */ 299#define RT5645_ADC_L_VOL_MASK (0x7f << 8) 300#define RT5645_ADC_L_VOL_SFT 8 301#define RT5645_ADC_R_VOL_MASK (0x7f) 302#define RT5645_ADC_R_VOL_SFT 0 303 304/* Mono ADC Digital Volume Control (0x1d) */ 305#define RT5645_MONO_ADC_L_VOL_MASK (0x7f << 8) 306#define RT5645_MONO_ADC_L_VOL_SFT 8 307#define RT5645_MONO_ADC_R_VOL_MASK (0x7f) 308#define RT5645_MONO_ADC_R_VOL_SFT 0 309 310/* ADC Boost Volume Control (0x1e) */ 311#define RT5645_STO1_ADC_L_BST_MASK (0x3 << 14) 312#define RT5645_STO1_ADC_L_BST_SFT 14 313#define RT5645_STO1_ADC_R_BST_MASK (0x3 << 12) 314#define RT5645_STO1_ADC_R_BST_SFT 12 315#define RT5645_STO1_ADC_COMP_MASK (0x3 << 10) 316#define RT5645_STO1_ADC_COMP_SFT 10 317#define RT5645_STO2_ADC_L_BST_MASK (0x3 << 8) 318#define RT5645_STO2_ADC_L_BST_SFT 8 319#define RT5645_STO2_ADC_R_BST_MASK (0x3 << 6) 320#define RT5645_STO2_ADC_R_BST_SFT 6 321#define RT5645_STO2_ADC_COMP_MASK (0x3 << 4) 322#define RT5645_STO2_ADC_COMP_SFT 4 323 324/* Stereo2 ADC Mixer Control (0x26) */ 325#define RT5645_STO2_ADC_SRC_MASK (0x1 << 15) 326#define RT5645_STO2_ADC_SRC_SFT 15 327 328/* Stereo ADC Mixer Control (0x27) */ 329#define RT5645_M_ADC_L1 (0x1 << 14) 330#define RT5645_M_ADC_L1_SFT 14 331#define RT5645_M_ADC_L2 (0x1 << 13) 332#define RT5645_M_ADC_L2_SFT 13 333#define RT5645_ADC_1_SRC_MASK (0x1 << 12) 334#define RT5645_ADC_1_SRC_SFT 12 335#define RT5645_ADC_1_SRC_ADC (0x1 << 12) 336#define RT5645_ADC_1_SRC_DACMIX (0x0 << 12) 337#define RT5645_ADC_2_SRC_MASK (0x1 << 11) 338#define RT5645_ADC_2_SRC_SFT 11 339#define RT5645_DMIC_SRC_MASK (0x1 << 8) 340#define RT5645_DMIC_SRC_SFT 8 341#define RT5645_M_ADC_R1 (0x1 << 6) 342#define RT5645_M_ADC_R1_SFT 6 343#define RT5645_M_ADC_R2 (0x1 << 5) 344#define RT5645_M_ADC_R2_SFT 5 345#define RT5645_DMIC3_SRC_MASK (0x1 << 1) 346#define RT5645_DMIC3_SRC_SFT 0 347 348/* Mono ADC Mixer Control (0x28) */ 349#define RT5645_M_MONO_ADC_L1 (0x1 << 14) 350#define RT5645_M_MONO_ADC_L1_SFT 14 351#define RT5645_M_MONO_ADC_L2 (0x1 << 13) 352#define RT5645_M_MONO_ADC_L2_SFT 13 353#define RT5645_MONO_ADC_L1_SRC_MASK (0x1 << 12) 354#define RT5645_MONO_ADC_L1_SRC_SFT 12 355#define RT5645_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12) 356#define RT5645_MONO_ADC_L1_SRC_ADCL (0x1 << 12) 357#define RT5645_MONO_ADC_L2_SRC_MASK (0x1 << 11) 358#define RT5645_MONO_ADC_L2_SRC_SFT 11 359#define RT5645_MONO_DMIC_L_SRC_MASK (0x1 << 8) 360#define RT5645_MONO_DMIC_L_SRC_SFT 8 361#define RT5645_M_MONO_ADC_R1 (0x1 << 6) 362#define RT5645_M_MONO_ADC_R1_SFT 6 363#define RT5645_M_MONO_ADC_R2 (0x1 << 5) 364#define RT5645_M_MONO_ADC_R2_SFT 5 365#define RT5645_MONO_ADC_R1_SRC_MASK (0x1 << 4) 366#define RT5645_MONO_ADC_R1_SRC_SFT 4 367#define RT5645_MONO_ADC_R1_SRC_ADCR (0x1 << 4) 368#define RT5645_MONO_ADC_R1_SRC_DACMIXR (0x0 << 4) 369#define RT5645_MONO_ADC_R2_SRC_MASK (0x1 << 3) 370#define RT5645_MONO_ADC_R2_SRC_SFT 3 371#define RT5645_MONO_DMIC_R_SRC_MASK (0x3) 372#define RT5645_MONO_DMIC_R_SRC_SFT 0 373 374/* ADC Mixer to DAC Mixer Control (0x29) */ 375#define RT5645_M_ADCMIX_L (0x1 << 15) 376#define RT5645_M_ADCMIX_L_SFT 15 377#define RT5645_M_DAC1_L (0x1 << 14) 378#define RT5645_M_DAC1_L_SFT 14 379#define RT5645_DAC1_R_SEL_MASK (0x3 << 10) 380#define RT5645_DAC1_R_SEL_SFT 10 381#define RT5645_DAC1_R_SEL_IF1 (0x0 << 10) 382#define RT5645_DAC1_R_SEL_IF2 (0x1 << 10) 383#define RT5645_DAC1_R_SEL_IF3 (0x2 << 10) 384#define RT5645_DAC1_R_SEL_IF4 (0x3 << 10) 385#define RT5645_DAC1_L_SEL_MASK (0x3 << 8) 386#define RT5645_DAC1_L_SEL_SFT 8 387#define RT5645_DAC1_L_SEL_IF1 (0x0 << 8) 388#define RT5645_DAC1_L_SEL_IF2 (0x1 << 8) 389#define RT5645_DAC1_L_SEL_IF3 (0x2 << 8) 390#define RT5645_DAC1_L_SEL_IF4 (0x3 << 8) 391#define RT5645_M_ADCMIX_R (0x1 << 7) 392#define RT5645_M_ADCMIX_R_SFT 7 393#define RT5645_M_DAC1_R (0x1 << 6) 394#define RT5645_M_DAC1_R_SFT 6 395 396/* Stereo DAC Mixer Control (0x2a) */ 397#define RT5645_M_DAC_L1 (0x1 << 14) 398#define RT5645_M_DAC_L1_SFT 14 399#define RT5645_DAC_L1_STO_L_VOL_MASK (0x1 << 13) 400#define RT5645_DAC_L1_STO_L_VOL_SFT 13 401#define RT5645_M_DAC_L2 (0x1 << 12) 402#define RT5645_M_DAC_L2_SFT 12 403#define RT5645_DAC_L2_STO_L_VOL_MASK (0x1 << 11) 404#define RT5645_DAC_L2_STO_L_VOL_SFT 11 405#define RT5645_M_ANC_DAC_L (0x1 << 10) 406#define RT5645_M_ANC_DAC_L_SFT 10 407#define RT5645_M_DAC_R1_STO_L (0x1 << 9) 408#define RT5645_M_DAC_R1_STO_L_SFT 9 409#define RT5645_DAC_R1_STO_L_VOL_MASK (0x1 << 8) 410#define RT5645_DAC_R1_STO_L_VOL_SFT 8 411#define RT5645_M_DAC_R1 (0x1 << 6) 412#define RT5645_M_DAC_R1_SFT 6 413#define RT5645_DAC_R1_STO_R_VOL_MASK (0x1 << 5) 414#define RT5645_DAC_R1_STO_R_VOL_SFT 5 415#define RT5645_M_DAC_R2 (0x1 << 4) 416#define RT5645_M_DAC_R2_SFT 4 417#define RT5645_DAC_R2_STO_R_VOL_MASK (0x1 << 3) 418#define RT5645_DAC_R2_STO_R_VOL_SFT 3 419#define RT5645_M_ANC_DAC_R (0x1 << 2) 420#define RT5645_M_ANC_DAC_R_SFT 2 421#define RT5645_M_DAC_L1_STO_R (0x1 << 1) 422#define RT5645_M_DAC_L1_STO_R_SFT 1 423#define RT5645_DAC_L1_STO_R_VOL_MASK (0x1) 424#define RT5645_DAC_L1_STO_R_VOL_SFT 0 425 426/* Mono DAC Mixer Control (0x2b) */ 427#define RT5645_M_DAC_L1_MONO_L (0x1 << 14) 428#define RT5645_M_DAC_L1_MONO_L_SFT 14 429#define RT5645_DAC_L1_MONO_L_VOL_MASK (0x1 << 13) 430#define RT5645_DAC_L1_MONO_L_VOL_SFT 13 431#define RT5645_M_DAC_L2_MONO_L (0x1 << 12) 432#define RT5645_M_DAC_L2_MONO_L_SFT 12 433#define RT5645_DAC_L2_MONO_L_VOL_MASK (0x1 << 11) 434#define RT5645_DAC_L2_MONO_L_VOL_SFT 11 435#define RT5645_M_DAC_R2_MONO_L (0x1 << 10) 436#define RT5645_M_DAC_R2_MONO_L_SFT 10 437#define RT5645_DAC_R2_MONO_L_VOL_MASK (0x1 << 9) 438#define RT5645_DAC_R2_MONO_L_VOL_SFT 9 439#define RT5645_M_DAC_R1_MONO_R (0x1 << 6) 440#define RT5645_M_DAC_R1_MONO_R_SFT 6 441#define RT5645_DAC_R1_MONO_R_VOL_MASK (0x1 << 5) 442#define RT5645_DAC_R1_MONO_R_VOL_SFT 5 443#define RT5645_M_DAC_R2_MONO_R (0x1 << 4) 444#define RT5645_M_DAC_R2_MONO_R_SFT 4 445#define RT5645_DAC_R2_MONO_R_VOL_MASK (0x1 << 3) 446#define RT5645_DAC_R2_MONO_R_VOL_SFT 3 447#define RT5645_M_DAC_L2_MONO_R (0x1 << 2) 448#define RT5645_M_DAC_L2_MONO_R_SFT 2 449#define RT5645_DAC_L2_MONO_R_VOL_MASK (0x1 << 1) 450#define RT5645_DAC_L2_MONO_R_VOL_SFT 1 451 452/* Digital Mixer Control (0x2c) */ 453#define RT5645_M_STO_L_DAC_L (0x1 << 15) 454#define RT5645_M_STO_L_DAC_L_SFT 15 455#define RT5645_STO_L_DAC_L_VOL_MASK (0x1 << 14) 456#define RT5645_STO_L_DAC_L_VOL_SFT 14 457#define RT5645_M_DAC_L2_DAC_L (0x1 << 13) 458#define RT5645_M_DAC_L2_DAC_L_SFT 13 459#define RT5645_DAC_L2_DAC_L_VOL_MASK (0x1 << 12) 460#define RT5645_DAC_L2_DAC_L_VOL_SFT 12 461#define RT5645_M_STO_R_DAC_R (0x1 << 11) 462#define RT5645_M_STO_R_DAC_R_SFT 11 463#define RT5645_STO_R_DAC_R_VOL_MASK (0x1 << 10) 464#define RT5645_STO_R_DAC_R_VOL_SFT 10 465#define RT5645_M_DAC_R2_DAC_R (0x1 << 9) 466#define RT5645_M_DAC_R2_DAC_R_SFT 9 467#define RT5645_DAC_R2_DAC_R_VOL_MASK (0x1 << 8) 468#define RT5645_DAC_R2_DAC_R_VOL_SFT 8 469#define RT5645_M_DAC_R2_DAC_L (0x1 << 7) 470#define RT5645_M_DAC_R2_DAC_L_SFT 7 471#define RT5645_DAC_R2_DAC_L_VOL_MASK (0x1 << 6) 472#define RT5645_DAC_R2_DAC_L_VOL_SFT 6 473#define RT5645_M_DAC_L2_DAC_R (0x1 << 5) 474#define RT5645_M_DAC_L2_DAC_R_SFT 5 475#define RT5645_DAC_L2_DAC_R_VOL_MASK (0x1 << 4) 476#define RT5645_DAC_L2_DAC_R_VOL_SFT 4 477 478/* Analog DAC1/2 Input Source Control (0x2d) */ 479#define RT5650_A_DAC1_L_IN_SFT 3 480#define RT5650_A_DAC1_R_IN_SFT 2 481#define RT5650_A_DAC2_L_IN_SFT 1 482#define RT5650_A_DAC2_R_IN_SFT 0 483 484/* Digital Interface Data Control (0x2f) */ 485#define RT5645_IF1_ADC2_IN_SEL (0x1 << 15) 486#define RT5645_IF1_ADC2_IN_SFT 15 487#define RT5645_IF2_ADC_IN_MASK (0x7 << 12) 488#define RT5645_IF2_ADC_IN_SFT 12 489#define RT5645_IF2_DAC_SEL_MASK (0x3 << 10) 490#define RT5645_IF2_DAC_SEL_SFT 10 491#define RT5645_IF2_ADC_SEL_MASK (0x3 << 8) 492#define RT5645_IF2_ADC_SEL_SFT 8 493#define RT5645_IF3_DAC_SEL_MASK (0x3 << 6) 494#define RT5645_IF3_DAC_SEL_SFT 6 495#define RT5645_IF3_ADC_SEL_MASK (0x3 << 4) 496#define RT5645_IF3_ADC_SEL_SFT 4 497#define RT5645_IF3_ADC_IN_MASK (0x7) 498#define RT5645_IF3_ADC_IN_SFT 0 499 500/* PDM Output Control (0x31) */ 501#define RT5645_PDM1_L_MASK (0x1 << 15) 502#define RT5645_PDM1_L_SFT 15 503#define RT5645_M_PDM1_L (0x1 << 14) 504#define RT5645_M_PDM1_L_SFT 14 505#define RT5645_PDM1_R_MASK (0x1 << 13) 506#define RT5645_PDM1_R_SFT 13 507#define RT5645_M_PDM1_R (0x1 << 12) 508#define RT5645_M_PDM1_R_SFT 12 509#define RT5645_PDM2_L_MASK (0x1 << 11) 510#define RT5645_PDM2_L_SFT 11 511#define RT5645_M_PDM2_L (0x1 << 10) 512#define RT5645_M_PDM2_L_SFT 10 513#define RT5645_PDM2_R_MASK (0x1 << 9) 514#define RT5645_PDM2_R_SFT 9 515#define RT5645_M_PDM2_R (0x1 << 8) 516#define RT5645_M_PDM2_R_SFT 8 517#define RT5645_PDM2_BUSY (0x1 << 7) 518#define RT5645_PDM1_BUSY (0x1 << 6) 519#define RT5645_PDM_PATTERN (0x1 << 5) 520#define RT5645_PDM_GAIN (0x1 << 4) 521#define RT5645_PDM_DIV_MASK (0x3) 522 523/* REC Left Mixer Control 1 (0x3b) */ 524#define RT5645_G_HP_L_RM_L_MASK (0x7 << 13) 525#define RT5645_G_HP_L_RM_L_SFT 13 526#define RT5645_G_IN_L_RM_L_MASK (0x7 << 10) 527#define RT5645_G_IN_L_RM_L_SFT 10 528#define RT5645_G_BST4_RM_L_MASK (0x7 << 7) 529#define RT5645_G_BST4_RM_L_SFT 7 530#define RT5645_G_BST3_RM_L_MASK (0x7 << 4) 531#define RT5645_G_BST3_RM_L_SFT 4 532#define RT5645_G_BST2_RM_L_MASK (0x7 << 1) 533#define RT5645_G_BST2_RM_L_SFT 1 534 535/* REC Left Mixer Control 2 (0x3c) */ 536#define RT5645_G_BST1_RM_L_MASK (0x7 << 13) 537#define RT5645_G_BST1_RM_L_SFT 13 538#define RT5645_G_OM_L_RM_L_MASK (0x7 << 10) 539#define RT5645_G_OM_L_RM_L_SFT 10 540#define RT5645_M_MM_L_RM_L (0x1 << 6) 541#define RT5645_M_MM_L_RM_L_SFT 6 542#define RT5645_M_IN_L_RM_L (0x1 << 5) 543#define RT5645_M_IN_L_RM_L_SFT 5 544#define RT5645_M_HP_L_RM_L (0x1 << 4) 545#define RT5645_M_HP_L_RM_L_SFT 4 546#define RT5645_M_BST3_RM_L (0x1 << 3) 547#define RT5645_M_BST3_RM_L_SFT 3 548#define RT5645_M_BST2_RM_L (0x1 << 2) 549#define RT5645_M_BST2_RM_L_SFT 2 550#define RT5645_M_BST1_RM_L (0x1 << 1) 551#define RT5645_M_BST1_RM_L_SFT 1 552#define RT5645_M_OM_L_RM_L (0x1) 553#define RT5645_M_OM_L_RM_L_SFT 0 554 555/* REC Right Mixer Control 1 (0x3d) */ 556#define RT5645_G_HP_R_RM_R_MASK (0x7 << 13) 557#define RT5645_G_HP_R_RM_R_SFT 13 558#define RT5645_G_IN_R_RM_R_MASK (0x7 << 10) 559#define RT5645_G_IN_R_RM_R_SFT 10 560#define RT5645_G_BST4_RM_R_MASK (0x7 << 7) 561#define RT5645_G_BST4_RM_R_SFT 7 562#define RT5645_G_BST3_RM_R_MASK (0x7 << 4) 563#define RT5645_G_BST3_RM_R_SFT 4 564#define RT5645_G_BST2_RM_R_MASK (0x7 << 1) 565#define RT5645_G_BST2_RM_R_SFT 1 566 567/* REC Right Mixer Control 2 (0x3e) */ 568#define RT5645_G_BST1_RM_R_MASK (0x7 << 13) 569#define RT5645_G_BST1_RM_R_SFT 13 570#define RT5645_G_OM_R_RM_R_MASK (0x7 << 10) 571#define RT5645_G_OM_R_RM_R_SFT 10 572#define RT5645_M_MM_R_RM_R (0x1 << 6) 573#define RT5645_M_MM_R_RM_R_SFT 6 574#define RT5645_M_IN_R_RM_R (0x1 << 5) 575#define RT5645_M_IN_R_RM_R_SFT 5 576#define RT5645_M_HP_R_RM_R (0x1 << 4) 577#define RT5645_M_HP_R_RM_R_SFT 4 578#define RT5645_M_BST3_RM_R (0x1 << 3) 579#define RT5645_M_BST3_RM_R_SFT 3 580#define RT5645_M_BST2_RM_R (0x1 << 2) 581#define RT5645_M_BST2_RM_R_SFT 2 582#define RT5645_M_BST1_RM_R (0x1 << 1) 583#define RT5645_M_BST1_RM_R_SFT 1 584#define RT5645_M_OM_R_RM_R (0x1) 585#define RT5645_M_OM_R_RM_R_SFT 0 586 587/* HPOMIX Control (0x40) (0x42) */ 588#define RT5645_M_BST1_HV (0x1 << 4) 589#define RT5645_M_BST1_HV_SFT 4 590#define RT5645_M_BST2_HV (0x1 << 4) 591#define RT5645_M_BST2_HV_SFT 4 592#define RT5645_M_BST3_HV (0x1 << 3) 593#define RT5645_M_BST3_HV_SFT 3 594#define RT5645_M_IN_HV (0x1 << 2) 595#define RT5645_M_IN_HV_SFT 2 596#define RT5645_M_DAC2_HV (0x1 << 1) 597#define RT5645_M_DAC2_HV_SFT 1 598#define RT5645_M_DAC1_HV (0x1 << 0) 599#define RT5645_M_DAC1_HV_SFT 0 600 601/* HPMIX Control (0x45) */ 602#define RT5645_M_DAC1_HM (0x1 << 14) 603#define RT5645_M_DAC1_HM_SFT 14 604#define RT5645_M_HPVOL_HM (0x1 << 13) 605#define RT5645_M_HPVOL_HM_SFT 13 606#define RT5645_IRQ_PSV_MODE (0x1 << 12) 607 608/* SPK Left Mixer Control (0x46) */ 609#define RT5645_G_RM_L_SM_L_MASK (0x3 << 14) 610#define RT5645_G_RM_L_SM_L_SFT 14 611#define RT5645_G_IN_L_SM_L_MASK (0x3 << 12) 612#define RT5645_G_IN_L_SM_L_SFT 12 613#define RT5645_G_DAC_L1_SM_L_MASK (0x3 << 10) 614#define RT5645_G_DAC_L1_SM_L_SFT 10 615#define RT5645_G_DAC_L2_SM_L_MASK (0x3 << 8) 616#define RT5645_G_DAC_L2_SM_L_SFT 8 617#define RT5645_G_OM_L_SM_L_MASK (0x3 << 6) 618#define RT5645_G_OM_L_SM_L_SFT 6 619#define RT5645_M_BST1_L_SM_L (0x1 << 5) 620#define RT5645_M_BST1_L_SM_L_SFT 5 621#define RT5645_M_IN_L_SM_L (0x1 << 3) 622#define RT5645_M_IN_L_SM_L_SFT 3 623#define RT5645_M_DAC_L1_SM_L (0x1 << 1) 624#define RT5645_M_DAC_L1_SM_L_SFT 1 625#define RT5645_M_DAC_L2_SM_L (0x1 << 2) 626#define RT5645_M_DAC_L2_SM_L_SFT 2 627#define RT5645_M_BST3_L_SM_L (0x1 << 4) 628#define RT5645_M_BST3_L_SM_L_SFT 4 629 630/* SPK Right Mixer Control (0x47) */ 631#define RT5645_G_RM_R_SM_R_MASK (0x3 << 14) 632#define RT5645_G_RM_R_SM_R_SFT 14 633#define RT5645_G_IN_R_SM_R_MASK (0x3 << 12) 634#define RT5645_G_IN_R_SM_R_SFT 12 635#define RT5645_G_DAC_R1_SM_R_MASK (0x3 << 10) 636#define RT5645_G_DAC_R1_SM_R_SFT 10 637#define RT5645_G_DAC_R2_SM_R_MASK (0x3 << 8) 638#define RT5645_G_DAC_R2_SM_R_SFT 8 639#define RT5645_G_OM_R_SM_R_MASK (0x3 << 6) 640#define RT5645_G_OM_R_SM_R_SFT 6 641#define RT5645_M_BST2_R_SM_R (0x1 << 5) 642#define RT5645_M_BST2_R_SM_R_SFT 5 643#define RT5645_M_IN_R_SM_R (0x1 << 3) 644#define RT5645_M_IN_R_SM_R_SFT 3 645#define RT5645_M_DAC_R1_SM_R (0x1 << 1) 646#define RT5645_M_DAC_R1_SM_R_SFT 1 647#define RT5645_M_DAC_R2_SM_R (0x1 << 2) 648#define RT5645_M_DAC_R2_SM_R_SFT 2 649#define RT5645_M_BST3_R_SM_R (0x1 << 4) 650#define RT5645_M_BST3_R_SM_R_SFT 4 651 652/* SPOLMIX Control (0x48) */ 653#define RT5645_M_DAC_L1_SPM_L (0x1 << 15) 654#define RT5645_M_DAC_L1_SPM_L_SFT 15 655#define RT5645_M_DAC_R1_SPM_L (0x1 << 14) 656#define RT5645_M_DAC_R1_SPM_L_SFT 14 657#define RT5645_M_SV_L_SPM_L (0x1 << 13) 658#define RT5645_M_SV_L_SPM_L_SFT 13 659#define RT5645_M_SV_R_SPM_L (0x1 << 12) 660#define RT5645_M_SV_R_SPM_L_SFT 12 661#define RT5645_M_BST3_SPM_L (0x1 << 11) 662#define RT5645_M_BST3_SPM_L_SFT 11 663#define RT5645_M_DAC_R1_SPM_R (0x1 << 2) 664#define RT5645_M_DAC_R1_SPM_R_SFT 2 665#define RT5645_M_BST3_SPM_R (0x1 << 1) 666#define RT5645_M_BST3_SPM_R_SFT 1 667#define RT5645_M_SV_R_SPM_R (0x1 << 0) 668#define RT5645_M_SV_R_SPM_R_SFT 0 669 670/* Mono Output Mixer Control (0x4c) */ 671#define RT5645_M_OV_L_MM (0x1 << 9) 672#define RT5645_M_OV_L_MM_SFT 9 673#define RT5645_M_DAC_L2_MA (0x1 << 8) 674#define RT5645_M_DAC_L2_MA_SFT 8 675#define RT5645_G_MONOMIX_MASK (0x1 << 10) 676#define RT5645_G_MONOMIX_SFT 10 677#define RT5645_M_BST2_MM (0x1 << 4) 678#define RT5645_M_BST2_MM_SFT 4 679#define RT5645_M_DAC_R1_MM (0x1 << 3) 680#define RT5645_M_DAC_R1_MM_SFT 3 681#define RT5645_M_DAC_R2_MM (0x1 << 2) 682#define RT5645_M_DAC_R2_MM_SFT 2 683#define RT5645_M_DAC_L2_MM (0x1 << 1) 684#define RT5645_M_DAC_L2_MM_SFT 1 685#define RT5645_M_BST3_MM (0x1 << 0) 686#define RT5645_M_BST3_MM_SFT 0 687 688/* Output Left Mixer Control 1 (0x4d) */ 689#define RT5645_G_BST3_OM_L_MASK (0x7 << 13) 690#define RT5645_G_BST3_OM_L_SFT 13 691#define RT5645_G_BST2_OM_L_MASK (0x7 << 10) 692#define RT5645_G_BST2_OM_L_SFT 10 693#define RT5645_G_BST1_OM_L_MASK (0x7 << 7) 694#define RT5645_G_BST1_OM_L_SFT 7 695#define RT5645_G_IN_L_OM_L_MASK (0x7 << 4) 696#define RT5645_G_IN_L_OM_L_SFT 4 697#define RT5645_G_RM_L_OM_L_MASK (0x7 << 1) 698#define RT5645_G_RM_L_OM_L_SFT 1 699 700/* Output Left Mixer Control 2 (0x4e) */ 701#define RT5645_G_DAC_R2_OM_L_MASK (0x7 << 13) 702#define RT5645_G_DAC_R2_OM_L_SFT 13 703#define RT5645_G_DAC_L2_OM_L_MASK (0x7 << 10) 704#define RT5645_G_DAC_L2_OM_L_SFT 10 705#define RT5645_G_DAC_L1_OM_L_MASK (0x7 << 7) 706#define RT5645_G_DAC_L1_OM_L_SFT 7 707 708/* Output Left Mixer Control 3 (0x4f) */ 709#define RT5645_M_BST3_OM_L (0x1 << 4) 710#define RT5645_M_BST3_OM_L_SFT 4 711#define RT5645_M_BST1_OM_L (0x1 << 3) 712#define RT5645_M_BST1_OM_L_SFT 3 713#define RT5645_M_IN_L_OM_L (0x1 << 2) 714#define RT5645_M_IN_L_OM_L_SFT 2 715#define RT5645_M_DAC_L2_OM_L (0x1 << 1) 716#define RT5645_M_DAC_L2_OM_L_SFT 1 717#define RT5645_M_DAC_L1_OM_L (0x1) 718#define RT5645_M_DAC_L1_OM_L_SFT 0 719 720/* Output Right Mixer Control 1 (0x50) */ 721#define RT5645_G_BST4_OM_R_MASK (0x7 << 13) 722#define RT5645_G_BST4_OM_R_SFT 13 723#define RT5645_G_BST2_OM_R_MASK (0x7 << 10) 724#define RT5645_G_BST2_OM_R_SFT 10 725#define RT5645_G_BST1_OM_R_MASK (0x7 << 7) 726#define RT5645_G_BST1_OM_R_SFT 7 727#define RT5645_G_IN_R_OM_R_MASK (0x7 << 4) 728#define RT5645_G_IN_R_OM_R_SFT 4 729#define RT5645_G_RM_R_OM_R_MASK (0x7 << 1) 730#define RT5645_G_RM_R_OM_R_SFT 1 731 732/* Output Right Mixer Control 2 (0x51) */ 733#define RT5645_G_DAC_L2_OM_R_MASK (0x7 << 13) 734#define RT5645_G_DAC_L2_OM_R_SFT 13 735#define RT5645_G_DAC_R2_OM_R_MASK (0x7 << 10) 736#define RT5645_G_DAC_R2_OM_R_SFT 10 737#define RT5645_G_DAC_R1_OM_R_MASK (0x7 << 7) 738#define RT5645_G_DAC_R1_OM_R_SFT 7 739 740/* Output Right Mixer Control 3 (0x52) */ 741#define RT5645_M_BST3_OM_R (0x1 << 4) 742#define RT5645_M_BST3_OM_R_SFT 4 743#define RT5645_M_BST2_OM_R (0x1 << 3) 744#define RT5645_M_BST2_OM_R_SFT 3 745#define RT5645_M_IN_R_OM_R (0x1 << 2) 746#define RT5645_M_IN_R_OM_R_SFT 2 747#define RT5645_M_DAC_R2_OM_R (0x1 << 1) 748#define RT5645_M_DAC_R2_OM_R_SFT 1 749#define RT5645_M_DAC_R1_OM_R (0x1) 750#define RT5645_M_DAC_R1_OM_R_SFT 0 751 752/* LOUT Mixer Control (0x53) */ 753#define RT5645_M_DAC_L1_LM (0x1 << 15) 754#define RT5645_M_DAC_L1_LM_SFT 15 755#define RT5645_M_DAC_R1_LM (0x1 << 14) 756#define RT5645_M_DAC_R1_LM_SFT 14 757#define RT5645_M_OV_L_LM (0x1 << 13) 758#define RT5645_M_OV_L_LM_SFT 13 759#define RT5645_M_OV_R_LM (0x1 << 12) 760#define RT5645_M_OV_R_LM_SFT 12 761#define RT5645_G_LOUTMIX_MASK (0x1 << 11) 762#define RT5645_G_LOUTMIX_SFT 11 763 764/* Power Management for Digital 1 (0x61) */ 765#define RT5645_PWR_I2S1 (0x1 << 15) 766#define RT5645_PWR_I2S1_BIT 15 767#define RT5645_PWR_I2S2 (0x1 << 14) 768#define RT5645_PWR_I2S2_BIT 14 769#define RT5645_PWR_I2S3 (0x1 << 13) 770#define RT5645_PWR_I2S3_BIT 13 771#define RT5645_PWR_DAC_L1 (0x1 << 12) 772#define RT5645_PWR_DAC_L1_BIT 12 773#define RT5645_PWR_DAC_R1 (0x1 << 11) 774#define RT5645_PWR_DAC_R1_BIT 11 775#define RT5645_PWR_CLS_D_R (0x1 << 9) 776#define RT5645_PWR_CLS_D_R_BIT 9 777#define RT5645_PWR_CLS_D_L (0x1 << 8) 778#define RT5645_PWR_CLS_D_L_BIT 8 779#define RT5645_PWR_ADC_R (0x1 << 1) 780#define RT5645_PWR_ADC_R_BIT 1 781#define RT5645_PWR_DAC_L2 (0x1 << 7) 782#define RT5645_PWR_DAC_L2_BIT 7 783#define RT5645_PWR_DAC_R2 (0x1 << 6) 784#define RT5645_PWR_DAC_R2_BIT 6 785#define RT5645_PWR_ADC_L (0x1 << 2) 786#define RT5645_PWR_ADC_L_BIT 2 787#define RT5645_PWR_ADC_R (0x1 << 1) 788#define RT5645_PWR_ADC_R_BIT 1 789#define RT5645_PWR_CLS_D (0x1) 790#define RT5645_PWR_CLS_D_BIT 0 791 792/* Power Management for Digital 2 (0x62) */ 793#define RT5645_PWR_ADC_S1F (0x1 << 15) 794#define RT5645_PWR_ADC_S1F_BIT 15 795#define RT5645_PWR_ADC_MF_L (0x1 << 14) 796#define RT5645_PWR_ADC_MF_L_BIT 14 797#define RT5645_PWR_ADC_MF_R (0x1 << 13) 798#define RT5645_PWR_ADC_MF_R_BIT 13 799#define RT5645_PWR_I2S_DSP (0x1 << 12) 800#define RT5645_PWR_I2S_DSP_BIT 12 801#define RT5645_PWR_DAC_S1F (0x1 << 11) 802#define RT5645_PWR_DAC_S1F_BIT 11 803#define RT5645_PWR_DAC_MF_L (0x1 << 10) 804#define RT5645_PWR_DAC_MF_L_BIT 10 805#define RT5645_PWR_DAC_MF_R (0x1 << 9) 806#define RT5645_PWR_DAC_MF_R_BIT 9 807#define RT5645_PWR_PDM1 (0x1 << 7) 808#define RT5645_PWR_PDM1_BIT 7 809#define RT5645_PWR_PDM2 (0x1 << 6) 810#define RT5645_PWR_PDM2_BIT 6 811#define RT5645_PWR_IPTV (0x1 << 1) 812#define RT5645_PWR_IPTV_BIT 1 813#define RT5645_PWR_PAD (0x1) 814#define RT5645_PWR_PAD_BIT 0 815 816/* Power Management for Analog 1 (0x63) */ 817#define RT5645_PWR_VREF1 (0x1 << 15) 818#define RT5645_PWR_VREF1_BIT 15 819#define RT5645_PWR_FV1 (0x1 << 14) 820#define RT5645_PWR_FV1_BIT 14 821#define RT5645_PWR_MB (0x1 << 13) 822#define RT5645_PWR_MB_BIT 13 823#define RT5645_PWR_LM (0x1 << 12) 824#define RT5645_PWR_LM_BIT 12 825#define RT5645_PWR_BG (0x1 << 11) 826#define RT5645_PWR_BG_BIT 11 827#define RT5645_PWR_MA (0x1 << 10) 828#define RT5645_PWR_MA_BIT 10 829#define RT5645_PWR_HP_L (0x1 << 7) 830#define RT5645_PWR_HP_L_BIT 7 831#define RT5645_PWR_HP_R (0x1 << 6) 832#define RT5645_PWR_HP_R_BIT 6 833#define RT5645_PWR_HA (0x1 << 5) 834#define RT5645_PWR_HA_BIT 5 835#define RT5645_PWR_VREF2 (0x1 << 4) 836#define RT5645_PWR_VREF2_BIT 4 837#define RT5645_PWR_FV2 (0x1 << 3) 838#define RT5645_PWR_FV2_BIT 3 839#define RT5645_LDO_SEL_MASK (0x3) 840#define RT5645_LDO_SEL_SFT 0 841 842/* Power Management for Analog 2 (0x64) */ 843#define RT5645_PWR_BST1 (0x1 << 15) 844#define RT5645_PWR_BST1_BIT 15 845#define RT5645_PWR_BST2 (0x1 << 14) 846#define RT5645_PWR_BST2_BIT 14 847#define RT5645_PWR_BST3 (0x1 << 13) 848#define RT5645_PWR_BST3_BIT 13 849#define RT5645_PWR_BST4 (0x1 << 12) 850#define RT5645_PWR_BST4_BIT 12 851#define RT5645_PWR_MB1 (0x1 << 11) 852#define RT5645_PWR_MB1_BIT 11 853#define RT5645_PWR_MB2 (0x1 << 10) 854#define RT5645_PWR_MB2_BIT 10 855#define RT5645_PWR_PLL (0x1 << 9) 856#define RT5645_PWR_PLL_BIT 9 857#define RT5645_PWR_BST2_P (0x1 << 5) 858#define RT5645_PWR_BST2_P_BIT 5 859#define RT5645_PWR_BST3_P (0x1 << 4) 860#define RT5645_PWR_BST3_P_BIT 4 861#define RT5645_PWR_BST4_P (0x1 << 3) 862#define RT5645_PWR_BST4_P_BIT 3 863#define RT5645_PWR_JD1 (0x1 << 2) 864#define RT5645_PWR_JD1_BIT 2 865#define RT5645_PWR_JD (0x1 << 1) 866#define RT5645_PWR_JD_BIT 1 867 868/* Power Management for Mixer (0x65) */ 869#define RT5645_PWR_OM_L (0x1 << 15) 870#define RT5645_PWR_OM_L_BIT 15 871#define RT5645_PWR_OM_R (0x1 << 14) 872#define RT5645_PWR_OM_R_BIT 14 873#define RT5645_PWR_SM_L (0x1 << 13) 874#define RT5645_PWR_SM_L_BIT 13 875#define RT5645_PWR_SM_R (0x1 << 12) 876#define RT5645_PWR_SM_R_BIT 12 877#define RT5645_PWR_RM_L (0x1 << 11) 878#define RT5645_PWR_RM_L_BIT 11 879#define RT5645_PWR_RM_R (0x1 << 10) 880#define RT5645_PWR_RM_R_BIT 10 881#define RT5645_PWR_MM (0x1 << 8) 882#define RT5645_PWR_MM_BIT 8 883#define RT5645_PWR_HM_L (0x1 << 7) 884#define RT5645_PWR_HM_L_BIT 7 885#define RT5645_PWR_HM_R (0x1 << 6) 886#define RT5645_PWR_HM_R_BIT 6 887#define RT5645_PWR_LDO2 (0x1 << 1) 888#define RT5645_PWR_LDO2_BIT 1 889 890/* Power Management for Volume (0x66) */ 891#define RT5645_PWR_SV_L (0x1 << 15) 892#define RT5645_PWR_SV_L_BIT 15 893#define RT5645_PWR_SV_R (0x1 << 14) 894#define RT5645_PWR_SV_R_BIT 14 895#define RT5645_PWR_HV_L (0x1 << 11) 896#define RT5645_PWR_HV_L_BIT 11 897#define RT5645_PWR_HV_R (0x1 << 10) 898#define RT5645_PWR_HV_R_BIT 10 899#define RT5645_PWR_IN_L (0x1 << 9) 900#define RT5645_PWR_IN_L_BIT 9 901#define RT5645_PWR_IN_R (0x1 << 8) 902#define RT5645_PWR_IN_R_BIT 8 903#define RT5645_PWR_MIC_DET (0x1 << 5) 904#define RT5645_PWR_MIC_DET_BIT 5 905 906/* I2S1/2 Audio Serial Data Port Control (0x70 0x71) */ 907#define RT5645_I2S_MS_MASK (0x1 << 15) 908#define RT5645_I2S_MS_SFT 15 909#define RT5645_I2S_MS_M (0x0 << 15) 910#define RT5645_I2S_MS_S (0x1 << 15) 911#define RT5645_I2S_O_CP_MASK (0x3 << 10) 912#define RT5645_I2S_O_CP_SFT 10 913#define RT5645_I2S_O_CP_OFF (0x0 << 10) 914#define RT5645_I2S_O_CP_U_LAW (0x1 << 10) 915#define RT5645_I2S_O_CP_A_LAW (0x2 << 10) 916#define RT5645_I2S_I_CP_MASK (0x3 << 8) 917#define RT5645_I2S_I_CP_SFT 8 918#define RT5645_I2S_I_CP_OFF (0x0 << 8) 919#define RT5645_I2S_I_CP_U_LAW (0x1 << 8) 920#define RT5645_I2S_I_CP_A_LAW (0x2 << 8) 921#define RT5645_I2S_BP_MASK (0x1 << 7) 922#define RT5645_I2S_BP_SFT 7 923#define RT5645_I2S_BP_NOR (0x0 << 7) 924#define RT5645_I2S_BP_INV (0x1 << 7) 925#define RT5645_I2S_DL_MASK (0x3 << 2) 926#define RT5645_I2S_DL_SFT 2 927#define RT5645_I2S_DL_16 (0x0 << 2) 928#define RT5645_I2S_DL_20 (0x1 << 2) 929#define RT5645_I2S_DL_24 (0x2 << 2) 930#define RT5645_I2S_DL_8 (0x3 << 2) 931#define RT5645_I2S_DF_MASK (0x3) 932#define RT5645_I2S_DF_SFT 0 933#define RT5645_I2S_DF_I2S (0x0) 934#define RT5645_I2S_DF_LEFT (0x1) 935#define RT5645_I2S_DF_PCM_A (0x2) 936#define RT5645_I2S_DF_PCM_B (0x3) 937 938/* I2S2 Audio Serial Data Port Control (0x71) */ 939#define RT5645_I2S2_SDI_MASK (0x1 << 6) 940#define RT5645_I2S2_SDI_SFT 6 941#define RT5645_I2S2_SDI_I2S1 (0x0 << 6) 942#define RT5645_I2S2_SDI_I2S2 (0x1 << 6) 943 944/* ADC/DAC Clock Control 1 (0x73) */ 945#define RT5645_I2S_BCLK_MS1_MASK (0x1 << 15) 946#define RT5645_I2S_BCLK_MS1_SFT 15 947#define RT5645_I2S_BCLK_MS1_32 (0x0 << 15) 948#define RT5645_I2S_BCLK_MS1_64 (0x1 << 15) 949#define RT5645_I2S_PD1_MASK (0x7 << 12) 950#define RT5645_I2S_PD1_SFT 12 951#define RT5645_I2S_PD1_1 (0x0 << 12) 952#define RT5645_I2S_PD1_2 (0x1 << 12) 953#define RT5645_I2S_PD1_3 (0x2 << 12) 954#define RT5645_I2S_PD1_4 (0x3 << 12) 955#define RT5645_I2S_PD1_6 (0x4 << 12) 956#define RT5645_I2S_PD1_8 (0x5 << 12) 957#define RT5645_I2S_PD1_12 (0x6 << 12) 958#define RT5645_I2S_PD1_16 (0x7 << 12) 959#define RT5645_I2S_BCLK_MS2_MASK (0x1 << 11) 960#define RT5645_I2S_BCLK_MS2_SFT 11 961#define RT5645_I2S_BCLK_MS2_32 (0x0 << 11) 962#define RT5645_I2S_BCLK_MS2_64 (0x1 << 11) 963#define RT5645_I2S_PD2_MASK (0x7 << 8) 964#define RT5645_I2S_PD2_SFT 8 965#define RT5645_I2S_PD2_1 (0x0 << 8) 966#define RT5645_I2S_PD2_2 (0x1 << 8) 967#define RT5645_I2S_PD2_3 (0x2 << 8) 968#define RT5645_I2S_PD2_4 (0x3 << 8) 969#define RT5645_I2S_PD2_6 (0x4 << 8) 970#define RT5645_I2S_PD2_8 (0x5 << 8) 971#define RT5645_I2S_PD2_12 (0x6 << 8) 972#define RT5645_I2S_PD2_16 (0x7 << 8) 973#define RT5645_I2S_BCLK_MS3_MASK (0x1 << 7) 974#define RT5645_I2S_BCLK_MS3_SFT 7 975#define RT5645_I2S_BCLK_MS3_32 (0x0 << 7) 976#define RT5645_I2S_BCLK_MS3_64 (0x1 << 7) 977#define RT5645_I2S_PD3_MASK (0x7 << 4) 978#define RT5645_I2S_PD3_SFT 4 979#define RT5645_I2S_PD3_1 (0x0 << 4) 980#define RT5645_I2S_PD3_2 (0x1 << 4) 981#define RT5645_I2S_PD3_3 (0x2 << 4) 982#define RT5645_I2S_PD3_4 (0x3 << 4) 983#define RT5645_I2S_PD3_6 (0x4 << 4) 984#define RT5645_I2S_PD3_8 (0x5 << 4) 985#define RT5645_I2S_PD3_12 (0x6 << 4) 986#define RT5645_I2S_PD3_16 (0x7 << 4) 987#define RT5645_DAC_OSR_MASK (0x3 << 2) 988#define RT5645_DAC_OSR_SFT 2 989#define RT5645_DAC_OSR_128 (0x0 << 2) 990#define RT5645_DAC_OSR_64 (0x1 << 2) 991#define RT5645_DAC_OSR_32 (0x2 << 2) 992#define RT5645_DAC_OSR_16 (0x3 << 2) 993#define RT5645_ADC_OSR_MASK (0x3) 994#define RT5645_ADC_OSR_SFT 0 995#define RT5645_ADC_OSR_128 (0x0) 996#define RT5645_ADC_OSR_64 (0x1) 997#define RT5645_ADC_OSR_32 (0x2) 998#define RT5645_ADC_OSR_16 (0x3) 999 1000/* ADC/DAC Clock Control 2 (0x74) */ 1001#define RT5645_DAC_L_OSR_MASK (0x3 << 14) 1002#define RT5645_DAC_L_OSR_SFT 14 1003#define RT5645_DAC_L_OSR_128 (0x0 << 14) 1004#define RT5645_DAC_L_OSR_64 (0x1 << 14) 1005#define RT5645_DAC_L_OSR_32 (0x2 << 14) 1006#define RT5645_DAC_L_OSR_16 (0x3 << 14) 1007#define RT5645_ADC_R_OSR_MASK (0x3 << 12) 1008#define RT5645_ADC_R_OSR_SFT 12 1009#define RT5645_ADC_R_OSR_128 (0x0 << 12) 1010#define RT5645_ADC_R_OSR_64 (0x1 << 12) 1011#define RT5645_ADC_R_OSR_32 (0x2 << 12) 1012#define RT5645_ADC_R_OSR_16 (0x3 << 12) 1013#define RT5645_DAHPF_EN (0x1 << 11) 1014#define RT5645_DAHPF_EN_SFT 11 1015#define RT5645_ADHPF_EN (0x1 << 10) 1016#define RT5645_ADHPF_EN_SFT 10 1017 1018/* Digital Microphone Control (0x75) */ 1019#define RT5645_DMIC_1_EN_MASK (0x1 << 15) 1020#define RT5645_DMIC_1_EN_SFT 15 1021#define RT5645_DMIC_1_DIS (0x0 << 15) 1022#define RT5645_DMIC_1_EN (0x1 << 15) 1023#define RT5645_DMIC_2_EN_MASK (0x1 << 14) 1024#define RT5645_DMIC_2_EN_SFT 14 1025#define RT5645_DMIC_2_DIS (0x0 << 14) 1026#define RT5645_DMIC_2_EN (0x1 << 14) 1027#define RT5645_DMIC_1L_LH_MASK (0x1 << 13) 1028#define RT5645_DMIC_1L_LH_SFT 13 1029#define RT5645_DMIC_1L_LH_FALLING (0x0 << 13) 1030#define RT5645_DMIC_1L_LH_RISING (0x1 << 13) 1031#define RT5645_DMIC_1R_LH_MASK (0x1 << 12) 1032#define RT5645_DMIC_1R_LH_SFT 12 1033#define RT5645_DMIC_1R_LH_FALLING (0x0 << 12) 1034#define RT5645_DMIC_1R_LH_RISING (0x1 << 12) 1035#define RT5645_DMIC_2_DP_MASK (0x3 << 10) 1036#define RT5645_DMIC_2_DP_SFT 10 1037#define RT5645_DMIC_2_DP_GPIO6 (0x0 << 10) 1038#define RT5645_DMIC_2_DP_GPIO10 (0x1 << 10) 1039#define RT5645_DMIC_2_DP_GPIO12 (0x2 << 10) 1040#define RT5645_DMIC_2_DP_IN2P (0x3 << 10) 1041#define RT5645_DMIC_2L_LH_MASK (0x1 << 9) 1042#define RT5645_DMIC_2L_LH_SFT 9 1043#define RT5645_DMIC_2L_LH_FALLING (0x0 << 9) 1044#define RT5645_DMIC_2L_LH_RISING (0x1 << 9) 1045#define RT5645_DMIC_2R_LH_MASK (0x1 << 8) 1046#define RT5645_DMIC_2R_LH_SFT 8 1047#define RT5645_DMIC_2R_LH_FALLING (0x0 << 8) 1048#define RT5645_DMIC_2R_LH_RISING (0x1 << 8) 1049#define RT5645_DMIC_CLK_MASK (0x7 << 5) 1050#define RT5645_DMIC_CLK_SFT 5 1051#define RT5645_DMIC_3_EN_MASK (0x1 << 4) 1052#define RT5645_DMIC_3_EN_SFT 4 1053#define RT5645_DMIC_3_DIS (0x0 << 4) 1054#define RT5645_DMIC_3_EN (0x1 << 4) 1055#define RT5645_DMIC_1_DP_MASK (0x3 << 0) 1056#define RT5645_DMIC_1_DP_SFT 0 1057#define RT5645_DMIC_1_DP_GPIO5 (0x0 << 0) 1058#define RT5645_DMIC_1_DP_IN2N (0x1 << 0) 1059#define RT5645_DMIC_1_DP_GPIO11 (0x2 << 0) 1060 1061/* TDM Control 1 (0x77) */ 1062#define RT5645_IF1_ADC_IN_MASK (0x3 << 8) 1063#define RT5645_IF1_ADC_IN_SFT 8 1064 1065/* Global Clock Control (0x80) */ 1066#define RT5645_SCLK_SRC_MASK (0x3 << 14) 1067#define RT5645_SCLK_SRC_SFT 14 1068#define RT5645_SCLK_SRC_MCLK (0x0 << 14) 1069#define RT5645_SCLK_SRC_PLL1 (0x1 << 14) 1070#define RT5645_SCLK_SRC_RCCLK (0x2 << 14) /* 15MHz */ 1071#define RT5645_PLL1_SRC_MASK (0x3 << 12) 1072#define RT5645_PLL1_SRC_SFT 12 1073#define RT5645_PLL1_SRC_MCLK (0x0 << 12) 1074#define RT5645_PLL1_SRC_BCLK1 (0x1 << 12) 1075#define RT5645_PLL1_SRC_BCLK2 (0x2 << 12) 1076#define RT5645_PLL1_SRC_BCLK3 (0x3 << 12) 1077#define RT5645_PLL1_PD_MASK (0x1 << 3) 1078#define RT5645_PLL1_PD_SFT 3 1079#define RT5645_PLL1_PD_1 (0x0 << 3) 1080#define RT5645_PLL1_PD_2 (0x1 << 3) 1081 1082#define RT5645_PLL_INP_MAX 40000000 1083#define RT5645_PLL_INP_MIN 256000 1084/* PLL M/N/K Code Control 1 (0x81) */ 1085#define RT5645_PLL_N_MAX 0x1ff 1086#define RT5645_PLL_N_MASK (RT5645_PLL_N_MAX << 7) 1087#define RT5645_PLL_N_SFT 7 1088#define RT5645_PLL_K_MAX 0x1f 1089#define RT5645_PLL_K_MASK (RT5645_PLL_K_MAX) 1090#define RT5645_PLL_K_SFT 0 1091 1092/* PLL M/N/K Code Control 2 (0x82) */ 1093#define RT5645_PLL_M_MAX 0xf 1094#define RT5645_PLL_M_MASK (RT5645_PLL_M_MAX << 12) 1095#define RT5645_PLL_M_SFT 12 1096#define RT5645_PLL_M_BP (0x1 << 11) 1097#define RT5645_PLL_M_BP_SFT 11 1098 1099/* ASRC Control 1 (0x83) */ 1100#define RT5645_STO_T_MASK (0x1 << 15) 1101#define RT5645_STO_T_SFT 15 1102#define RT5645_STO_T_SCLK (0x0 << 15) 1103#define RT5645_STO_T_LRCK1 (0x1 << 15) 1104#define RT5645_M1_T_MASK (0x1 << 14) 1105#define RT5645_M1_T_SFT 14 1106#define RT5645_M1_T_I2S2 (0x0 << 14) 1107#define RT5645_M1_T_I2S2_D3 (0x1 << 14) 1108#define RT5645_I2S2_F_MASK (0x1 << 12) 1109#define RT5645_I2S2_F_SFT 12 1110#define RT5645_I2S2_F_I2S2_D2 (0x0 << 12) 1111#define RT5645_I2S2_F_I2S1_TCLK (0x1 << 12) 1112#define RT5645_DMIC_1_M_MASK (0x1 << 9) 1113#define RT5645_DMIC_1_M_SFT 9 1114#define RT5645_DMIC_1_M_NOR (0x0 << 9) 1115#define RT5645_DMIC_1_M_ASYN (0x1 << 9) 1116#define RT5645_DMIC_2_M_MASK (0x1 << 8) 1117#define RT5645_DMIC_2_M_SFT 8 1118#define RT5645_DMIC_2_M_NOR (0x0 << 8) 1119#define RT5645_DMIC_2_M_ASYN (0x1 << 8) 1120 1121/* ASRC clock source selection (0x84, 0x85) */ 1122#define RT5645_CLK_SEL_SYS (0x0) 1123#define RT5645_CLK_SEL_I2S1_ASRC (0x1) 1124#define RT5645_CLK_SEL_I2S2_ASRC (0x2) 1125#define RT5645_CLK_SEL_SYS2 (0x5) 1126 1127/* ASRC Control 2 (0x84) */ 1128#define RT5645_DA_STO_CLK_SEL_MASK (0xf << 12) 1129#define RT5645_DA_STO_CLK_SEL_SFT 12 1130#define RT5645_DA_MONOL_CLK_SEL_MASK (0xf << 8) 1131#define RT5645_DA_MONOL_CLK_SEL_SFT 8 1132#define RT5645_DA_MONOR_CLK_SEL_MASK (0xf << 4) 1133#define RT5645_DA_MONOR_CLK_SEL_SFT 4 1134#define RT5645_AD_STO1_CLK_SEL_MASK (0xf << 0) 1135#define RT5645_AD_STO1_CLK_SEL_SFT 0 1136 1137/* ASRC Control 3 (0x85) */ 1138#define RT5645_AD_MONOL_CLK_SEL_MASK (0xf << 4) 1139#define RT5645_AD_MONOL_CLK_SEL_SFT 4 1140#define RT5645_AD_MONOR_CLK_SEL_MASK (0xf << 0) 1141#define RT5645_AD_MONOR_CLK_SEL_SFT 0 1142 1143/* ASRC Control 4 (0x89) */ 1144#define RT5645_I2S1_PD_MASK (0x7 << 12) 1145#define RT5645_I2S1_PD_SFT 12 1146#define RT5645_I2S2_PD_MASK (0x7 << 8) 1147#define RT5645_I2S2_PD_SFT 8 1148 1149/* HPOUT Over Current Detection (0x8b) */ 1150#define RT5645_HP_OVCD_MASK (0x1 << 10) 1151#define RT5645_HP_OVCD_SFT 10 1152#define RT5645_HP_OVCD_DIS (0x0 << 10) 1153#define RT5645_HP_OVCD_EN (0x1 << 10) 1154#define RT5645_HP_OC_TH_MASK (0x3 << 8) 1155#define RT5645_HP_OC_TH_SFT 8 1156#define RT5645_HP_OC_TH_90 (0x0 << 8) 1157#define RT5645_HP_OC_TH_105 (0x1 << 8) 1158#define RT5645_HP_OC_TH_120 (0x2 << 8) 1159#define RT5645_HP_OC_TH_135 (0x3 << 8) 1160 1161/* Class D Over Current Control (0x8c) */ 1162#define RT5645_CLSD_OC_MASK (0x1 << 9) 1163#define RT5645_CLSD_OC_SFT 9 1164#define RT5645_CLSD_OC_PU (0x0 << 9) 1165#define RT5645_CLSD_OC_PD (0x1 << 9) 1166#define RT5645_AUTO_PD_MASK (0x1 << 8) 1167#define RT5645_AUTO_PD_SFT 8 1168#define RT5645_AUTO_PD_DIS (0x0 << 8) 1169#define RT5645_AUTO_PD_EN (0x1 << 8) 1170#define RT5645_CLSD_OC_TH_MASK (0x3f) 1171#define RT5645_CLSD_OC_TH_SFT 0 1172 1173/* Class D Output Control (0x8d) */ 1174#define RT5645_CLSD_RATIO_MASK (0xf << 12) 1175#define RT5645_CLSD_RATIO_SFT 12 1176#define RT5645_CLSD_OM_MASK (0x1 << 11) 1177#define RT5645_CLSD_OM_SFT 11 1178#define RT5645_CLSD_OM_MONO (0x0 << 11) 1179#define RT5645_CLSD_OM_STO (0x1 << 11) 1180#define RT5645_CLSD_SCH_MASK (0x1 << 10) 1181#define RT5645_CLSD_SCH_SFT 10 1182#define RT5645_CLSD_SCH_L (0x0 << 10) 1183#define RT5645_CLSD_SCH_S (0x1 << 10) 1184 1185/* Depop Mode Control 1 (0x8e) */ 1186#define RT5645_SMT_TRIG_MASK (0x1 << 15) 1187#define RT5645_SMT_TRIG_SFT 15 1188#define RT5645_SMT_TRIG_DIS (0x0 << 15) 1189#define RT5645_SMT_TRIG_EN (0x1 << 15) 1190#define RT5645_HP_L_SMT_MASK (0x1 << 9) 1191#define RT5645_HP_L_SMT_SFT 9 1192#define RT5645_HP_L_SMT_DIS (0x0 << 9) 1193#define RT5645_HP_L_SMT_EN (0x1 << 9) 1194#define RT5645_HP_R_SMT_MASK (0x1 << 8) 1195#define RT5645_HP_R_SMT_SFT 8 1196#define RT5645_HP_R_SMT_DIS (0x0 << 8) 1197#define RT5645_HP_R_SMT_EN (0x1 << 8) 1198#define RT5645_HP_CD_PD_MASK (0x1 << 7) 1199#define RT5645_HP_CD_PD_SFT 7 1200#define RT5645_HP_CD_PD_DIS (0x0 << 7) 1201#define RT5645_HP_CD_PD_EN (0x1 << 7) 1202#define RT5645_RSTN_MASK (0x1 << 6) 1203#define RT5645_RSTN_SFT 6 1204#define RT5645_RSTN_DIS (0x0 << 6) 1205#define RT5645_RSTN_EN (0x1 << 6) 1206#define RT5645_RSTP_MASK (0x1 << 5) 1207#define RT5645_RSTP_SFT 5 1208#define RT5645_RSTP_DIS (0x0 << 5) 1209#define RT5645_RSTP_EN (0x1 << 5) 1210#define RT5645_HP_CO_MASK (0x1 << 4) 1211#define RT5645_HP_CO_SFT 4 1212#define RT5645_HP_CO_DIS (0x0 << 4) 1213#define RT5645_HP_CO_EN (0x1 << 4) 1214#define RT5645_HP_CP_MASK (0x1 << 3) 1215#define RT5645_HP_CP_SFT 3 1216#define RT5645_HP_CP_PD (0x0 << 3) 1217#define RT5645_HP_CP_PU (0x1 << 3) 1218#define RT5645_HP_SG_MASK (0x1 << 2) 1219#define RT5645_HP_SG_SFT 2 1220#define RT5645_HP_SG_DIS (0x0 << 2) 1221#define RT5645_HP_SG_EN (0x1 << 2) 1222#define RT5645_HP_DP_MASK (0x1 << 1) 1223#define RT5645_HP_DP_SFT 1 1224#define RT5645_HP_DP_PD (0x0 << 1) 1225#define RT5645_HP_DP_PU (0x1 << 1) 1226#define RT5645_HP_CB_MASK (0x1) 1227#define RT5645_HP_CB_SFT 0 1228#define RT5645_HP_CB_PD (0x0) 1229#define RT5645_HP_CB_PU (0x1) 1230 1231/* Depop Mode Control 2 (0x8f) */ 1232#define RT5645_DEPOP_MASK (0x1 << 13) 1233#define RT5645_DEPOP_SFT 13 1234#define RT5645_DEPOP_AUTO (0x0 << 13) 1235#define RT5645_DEPOP_MAN (0x1 << 13) 1236#define RT5645_RAMP_MASK (0x1 << 12) 1237#define RT5645_RAMP_SFT 12 1238#define RT5645_RAMP_DIS (0x0 << 12) 1239#define RT5645_RAMP_EN (0x1 << 12) 1240#define RT5645_BPS_MASK (0x1 << 11) 1241#define RT5645_BPS_SFT 11 1242#define RT5645_BPS_DIS (0x0 << 11) 1243#define RT5645_BPS_EN (0x1 << 11) 1244#define RT5645_FAST_UPDN_MASK (0x1 << 10) 1245#define RT5645_FAST_UPDN_SFT 10 1246#define RT5645_FAST_UPDN_DIS (0x0 << 10) 1247#define RT5645_FAST_UPDN_EN (0x1 << 10) 1248#define RT5645_MRES_MASK (0x3 << 8) 1249#define RT5645_MRES_SFT 8 1250#define RT5645_MRES_15MO (0x0 << 8) 1251#define RT5645_MRES_25MO (0x1 << 8) 1252#define RT5645_MRES_35MO (0x2 << 8) 1253#define RT5645_MRES_45MO (0x3 << 8) 1254#define RT5645_VLO_MASK (0x1 << 7) 1255#define RT5645_VLO_SFT 7 1256#define RT5645_VLO_3V (0x0 << 7) 1257#define RT5645_VLO_32V (0x1 << 7) 1258#define RT5645_DIG_DP_MASK (0x1 << 6) 1259#define RT5645_DIG_DP_SFT 6 1260#define RT5645_DIG_DP_DIS (0x0 << 6) 1261#define RT5645_DIG_DP_EN (0x1 << 6) 1262#define RT5645_DP_TH_MASK (0x3 << 4) 1263#define RT5645_DP_TH_SFT 4 1264 1265/* Depop Mode Control 3 (0x90) */ 1266#define RT5645_CP_SYS_MASK (0x7 << 12) 1267#define RT5645_CP_SYS_SFT 12 1268#define RT5645_CP_FQ1_MASK (0x7 << 8) 1269#define RT5645_CP_FQ1_SFT 8 1270#define RT5645_CP_FQ2_MASK (0x7 << 4) 1271#define RT5645_CP_FQ2_SFT 4 1272#define RT5645_CP_FQ3_MASK (0x7) 1273#define RT5645_CP_FQ3_SFT 0 1274#define RT5645_CP_FQ_1_5_KHZ 0 1275#define RT5645_CP_FQ_3_KHZ 1 1276#define RT5645_CP_FQ_6_KHZ 2 1277#define RT5645_CP_FQ_12_KHZ 3 1278#define RT5645_CP_FQ_24_KHZ 4 1279#define RT5645_CP_FQ_48_KHZ 5 1280#define RT5645_CP_FQ_96_KHZ 6 1281#define RT5645_CP_FQ_192_KHZ 7 1282 1283/* PV detection and SPK gain control (0x92) */ 1284#define RT5645_PVDD_DET_MASK (0x1 << 15) 1285#define RT5645_PVDD_DET_SFT 15 1286#define RT5645_PVDD_DET_DIS (0x0 << 15) 1287#define RT5645_PVDD_DET_EN (0x1 << 15) 1288#define RT5645_SPK_AG_MASK (0x1 << 14) 1289#define RT5645_SPK_AG_SFT 14 1290#define RT5645_SPK_AG_DIS (0x0 << 14) 1291#define RT5645_SPK_AG_EN (0x1 << 14) 1292 1293/* Micbias Control (0x93) */ 1294#define RT5645_MIC1_BS_MASK (0x1 << 15) 1295#define RT5645_MIC1_BS_SFT 15 1296#define RT5645_MIC1_BS_9AV (0x0 << 15) 1297#define RT5645_MIC1_BS_75AV (0x1 << 15) 1298#define RT5645_MIC2_BS_MASK (0x1 << 14) 1299#define RT5645_MIC2_BS_SFT 14 1300#define RT5645_MIC2_BS_9AV (0x0 << 14) 1301#define RT5645_MIC2_BS_75AV (0x1 << 14) 1302#define RT5645_MIC1_CLK_MASK (0x1 << 13) 1303#define RT5645_MIC1_CLK_SFT 13 1304#define RT5645_MIC1_CLK_DIS (0x0 << 13) 1305#define RT5645_MIC1_CLK_EN (0x1 << 13) 1306#define RT5645_MIC2_CLK_MASK (0x1 << 12) 1307#define RT5645_MIC2_CLK_SFT 12 1308#define RT5645_MIC2_CLK_DIS (0x0 << 12) 1309#define RT5645_MIC2_CLK_EN (0x1 << 12) 1310#define RT5645_MIC1_OVCD_MASK (0x1 << 11) 1311#define RT5645_MIC1_OVCD_SFT 11 1312#define RT5645_MIC1_OVCD_DIS (0x0 << 11) 1313#define RT5645_MIC1_OVCD_EN (0x1 << 11) 1314#define RT5645_MIC1_OVTH_MASK (0x3 << 9) 1315#define RT5645_MIC1_OVTH_SFT 9 1316#define RT5645_MIC1_OVTH_600UA (0x0 << 9) 1317#define RT5645_MIC1_OVTH_1500UA (0x1 << 9) 1318#define RT5645_MIC1_OVTH_2000UA (0x2 << 9) 1319#define RT5645_MIC2_OVCD_MASK (0x1 << 8) 1320#define RT5645_MIC2_OVCD_SFT 8 1321#define RT5645_MIC2_OVCD_DIS (0x0 << 8) 1322#define RT5645_MIC2_OVCD_EN (0x1 << 8) 1323#define RT5645_MIC2_OVTH_MASK (0x3 << 6) 1324#define RT5645_MIC2_OVTH_SFT 6 1325#define RT5645_MIC2_OVTH_600UA (0x0 << 6) 1326#define RT5645_MIC2_OVTH_1500UA (0x1 << 6) 1327#define RT5645_MIC2_OVTH_2000UA (0x2 << 6) 1328#define RT5645_PWR_MB_MASK (0x1 << 5) 1329#define RT5645_PWR_MB_SFT 5 1330#define RT5645_PWR_MB_PD (0x0 << 5) 1331#define RT5645_PWR_MB_PU (0x1 << 5) 1332#define RT5645_PWR_CLK25M_MASK (0x1 << 4) 1333#define RT5645_PWR_CLK25M_SFT 4 1334#define RT5645_PWR_CLK25M_PD (0x0 << 4) 1335#define RT5645_PWR_CLK25M_PU (0x1 << 4) 1336#define RT5645_IRQ_CLK_MCLK (0x0 << 3) 1337#define RT5645_IRQ_CLK_INT (0x1 << 3) 1338#define RT5645_JD1_MODE_MASK (0x3 << 0) 1339#define RT5645_JD1_MODE_0 (0x0 << 0) 1340#define RT5645_JD1_MODE_1 (0x1 << 0) 1341#define RT5645_JD1_MODE_2 (0x2 << 0) 1342 1343/* VAD Control 4 (0x9d) */ 1344#define RT5645_VAD_SEL_MASK (0x3 << 8) 1345#define RT5645_VAD_SEL_SFT 8 1346 1347/* EQ Control 1 (0xb0) */ 1348#define RT5645_EQ_SRC_MASK (0x1 << 15) 1349#define RT5645_EQ_SRC_SFT 15 1350#define RT5645_EQ_SRC_DAC (0x0 << 15) 1351#define RT5645_EQ_SRC_ADC (0x1 << 15) 1352#define RT5645_EQ_UPD (0x1 << 14) 1353#define RT5645_EQ_UPD_BIT 14 1354#define RT5645_EQ_CD_MASK (0x1 << 13) 1355#define RT5645_EQ_CD_SFT 13 1356#define RT5645_EQ_CD_DIS (0x0 << 13) 1357#define RT5645_EQ_CD_EN (0x1 << 13) 1358#define RT5645_EQ_DITH_MASK (0x3 << 8) 1359#define RT5645_EQ_DITH_SFT 8 1360#define RT5645_EQ_DITH_NOR (0x0 << 8) 1361#define RT5645_EQ_DITH_LSB (0x1 << 8) 1362#define RT5645_EQ_DITH_LSB_1 (0x2 << 8) 1363#define RT5645_EQ_DITH_LSB_2 (0x3 << 8) 1364 1365/* EQ Control 2 (0xb1) */ 1366#define RT5645_EQ_HPF1_M_MASK (0x1 << 8) 1367#define RT5645_EQ_HPF1_M_SFT 8 1368#define RT5645_EQ_HPF1_M_HI (0x0 << 8) 1369#define RT5645_EQ_HPF1_M_1ST (0x1 << 8) 1370#define RT5645_EQ_LPF1_M_MASK (0x1 << 7) 1371#define RT5645_EQ_LPF1_M_SFT 7 1372#define RT5645_EQ_LPF1_M_LO (0x0 << 7) 1373#define RT5645_EQ_LPF1_M_1ST (0x1 << 7) 1374#define RT5645_EQ_HPF2_MASK (0x1 << 6) 1375#define RT5645_EQ_HPF2_SFT 6 1376#define RT5645_EQ_HPF2_DIS (0x0 << 6) 1377#define RT5645_EQ_HPF2_EN (0x1 << 6) 1378#define RT5645_EQ_HPF1_MASK (0x1 << 5) 1379#define RT5645_EQ_HPF1_SFT 5 1380#define RT5645_EQ_HPF1_DIS (0x0 << 5) 1381#define RT5645_EQ_HPF1_EN (0x1 << 5) 1382#define RT5645_EQ_BPF4_MASK (0x1 << 4) 1383#define RT5645_EQ_BPF4_SFT 4 1384#define RT5645_EQ_BPF4_DIS (0x0 << 4) 1385#define RT5645_EQ_BPF4_EN (0x1 << 4) 1386#define RT5645_EQ_BPF3_MASK (0x1 << 3) 1387#define RT5645_EQ_BPF3_SFT 3 1388#define RT5645_EQ_BPF3_DIS (0x0 << 3) 1389#define RT5645_EQ_BPF3_EN (0x1 << 3) 1390#define RT5645_EQ_BPF2_MASK (0x1 << 2) 1391#define RT5645_EQ_BPF2_SFT 2 1392#define RT5645_EQ_BPF2_DIS (0x0 << 2) 1393#define RT5645_EQ_BPF2_EN (0x1 << 2) 1394#define RT5645_EQ_BPF1_MASK (0x1 << 1) 1395#define RT5645_EQ_BPF1_SFT 1 1396#define RT5645_EQ_BPF1_DIS (0x0 << 1) 1397#define RT5645_EQ_BPF1_EN (0x1 << 1) 1398#define RT5645_EQ_LPF_MASK (0x1) 1399#define RT5645_EQ_LPF_SFT 0 1400#define RT5645_EQ_LPF_DIS (0x0) 1401#define RT5645_EQ_LPF_EN (0x1) 1402#define RT5645_EQ_CTRL_MASK (0x7f) 1403 1404/* Memory Test (0xb2) */ 1405#define RT5645_MT_MASK (0x1 << 15) 1406#define RT5645_MT_SFT 15 1407#define RT5645_MT_DIS (0x0 << 15) 1408#define RT5645_MT_EN (0x1 << 15) 1409 1410/* DRC/AGC Control 1 (0xb4) */ 1411#define RT5645_DRC_AGC_P_MASK (0x1 << 15) 1412#define RT5645_DRC_AGC_P_SFT 15 1413#define RT5645_DRC_AGC_P_DAC (0x0 << 15) 1414#define RT5645_DRC_AGC_P_ADC (0x1 << 15) 1415#define RT5645_DRC_AGC_MASK (0x1 << 14) 1416#define RT5645_DRC_AGC_SFT 14 1417#define RT5645_DRC_AGC_DIS (0x0 << 14) 1418#define RT5645_DRC_AGC_EN (0x1 << 14) 1419#define RT5645_DRC_AGC_UPD (0x1 << 13) 1420#define RT5645_DRC_AGC_UPD_BIT 13 1421#define RT5645_DRC_AGC_AR_MASK (0x1f << 8) 1422#define RT5645_DRC_AGC_AR_SFT 8 1423#define RT5645_DRC_AGC_R_MASK (0x7 << 5) 1424#define RT5645_DRC_AGC_R_SFT 5 1425#define RT5645_DRC_AGC_R_48K (0x1 << 5) 1426#define RT5645_DRC_AGC_R_96K (0x2 << 5) 1427#define RT5645_DRC_AGC_R_192K (0x3 << 5) 1428#define RT5645_DRC_AGC_R_441K (0x5 << 5) 1429#define RT5645_DRC_AGC_R_882K (0x6 << 5) 1430#define RT5645_DRC_AGC_R_1764K (0x7 << 5) 1431#define RT5645_DRC_AGC_RC_MASK (0x1f) 1432#define RT5645_DRC_AGC_RC_SFT 0 1433 1434/* DRC/AGC Control 2 (0xb5) */ 1435#define RT5645_DRC_AGC_POB_MASK (0x3f << 8) 1436#define RT5645_DRC_AGC_POB_SFT 8 1437#define RT5645_DRC_AGC_CP_MASK (0x1 << 7) 1438#define RT5645_DRC_AGC_CP_SFT 7 1439#define RT5645_DRC_AGC_CP_DIS (0x0 << 7) 1440#define RT5645_DRC_AGC_CP_EN (0x1 << 7) 1441#define RT5645_DRC_AGC_CPR_MASK (0x3 << 5) 1442#define RT5645_DRC_AGC_CPR_SFT 5 1443#define RT5645_DRC_AGC_CPR_1_1 (0x0 << 5) 1444#define RT5645_DRC_AGC_CPR_1_2 (0x1 << 5) 1445#define RT5645_DRC_AGC_CPR_1_3 (0x2 << 5) 1446#define RT5645_DRC_AGC_CPR_1_4 (0x3 << 5) 1447#define RT5645_DRC_AGC_PRB_MASK (0x1f) 1448#define RT5645_DRC_AGC_PRB_SFT 0 1449 1450/* DRC/AGC Control 3 (0xb6) */ 1451#define RT5645_DRC_AGC_NGB_MASK (0xf << 12) 1452#define RT5645_DRC_AGC_NGB_SFT 12 1453#define RT5645_DRC_AGC_TAR_MASK (0x1f << 7) 1454#define RT5645_DRC_AGC_TAR_SFT 7 1455#define RT5645_DRC_AGC_NG_MASK (0x1 << 6) 1456#define RT5645_DRC_AGC_NG_SFT 6 1457#define RT5645_DRC_AGC_NG_DIS (0x0 << 6) 1458#define RT5645_DRC_AGC_NG_EN (0x1 << 6) 1459#define RT5645_DRC_AGC_NGH_MASK (0x1 << 5) 1460#define RT5645_DRC_AGC_NGH_SFT 5 1461#define RT5645_DRC_AGC_NGH_DIS (0x0 << 5) 1462#define RT5645_DRC_AGC_NGH_EN (0x1 << 5) 1463#define RT5645_DRC_AGC_NGT_MASK (0x1f) 1464#define RT5645_DRC_AGC_NGT_SFT 0 1465 1466/* ANC Control 1 (0xb8) */ 1467#define RT5645_ANC_M_MASK (0x1 << 15) 1468#define RT5645_ANC_M_SFT 15 1469#define RT5645_ANC_M_NOR (0x0 << 15) 1470#define RT5645_ANC_M_REV (0x1 << 15) 1471#define RT5645_ANC_MASK (0x1 << 14) 1472#define RT5645_ANC_SFT 14 1473#define RT5645_ANC_DIS (0x0 << 14) 1474#define RT5645_ANC_EN (0x1 << 14) 1475#define RT5645_ANC_MD_MASK (0x3 << 12) 1476#define RT5645_ANC_MD_SFT 12 1477#define RT5645_ANC_MD_DIS (0x0 << 12) 1478#define RT5645_ANC_MD_67MS (0x1 << 12) 1479#define RT5645_ANC_MD_267MS (0x2 << 12) 1480#define RT5645_ANC_MD_1067MS (0x3 << 12) 1481#define RT5645_ANC_SN_MASK (0x1 << 11) 1482#define RT5645_ANC_SN_SFT 11 1483#define RT5645_ANC_SN_DIS (0x0 << 11) 1484#define RT5645_ANC_SN_EN (0x1 << 11) 1485#define RT5645_ANC_CLK_MASK (0x1 << 10) 1486#define RT5645_ANC_CLK_SFT 10 1487#define RT5645_ANC_CLK_ANC (0x0 << 10) 1488#define RT5645_ANC_CLK_REG (0x1 << 10) 1489#define RT5645_ANC_ZCD_MASK (0x3 << 8) 1490#define RT5645_ANC_ZCD_SFT 8 1491#define RT5645_ANC_ZCD_DIS (0x0 << 8) 1492#define RT5645_ANC_ZCD_T1 (0x1 << 8) 1493#define RT5645_ANC_ZCD_T2 (0x2 << 8) 1494#define RT5645_ANC_ZCD_WT (0x3 << 8) 1495#define RT5645_ANC_CS_MASK (0x1 << 7) 1496#define RT5645_ANC_CS_SFT 7 1497#define RT5645_ANC_CS_DIS (0x0 << 7) 1498#define RT5645_ANC_CS_EN (0x1 << 7) 1499#define RT5645_ANC_SW_MASK (0x1 << 6) 1500#define RT5645_ANC_SW_SFT 6 1501#define RT5645_ANC_SW_NOR (0x0 << 6) 1502#define RT5645_ANC_SW_AUTO (0x1 << 6) 1503#define RT5645_ANC_CO_L_MASK (0x3f) 1504#define RT5645_ANC_CO_L_SFT 0 1505 1506/* ANC Control 2 (0xb6) */ 1507#define RT5645_ANC_FG_R_MASK (0xf << 12) 1508#define RT5645_ANC_FG_R_SFT 12 1509#define RT5645_ANC_FG_L_MASK (0xf << 8) 1510#define RT5645_ANC_FG_L_SFT 8 1511#define RT5645_ANC_CG_R_MASK (0xf << 4) 1512#define RT5645_ANC_CG_R_SFT 4 1513#define RT5645_ANC_CG_L_MASK (0xf) 1514#define RT5645_ANC_CG_L_SFT 0 1515 1516/* ANC Control 3 (0xb6) */ 1517#define RT5645_ANC_CD_MASK (0x1 << 6) 1518#define RT5645_ANC_CD_SFT 6 1519#define RT5645_ANC_CD_BOTH (0x0 << 6) 1520#define RT5645_ANC_CD_IND (0x1 << 6) 1521#define RT5645_ANC_CO_R_MASK (0x3f) 1522#define RT5645_ANC_CO_R_SFT 0 1523 1524/* Jack Detect Control (0xbb) */ 1525#define RT5645_JD_MASK (0x7 << 13) 1526#define RT5645_JD_SFT 13 1527#define RT5645_JD_DIS (0x0 << 13) 1528#define RT5645_JD_GPIO1 (0x1 << 13) 1529#define RT5645_JD_JD1_IN4P (0x2 << 13) 1530#define RT5645_JD_JD2_IN4N (0x3 << 13) 1531#define RT5645_JD_GPIO2 (0x4 << 13) 1532#define RT5645_JD_GPIO3 (0x5 << 13) 1533#define RT5645_JD_GPIO4 (0x6 << 13) 1534#define RT5645_JD_HP_MASK (0x1 << 11) 1535#define RT5645_JD_HP_SFT 11 1536#define RT5645_JD_HP_DIS (0x0 << 11) 1537#define RT5645_JD_HP_EN (0x1 << 11) 1538#define RT5645_JD_HP_TRG_MASK (0x1 << 10) 1539#define RT5645_JD_HP_TRG_SFT 10 1540#define RT5645_JD_HP_TRG_LO (0x0 << 10) 1541#define RT5645_JD_HP_TRG_HI (0x1 << 10) 1542#define RT5645_JD_SPL_MASK (0x1 << 9) 1543#define RT5645_JD_SPL_SFT 9 1544#define RT5645_JD_SPL_DIS (0x0 << 9) 1545#define RT5645_JD_SPL_EN (0x1 << 9) 1546#define RT5645_JD_SPL_TRG_MASK (0x1 << 8) 1547#define RT5645_JD_SPL_TRG_SFT 8 1548#define RT5645_JD_SPL_TRG_LO (0x0 << 8) 1549#define RT5645_JD_SPL_TRG_HI (0x1 << 8) 1550#define RT5645_JD_SPR_MASK (0x1 << 7) 1551#define RT5645_JD_SPR_SFT 7 1552#define RT5645_JD_SPR_DIS (0x0 << 7) 1553#define RT5645_JD_SPR_EN (0x1 << 7) 1554#define RT5645_JD_SPR_TRG_MASK (0x1 << 6) 1555#define RT5645_JD_SPR_TRG_SFT 6 1556#define RT5645_JD_SPR_TRG_LO (0x0 << 6) 1557#define RT5645_JD_SPR_TRG_HI (0x1 << 6) 1558#define RT5645_JD_MO_MASK (0x1 << 5) 1559#define RT5645_JD_MO_SFT 5 1560#define RT5645_JD_MO_DIS (0x0 << 5) 1561#define RT5645_JD_MO_EN (0x1 << 5) 1562#define RT5645_JD_MO_TRG_MASK (0x1 << 4) 1563#define RT5645_JD_MO_TRG_SFT 4 1564#define RT5645_JD_MO_TRG_LO (0x0 << 4) 1565#define RT5645_JD_MO_TRG_HI (0x1 << 4) 1566#define RT5645_JD_LO_MASK (0x1 << 3) 1567#define RT5645_JD_LO_SFT 3 1568#define RT5645_JD_LO_DIS (0x0 << 3) 1569#define RT5645_JD_LO_EN (0x1 << 3) 1570#define RT5645_JD_LO_TRG_MASK (0x1 << 2) 1571#define RT5645_JD_LO_TRG_SFT 2 1572#define RT5645_JD_LO_TRG_LO (0x0 << 2) 1573#define RT5645_JD_LO_TRG_HI (0x1 << 2) 1574#define RT5645_JD1_IN4P_MASK (0x1 << 1) 1575#define RT5645_JD1_IN4P_SFT 1 1576#define RT5645_JD1_IN4P_DIS (0x0 << 1) 1577#define RT5645_JD1_IN4P_EN (0x1 << 1) 1578#define RT5645_JD2_IN4N_MASK (0x1) 1579#define RT5645_JD2_IN4N_SFT 0 1580#define RT5645_JD2_IN4N_DIS (0x0) 1581#define RT5645_JD2_IN4N_EN (0x1) 1582 1583/* Jack detect for ANC (0xbc) */ 1584#define RT5645_ANC_DET_MASK (0x3 << 4) 1585#define RT5645_ANC_DET_SFT 4 1586#define RT5645_ANC_DET_DIS (0x0 << 4) 1587#define RT5645_ANC_DET_MB1 (0x1 << 4) 1588#define RT5645_ANC_DET_MB2 (0x2 << 4) 1589#define RT5645_ANC_DET_JD (0x3 << 4) 1590#define RT5645_AD_TRG_MASK (0x1 << 3) 1591#define RT5645_AD_TRG_SFT 3 1592#define RT5645_AD_TRG_LO (0x0 << 3) 1593#define RT5645_AD_TRG_HI (0x1 << 3) 1594#define RT5645_ANCM_DET_MASK (0x3 << 4) 1595#define RT5645_ANCM_DET_SFT 4 1596#define RT5645_ANCM_DET_DIS (0x0 << 4) 1597#define RT5645_ANCM_DET_MB1 (0x1 << 4) 1598#define RT5645_ANCM_DET_MB2 (0x2 << 4) 1599#define RT5645_ANCM_DET_JD (0x3 << 4) 1600#define RT5645_AMD_TRG_MASK (0x1 << 3) 1601#define RT5645_AMD_TRG_SFT 3 1602#define RT5645_AMD_TRG_LO (0x0 << 3) 1603#define RT5645_AMD_TRG_HI (0x1 << 3) 1604 1605/* IRQ Control 1 (0xbd) */ 1606#define RT5645_IRQ_JD_MASK (0x1 << 15) 1607#define RT5645_IRQ_JD_SFT 15 1608#define RT5645_IRQ_JD_BP (0x0 << 15) 1609#define RT5645_IRQ_JD_NOR (0x1 << 15) 1610#define RT5645_IRQ_OT_MASK (0x1 << 14) 1611#define RT5645_IRQ_OT_SFT 14 1612#define RT5645_IRQ_OT_BP (0x0 << 14) 1613#define RT5645_IRQ_OT_NOR (0x1 << 14) 1614#define RT5645_JD_STKY_MASK (0x1 << 13) 1615#define RT5645_JD_STKY_SFT 13 1616#define RT5645_JD_STKY_DIS (0x0 << 13) 1617#define RT5645_JD_STKY_EN (0x1 << 13) 1618#define RT5645_OT_STKY_MASK (0x1 << 12) 1619#define RT5645_OT_STKY_SFT 12 1620#define RT5645_OT_STKY_DIS (0x0 << 12) 1621#define RT5645_OT_STKY_EN (0x1 << 12) 1622#define RT5645_JD_P_MASK (0x1 << 11) 1623#define RT5645_JD_P_SFT 11 1624#define RT5645_JD_P_NOR (0x0 << 11) 1625#define RT5645_JD_P_INV (0x1 << 11) 1626#define RT5645_OT_P_MASK (0x1 << 10) 1627#define RT5645_OT_P_SFT 10 1628#define RT5645_OT_P_NOR (0x0 << 10) 1629#define RT5645_OT_P_INV (0x1 << 10) 1630#define RT5645_IRQ_JD_1_1_EN (0x1 << 9) 1631 1632/* IRQ Control 2 (0xbe) */ 1633#define RT5645_IRQ_MB1_OC_MASK (0x1 << 15) 1634#define RT5645_IRQ_MB1_OC_SFT 15 1635#define RT5645_IRQ_MB1_OC_BP (0x0 << 15) 1636#define RT5645_IRQ_MB1_OC_NOR (0x1 << 15) 1637#define RT5645_IRQ_MB2_OC_MASK (0x1 << 14) 1638#define RT5645_IRQ_MB2_OC_SFT 14 1639#define RT5645_IRQ_MB2_OC_BP (0x0 << 14) 1640#define RT5645_IRQ_MB2_OC_NOR (0x1 << 14) 1641#define RT5645_MB1_OC_STKY_MASK (0x1 << 13) 1642#define RT5645_MB1_OC_STKY_SFT 13 1643#define RT5645_MB1_OC_STKY_DIS (0x0 << 13) 1644#define RT5645_MB1_OC_STKY_EN (0x1 << 13) 1645#define RT5645_MB2_OC_STKY_MASK (0x1 << 12) 1646#define RT5645_MB2_OC_STKY_SFT 12 1647#define RT5645_MB2_OC_STKY_DIS (0x0 << 12) 1648#define RT5645_MB2_OC_STKY_EN (0x1 << 12) 1649#define RT5645_MB1_OC_P_MASK (0x1 << 7) 1650#define RT5645_MB1_OC_P_SFT 7 1651#define RT5645_MB1_OC_P_NOR (0x0 << 7) 1652#define RT5645_MB1_OC_P_INV (0x1 << 7) 1653#define RT5645_MB2_OC_P_MASK (0x1 << 6) 1654#define RT5645_MB2_OC_P_SFT 6 1655#define RT5645_MB2_OC_P_NOR (0x0 << 6) 1656#define RT5645_MB2_OC_P_INV (0x1 << 6) 1657#define RT5645_MB1_OC_CLR (0x1 << 3) 1658#define RT5645_MB1_OC_CLR_SFT 3 1659#define RT5645_MB2_OC_CLR (0x1 << 2) 1660#define RT5645_MB2_OC_CLR_SFT 2 1661 1662/* GPIO Control 1 (0xc0) */ 1663#define RT5645_GP1_PIN_MASK (0x1 << 15) 1664#define RT5645_GP1_PIN_SFT 15 1665#define RT5645_GP1_PIN_GPIO1 (0x0 << 15) 1666#define RT5645_GP1_PIN_IRQ (0x1 << 15) 1667#define RT5645_GP2_PIN_MASK (0x1 << 14) 1668#define RT5645_GP2_PIN_SFT 14 1669#define RT5645_GP2_PIN_GPIO2 (0x0 << 14) 1670#define RT5645_GP2_PIN_DMIC1_SCL (0x1 << 14) 1671#define RT5645_GP3_PIN_MASK (0x3 << 12) 1672#define RT5645_GP3_PIN_SFT 12 1673#define RT5645_GP3_PIN_GPIO3 (0x0 << 12) 1674#define RT5645_GP3_PIN_DMIC1_SDA (0x1 << 12) 1675#define RT5645_GP3_PIN_IRQ (0x2 << 12) 1676#define RT5645_GP4_PIN_MASK (0x1 << 11) 1677#define RT5645_GP4_PIN_SFT 11 1678#define RT5645_GP4_PIN_GPIO4 (0x0 << 11) 1679#define RT5645_GP4_PIN_DMIC2_SDA (0x1 << 11) 1680#define RT5645_DP_SIG_MASK (0x1 << 10) 1681#define RT5645_DP_SIG_SFT 10 1682#define RT5645_DP_SIG_TEST (0x0 << 10) 1683#define RT5645_DP_SIG_AP (0x1 << 10) 1684#define RT5645_GPIO_M_MASK (0x1 << 9) 1685#define RT5645_GPIO_M_SFT 9 1686#define RT5645_GPIO_M_FLT (0x0 << 9) 1687#define RT5645_GPIO_M_PH (0x1 << 9) 1688#define RT5645_I2S2_SEL (0x1 << 8) 1689#define RT5645_I2S2_SEL_SFT 8 1690#define RT5645_GP5_PIN_MASK (0x1 << 7) 1691#define RT5645_GP5_PIN_SFT 7 1692#define RT5645_GP5_PIN_GPIO5 (0x0 << 7) 1693#define RT5645_GP5_PIN_DMIC1_SDA (0x1 << 7) 1694#define RT5645_GP6_PIN_MASK (0x1 << 6) 1695#define RT5645_GP6_PIN_SFT 6 1696#define RT5645_GP6_PIN_GPIO6 (0x0 << 6) 1697#define RT5645_GP6_PIN_DMIC2_SDA (0x1 << 6) 1698#define RT5645_GP8_PIN_MASK (0x1 << 3) 1699#define RT5645_GP8_PIN_SFT 3 1700#define RT5645_GP8_PIN_GPIO8 (0x0 << 3) 1701#define RT5645_GP8_PIN_DMIC2_SDA (0x1 << 3) 1702#define RT5645_GP12_PIN_MASK (0x1 << 2) 1703#define RT5645_GP12_PIN_SFT 2 1704#define RT5645_GP12_PIN_GPIO12 (0x0 << 2) 1705#define RT5645_GP12_PIN_DMIC2_SDA (0x1 << 2) 1706#define RT5645_GP11_PIN_MASK (0x1 << 1) 1707#define RT5645_GP11_PIN_SFT 1 1708#define RT5645_GP11_PIN_GPIO11 (0x0 << 1) 1709#define RT5645_GP11_PIN_DMIC1_SDA (0x1 << 1) 1710#define RT5645_GP10_PIN_MASK (0x1) 1711#define RT5645_GP10_PIN_SFT 0 1712#define RT5645_GP10_PIN_GPIO10 (0x0) 1713#define RT5645_GP10_PIN_DMIC2_SDA (0x1) 1714 1715/* GPIO Control 3 (0xc2) */ 1716#define RT5645_GP4_PF_MASK (0x1 << 11) 1717#define RT5645_GP4_PF_SFT 11 1718#define RT5645_GP4_PF_IN (0x0 << 11) 1719#define RT5645_GP4_PF_OUT (0x1 << 11) 1720#define RT5645_GP4_OUT_MASK (0x1 << 10) 1721#define RT5645_GP4_OUT_SFT 10 1722#define RT5645_GP4_OUT_LO (0x0 << 10) 1723#define RT5645_GP4_OUT_HI (0x1 << 10) 1724#define RT5645_GP4_P_MASK (0x1 << 9) 1725#define RT5645_GP4_P_SFT 9 1726#define RT5645_GP4_P_NOR (0x0 << 9) 1727#define RT5645_GP4_P_INV (0x1 << 9) 1728#define RT5645_GP3_PF_MASK (0x1 << 8) 1729#define RT5645_GP3_PF_SFT 8 1730#define RT5645_GP3_PF_IN (0x0 << 8) 1731#define RT5645_GP3_PF_OUT (0x1 << 8) 1732#define RT5645_GP3_OUT_MASK (0x1 << 7) 1733#define RT5645_GP3_OUT_SFT 7 1734#define RT5645_GP3_OUT_LO (0x0 << 7) 1735#define RT5645_GP3_OUT_HI (0x1 << 7) 1736#define RT5645_GP3_P_MASK (0x1 << 6) 1737#define RT5645_GP3_P_SFT 6 1738#define RT5645_GP3_P_NOR (0x0 << 6) 1739#define RT5645_GP3_P_INV (0x1 << 6) 1740#define RT5645_GP2_PF_MASK (0x1 << 5) 1741#define RT5645_GP2_PF_SFT 5 1742#define RT5645_GP2_PF_IN (0x0 << 5) 1743#define RT5645_GP2_PF_OUT (0x1 << 5) 1744#define RT5645_GP2_OUT_MASK (0x1 << 4) 1745#define RT5645_GP2_OUT_SFT 4 1746#define RT5645_GP2_OUT_LO (0x0 << 4) 1747#define RT5645_GP2_OUT_HI (0x1 << 4) 1748#define RT5645_GP2_P_MASK (0x1 << 3) 1749#define RT5645_GP2_P_SFT 3 1750#define RT5645_GP2_P_NOR (0x0 << 3) 1751#define RT5645_GP2_P_INV (0x1 << 3) 1752#define RT5645_GP1_PF_MASK (0x1 << 2) 1753#define RT5645_GP1_PF_SFT 2 1754#define RT5645_GP1_PF_IN (0x0 << 2) 1755#define RT5645_GP1_PF_OUT (0x1 << 2) 1756#define RT5645_GP1_OUT_MASK (0x1 << 1) 1757#define RT5645_GP1_OUT_SFT 1 1758#define RT5645_GP1_OUT_LO (0x0 << 1) 1759#define RT5645_GP1_OUT_HI (0x1 << 1) 1760#define RT5645_GP1_P_MASK (0x1) 1761#define RT5645_GP1_P_SFT 0 1762#define RT5645_GP1_P_NOR (0x0) 1763#define RT5645_GP1_P_INV (0x1) 1764 1765/* Programmable Register Array Control 1 (0xc8) */ 1766#define RT5645_REG_SEQ_MASK (0xf << 12) 1767#define RT5645_REG_SEQ_SFT 12 1768#define RT5645_SEQ1_ST_MASK (0x1 << 11) /*RO*/ 1769#define RT5645_SEQ1_ST_SFT 11 1770#define RT5645_SEQ1_ST_RUN (0x0 << 11) 1771#define RT5645_SEQ1_ST_FIN (0x1 << 11) 1772#define RT5645_SEQ2_ST_MASK (0x1 << 10) /*RO*/ 1773#define RT5645_SEQ2_ST_SFT 10 1774#define RT5645_SEQ2_ST_RUN (0x0 << 10) 1775#define RT5645_SEQ2_ST_FIN (0x1 << 10) 1776#define RT5645_REG_LV_MASK (0x1 << 9) 1777#define RT5645_REG_LV_SFT 9 1778#define RT5645_REG_LV_MX (0x0 << 9) 1779#define RT5645_REG_LV_PR (0x1 << 9) 1780#define RT5645_SEQ_2_PT_MASK (0x1 << 8) 1781#define RT5645_SEQ_2_PT_BIT 8 1782#define RT5645_REG_IDX_MASK (0xff) 1783#define RT5645_REG_IDX_SFT 0 1784 1785/* Programmable Register Array Control 2 (0xc9) */ 1786#define RT5645_REG_DAT_MASK (0xffff) 1787#define RT5645_REG_DAT_SFT 0 1788 1789/* Programmable Register Array Control 3 (0xca) */ 1790#define RT5645_SEQ_DLY_MASK (0xff << 8) 1791#define RT5645_SEQ_DLY_SFT 8 1792#define RT5645_PROG_MASK (0x1 << 7) 1793#define RT5645_PROG_SFT 7 1794#define RT5645_PROG_DIS (0x0 << 7) 1795#define RT5645_PROG_EN (0x1 << 7) 1796#define RT5645_SEQ1_PT_RUN (0x1 << 6) 1797#define RT5645_SEQ1_PT_RUN_BIT 6 1798#define RT5645_SEQ2_PT_RUN (0x1 << 5) 1799#define RT5645_SEQ2_PT_RUN_BIT 5 1800 1801/* Programmable Register Array Control 4 (0xcb) */ 1802#define RT5645_SEQ1_START_MASK (0xf << 8) 1803#define RT5645_SEQ1_START_SFT 8 1804#define RT5645_SEQ1_END_MASK (0xf) 1805#define RT5645_SEQ1_END_SFT 0 1806 1807/* Programmable Register Array Control 5 (0xcc) */ 1808#define RT5645_SEQ2_START_MASK (0xf << 8) 1809#define RT5645_SEQ2_START_SFT 8 1810#define RT5645_SEQ2_END_MASK (0xf) 1811#define RT5645_SEQ2_END_SFT 0 1812 1813/* Scramble Function (0xcd) */ 1814#define RT5645_SCB_KEY_MASK (0xff) 1815#define RT5645_SCB_KEY_SFT 0 1816 1817/* Scramble Control (0xce) */ 1818#define RT5645_SCB_SWAP_MASK (0x1 << 15) 1819#define RT5645_SCB_SWAP_SFT 15 1820#define RT5645_SCB_SWAP_DIS (0x0 << 15) 1821#define RT5645_SCB_SWAP_EN (0x1 << 15) 1822#define RT5645_SCB_MASK (0x1 << 14) 1823#define RT5645_SCB_SFT 14 1824#define RT5645_SCB_DIS (0x0 << 14) 1825#define RT5645_SCB_EN (0x1 << 14) 1826 1827/* Baseback Control (0xcf) */ 1828#define RT5645_BB_MASK (0x1 << 15) 1829#define RT5645_BB_SFT 15 1830#define RT5645_BB_DIS (0x0 << 15) 1831#define RT5645_BB_EN (0x1 << 15) 1832#define RT5645_BB_CT_MASK (0x7 << 12) 1833#define RT5645_BB_CT_SFT 12 1834#define RT5645_BB_CT_A (0x0 << 12) 1835#define RT5645_BB_CT_B (0x1 << 12) 1836#define RT5645_BB_CT_C (0x2 << 12) 1837#define RT5645_BB_CT_D (0x3 << 12) 1838#define RT5645_M_BB_L_MASK (0x1 << 9) 1839#define RT5645_M_BB_L_SFT 9 1840#define RT5645_M_BB_R_MASK (0x1 << 8) 1841#define RT5645_M_BB_R_SFT 8 1842#define RT5645_M_BB_HPF_L_MASK (0x1 << 7) 1843#define RT5645_M_BB_HPF_L_SFT 7 1844#define RT5645_M_BB_HPF_R_MASK (0x1 << 6) 1845#define RT5645_M_BB_HPF_R_SFT 6 1846#define RT5645_G_BB_BST_MASK (0x3f) 1847#define RT5645_G_BB_BST_SFT 0 1848#define RT5645_G_BB_BST_25DB 0x14 1849 1850/* MP3 Plus Control 1 (0xd0) */ 1851#define RT5645_M_MP3_L_MASK (0x1 << 15) 1852#define RT5645_M_MP3_L_SFT 15 1853#define RT5645_M_MP3_R_MASK (0x1 << 14) 1854#define RT5645_M_MP3_R_SFT 14 1855#define RT5645_M_MP3_MASK (0x1 << 13) 1856#define RT5645_M_MP3_SFT 13 1857#define RT5645_M_MP3_DIS (0x0 << 13) 1858#define RT5645_M_MP3_EN (0x1 << 13) 1859#define RT5645_EG_MP3_MASK (0x1f << 8) 1860#define RT5645_EG_MP3_SFT 8 1861#define RT5645_MP3_HLP_MASK (0x1 << 7) 1862#define RT5645_MP3_HLP_SFT 7 1863#define RT5645_MP3_HLP_DIS (0x0 << 7) 1864#define RT5645_MP3_HLP_EN (0x1 << 7) 1865#define RT5645_M_MP3_ORG_L_MASK (0x1 << 6) 1866#define RT5645_M_MP3_ORG_L_SFT 6 1867#define RT5645_M_MP3_ORG_R_MASK (0x1 << 5) 1868#define RT5645_M_MP3_ORG_R_SFT 5 1869 1870/* MP3 Plus Control 2 (0xd1) */ 1871#define RT5645_MP3_WT_MASK (0x1 << 13) 1872#define RT5645_MP3_WT_SFT 13 1873#define RT5645_MP3_WT_1_4 (0x0 << 13) 1874#define RT5645_MP3_WT_1_2 (0x1 << 13) 1875#define RT5645_OG_MP3_MASK (0x1f << 8) 1876#define RT5645_OG_MP3_SFT 8 1877#define RT5645_HG_MP3_MASK (0x3f) 1878#define RT5645_HG_MP3_SFT 0 1879 1880/* 3D HP Control 1 (0xd2) */ 1881#define RT5645_3D_CF_MASK (0x1 << 15) 1882#define RT5645_3D_CF_SFT 15 1883#define RT5645_3D_CF_DIS (0x0 << 15) 1884#define RT5645_3D_CF_EN (0x1 << 15) 1885#define RT5645_3D_HP_MASK (0x1 << 14) 1886#define RT5645_3D_HP_SFT 14 1887#define RT5645_3D_HP_DIS (0x0 << 14) 1888#define RT5645_3D_HP_EN (0x1 << 14) 1889#define RT5645_3D_BT_MASK (0x1 << 13) 1890#define RT5645_3D_BT_SFT 13 1891#define RT5645_3D_BT_DIS (0x0 << 13) 1892#define RT5645_3D_BT_EN (0x1 << 13) 1893#define RT5645_3D_1F_MIX_MASK (0x3 << 11) 1894#define RT5645_3D_1F_MIX_SFT 11 1895#define RT5645_3D_HP_M_MASK (0x1 << 10) 1896#define RT5645_3D_HP_M_SFT 10 1897#define RT5645_3D_HP_M_SUR (0x0 << 10) 1898#define RT5645_3D_HP_M_FRO (0x1 << 10) 1899#define RT5645_M_3D_HRTF_MASK (0x1 << 9) 1900#define RT5645_M_3D_HRTF_SFT 9 1901#define RT5645_M_3D_D2H_MASK (0x1 << 8) 1902#define RT5645_M_3D_D2H_SFT 8 1903#define RT5645_M_3D_D2R_MASK (0x1 << 7) 1904#define RT5645_M_3D_D2R_SFT 7 1905#define RT5645_M_3D_REVB_MASK (0x1 << 6) 1906#define RT5645_M_3D_REVB_SFT 6 1907 1908/* Adjustable high pass filter control 1 (0xd3) */ 1909#define RT5645_2ND_HPF_MASK (0x1 << 15) 1910#define RT5645_2ND_HPF_SFT 15 1911#define RT5645_2ND_HPF_DIS (0x0 << 15) 1912#define RT5645_2ND_HPF_EN (0x1 << 15) 1913#define RT5645_HPF_CF_L_MASK (0x7 << 12) 1914#define RT5645_HPF_CF_L_SFT 12 1915#define RT5645_1ST_HPF_MASK (0x1 << 11) 1916#define RT5645_1ST_HPF_SFT 11 1917#define RT5645_1ST_HPF_DIS (0x0 << 11) 1918#define RT5645_1ST_HPF_EN (0x1 << 11) 1919#define RT5645_HPF_CF_R_MASK (0x7 << 8) 1920#define RT5645_HPF_CF_R_SFT 8 1921#define RT5645_ZD_T_MASK (0x3 << 6) 1922#define RT5645_ZD_T_SFT 6 1923#define RT5645_ZD_F_MASK (0x3 << 4) 1924#define RT5645_ZD_F_SFT 4 1925#define RT5645_ZD_F_IM (0x0 << 4) 1926#define RT5645_ZD_F_ZC_IM (0x1 << 4) 1927#define RT5645_ZD_F_ZC_IOD (0x2 << 4) 1928#define RT5645_ZD_F_UN (0x3 << 4) 1929 1930/* HP calibration control and Amp detection (0xd6) */ 1931#define RT5645_SI_DAC_MASK (0x1 << 11) 1932#define RT5645_SI_DAC_SFT 11 1933#define RT5645_SI_DAC_AUTO (0x0 << 11) 1934#define RT5645_SI_DAC_TEST (0x1 << 11) 1935#define RT5645_DC_CAL_M_MASK (0x1 << 10) 1936#define RT5645_DC_CAL_M_SFT 10 1937#define RT5645_DC_CAL_M_CAL (0x0 << 10) 1938#define RT5645_DC_CAL_M_NOR (0x1 << 10) 1939#define RT5645_DC_CAL_MASK (0x1 << 9) 1940#define RT5645_DC_CAL_SFT 9 1941#define RT5645_DC_CAL_DIS (0x0 << 9) 1942#define RT5645_DC_CAL_EN (0x1 << 9) 1943#define RT5645_HPD_RCV_MASK (0x7 << 6) 1944#define RT5645_HPD_RCV_SFT 6 1945#define RT5645_HPD_PS_MASK (0x1 << 5) 1946#define RT5645_HPD_PS_SFT 5 1947#define RT5645_HPD_PS_DIS (0x0 << 5) 1948#define RT5645_HPD_PS_EN (0x1 << 5) 1949#define RT5645_CAL_M_MASK (0x1 << 4) 1950#define RT5645_CAL_M_SFT 4 1951#define RT5645_CAL_M_DEP (0x0 << 4) 1952#define RT5645_CAL_M_CAL (0x1 << 4) 1953#define RT5645_CAL_MASK (0x1 << 3) 1954#define RT5645_CAL_SFT 3 1955#define RT5645_CAL_DIS (0x0 << 3) 1956#define RT5645_CAL_EN (0x1 << 3) 1957#define RT5645_CAL_TEST_MASK (0x1 << 2) 1958#define RT5645_CAL_TEST_SFT 2 1959#define RT5645_CAL_TEST_DIS (0x0 << 2) 1960#define RT5645_CAL_TEST_EN (0x1 << 2) 1961#define RT5645_CAL_P_MASK (0x3) 1962#define RT5645_CAL_P_SFT 0 1963#define RT5645_CAL_P_NONE (0x0) 1964#define RT5645_CAL_P_CAL (0x1) 1965#define RT5645_CAL_P_DAC_CAL (0x2) 1966 1967/* Soft volume and zero cross control 1 (0xd9) */ 1968#define RT5645_SV_MASK (0x1 << 15) 1969#define RT5645_SV_SFT 15 1970#define RT5645_SV_DIS (0x0 << 15) 1971#define RT5645_SV_EN (0x1 << 15) 1972#define RT5645_SPO_SV_MASK (0x1 << 14) 1973#define RT5645_SPO_SV_SFT 14 1974#define RT5645_SPO_SV_DIS (0x0 << 14) 1975#define RT5645_SPO_SV_EN (0x1 << 14) 1976#define RT5645_OUT_SV_MASK (0x1 << 13) 1977#define RT5645_OUT_SV_SFT 13 1978#define RT5645_OUT_SV_DIS (0x0 << 13) 1979#define RT5645_OUT_SV_EN (0x1 << 13) 1980#define RT5645_HP_SV_MASK (0x1 << 12) 1981#define RT5645_HP_SV_SFT 12 1982#define RT5645_HP_SV_DIS (0x0 << 12) 1983#define RT5645_HP_SV_EN (0x1 << 12) 1984#define RT5645_ZCD_DIG_MASK (0x1 << 11) 1985#define RT5645_ZCD_DIG_SFT 11 1986#define RT5645_ZCD_DIG_DIS (0x0 << 11) 1987#define RT5645_ZCD_DIG_EN (0x1 << 11) 1988#define RT5645_ZCD_MASK (0x1 << 10) 1989#define RT5645_ZCD_SFT 10 1990#define RT5645_ZCD_PD (0x0 << 10) 1991#define RT5645_ZCD_PU (0x1 << 10) 1992#define RT5645_M_ZCD_MASK (0x3f << 4) 1993#define RT5645_M_ZCD_SFT 4 1994#define RT5645_M_ZCD_RM_L (0x1 << 9) 1995#define RT5645_M_ZCD_RM_R (0x1 << 8) 1996#define RT5645_M_ZCD_SM_L (0x1 << 7) 1997#define RT5645_M_ZCD_SM_R (0x1 << 6) 1998#define RT5645_M_ZCD_OM_L (0x1 << 5) 1999#define RT5645_M_ZCD_OM_R (0x1 << 4) 2000#define RT5645_SV_DLY_MASK (0xf) 2001#define RT5645_SV_DLY_SFT 0 2002 2003/* Soft volume and zero cross control 2 (0xda) */ 2004#define RT5645_ZCD_HP_MASK (0x1 << 15) 2005#define RT5645_ZCD_HP_SFT 15 2006#define RT5645_ZCD_HP_DIS (0x0 << 15) 2007#define RT5645_ZCD_HP_EN (0x1 << 15) 2008 2009 2010/* Codec Private Register definition */ 2011/* 3D Speaker Control (0x63) */ 2012#define RT5645_3D_SPK_MASK (0x1 << 15) 2013#define RT5645_3D_SPK_SFT 15 2014#define RT5645_3D_SPK_DIS (0x0 << 15) 2015#define RT5645_3D_SPK_EN (0x1 << 15) 2016#define RT5645_3D_SPK_M_MASK (0x3 << 13) 2017#define RT5645_3D_SPK_M_SFT 13 2018#define RT5645_3D_SPK_CG_MASK (0x1f << 8) 2019#define RT5645_3D_SPK_CG_SFT 8 2020#define RT5645_3D_SPK_SG_MASK (0x1f) 2021#define RT5645_3D_SPK_SG_SFT 0 2022 2023/* Wind Noise Detection Control 1 (0x6c) */ 2024#define RT5645_WND_MASK (0x1 << 15) 2025#define RT5645_WND_SFT 15 2026#define RT5645_WND_DIS (0x0 << 15) 2027#define RT5645_WND_EN (0x1 << 15) 2028 2029/* Wind Noise Detection Control 2 (0x6d) */ 2030#define RT5645_WND_FC_NW_MASK (0x3f << 10) 2031#define RT5645_WND_FC_NW_SFT 10 2032#define RT5645_WND_FC_WK_MASK (0x3f << 4) 2033#define RT5645_WND_FC_WK_SFT 4 2034 2035/* Wind Noise Detection Control 3 (0x6e) */ 2036#define RT5645_HPF_FC_MASK (0x3f << 6) 2037#define RT5645_HPF_FC_SFT 6 2038#define RT5645_WND_FC_ST_MASK (0x3f) 2039#define RT5645_WND_FC_ST_SFT 0 2040 2041/* Wind Noise Detection Control 4 (0x6f) */ 2042#define RT5645_WND_TH_LO_MASK (0x3ff) 2043#define RT5645_WND_TH_LO_SFT 0 2044 2045/* Wind Noise Detection Control 5 (0x70) */ 2046#define RT5645_WND_TH_HI_MASK (0x3ff) 2047#define RT5645_WND_TH_HI_SFT 0 2048 2049/* Wind Noise Detection Control 8 (0x73) */ 2050#define RT5645_WND_WIND_MASK (0x1 << 13) /* Read-Only */ 2051#define RT5645_WND_WIND_SFT 13 2052#define RT5645_WND_STRONG_MASK (0x1 << 12) /* Read-Only */ 2053#define RT5645_WND_STRONG_SFT 12 2054enum { 2055 RT5645_NO_WIND, 2056 RT5645_BREEZE, 2057 RT5645_STORM, 2058}; 2059 2060/* Dipole Speaker Interface (0x75) */ 2061#define RT5645_DP_ATT_MASK (0x3 << 14) 2062#define RT5645_DP_ATT_SFT 14 2063#define RT5645_DP_SPK_MASK (0x1 << 10) 2064#define RT5645_DP_SPK_SFT 10 2065#define RT5645_DP_SPK_DIS (0x0 << 10) 2066#define RT5645_DP_SPK_EN (0x1 << 10) 2067 2068/* EQ Pre Volume Control (0xb3) */ 2069#define RT5645_EQ_PRE_VOL_MASK (0xffff) 2070#define RT5645_EQ_PRE_VOL_SFT 0 2071 2072/* EQ Post Volume Control (0xb4) */ 2073#define RT5645_EQ_PST_VOL_MASK (0xffff) 2074#define RT5645_EQ_PST_VOL_SFT 0 2075 2076/* Jack Detect Control 3 (0xf8) */ 2077#define RT5645_CMP_MIC_IN_DET_MASK (0x7 << 12) 2078#define RT5645_JD_CBJ_EN (0x1 << 7) 2079#define RT5645_JD_CBJ_POL (0x1 << 6) 2080#define RT5645_JD_TRI_CBJ_SEL_MASK (0x7 << 3) 2081#define RT5645_JD_TRI_CBJ_SEL_SFT (3) 2082#define RT5645_JD_TRI_HPO_SEL_MASK (0x7) 2083#define RT5645_JD_TRI_HPO_SEL_SFT (0) 2084#define RT5645_JD_F_GPIO_JD1 (0x0) 2085#define RT5645_JD_F_JD1_1 (0x1) 2086#define RT5645_JD_F_JD1_2 (0x2) 2087#define RT5645_JD_F_JD2 (0x3) 2088#define RT5645_JD_F_JD3 (0x4) 2089#define RT5645_JD_F_GPIO_JD2 (0x5) 2090#define RT5645_JD_F_MX0B_12 (0x6) 2091 2092/* Digital Misc Control (0xfa) */ 2093#define RT5645_RST_DSP (0x1 << 13) 2094#define RT5645_IF1_ADC1_IN1_SEL (0x1 << 12) 2095#define RT5645_IF1_ADC1_IN1_SFT 12 2096#define RT5645_IF1_ADC1_IN2_SEL (0x1 << 11) 2097#define RT5645_IF1_ADC1_IN2_SFT 11 2098#define RT5645_IF1_ADC2_IN1_SEL (0x1 << 10) 2099#define RT5645_IF1_ADC2_IN1_SFT 10 2100#define RT5645_DIG_GATE_CTRL 0x1 2101 2102/* General Control2 (0xfb) */ 2103#define RT5645_RXDC_SRC_MASK (0x1 << 7) 2104#define RT5645_RXDC_SRC_STO (0x0 << 7) 2105#define RT5645_RXDC_SRC_MONO (0x1 << 7) 2106#define RT5645_RXDC_SRC_SFT (7) 2107#define RT5645_RXDP2_SEL_MASK (0x1 << 3) 2108#define RT5645_RXDP2_SEL_IF2 (0x0 << 3) 2109#define RT5645_RXDP2_SEL_ADC (0x1 << 3) 2110#define RT5645_RXDP2_SEL_SFT (3) 2111 2112/* General Control3 (0xfc) */ 2113#define RT5645_JD_PSV_MODE (0x1 << 12) 2114#define RT5645_IRQ_CLK_GATE_CTRL (0x1 << 11) 2115#define RT5645_MICINDET_MANU (0x1 << 7) 2116 2117/* Vendor ID (0xfd) */ 2118#define RT5645_VER_C 0x2 2119#define RT5645_VER_D 0x3 2120 2121 2122/* Volume Rescale */ 2123#define RT5645_VOL_RSCL_MAX 0x27 2124#define RT5645_VOL_RSCL_RANGE 0x1F 2125/* Debug String Length */ 2126#define RT5645_REG_DISP_LEN 23 2127 2128 2129/* System Clock Source */ 2130enum { 2131 RT5645_SCLK_S_MCLK, 2132 RT5645_SCLK_S_PLL1, 2133 RT5645_SCLK_S_RCCLK, 2134}; 2135 2136/* PLL1 Source */ 2137enum { 2138 RT5645_PLL1_S_MCLK, 2139 RT5645_PLL1_S_BCLK1, 2140 RT5645_PLL1_S_BCLK2, 2141}; 2142 2143enum { 2144 RT5645_AIF1, 2145 RT5645_AIF2, 2146 RT5645_AIFS, 2147}; 2148 2149enum { 2150 RT5645_DMIC_DATA_IN2P, 2151 RT5645_DMIC_DATA_GPIO6, 2152 RT5645_DMIC_DATA_GPIO10, 2153 RT5645_DMIC_DATA_GPIO12, 2154}; 2155 2156enum { 2157 RT5645_DMIC_DATA_IN2N, 2158 RT5645_DMIC_DATA_GPIO5, 2159 RT5645_DMIC_DATA_GPIO11, 2160}; 2161 2162enum { 2163 CODEC_TYPE_RT5645, 2164 CODEC_TYPE_RT5650, 2165}; 2166 2167/* filter mask */ 2168enum { 2169 RT5645_DA_STEREO_FILTER = 0x1, 2170 RT5645_DA_MONO_L_FILTER = (0x1 << 1), 2171 RT5645_DA_MONO_R_FILTER = (0x1 << 2), 2172 RT5645_AD_STEREO_FILTER = (0x1 << 3), 2173 RT5645_AD_MONO_L_FILTER = (0x1 << 4), 2174 RT5645_AD_MONO_R_FILTER = (0x1 << 5), 2175}; 2176 2177int rt5645_sel_asrc_clk_src(struct snd_soc_codec *codec, 2178 unsigned int filter_mask, unsigned int clk_src); 2179 2180struct rt5645_priv { 2181 struct snd_soc_codec *codec; 2182 struct rt5645_platform_data pdata; 2183 struct regmap *regmap; 2184 struct i2c_client *i2c; 2185 struct snd_soc_jack *hp_jack; 2186 struct snd_soc_jack *mic_jack; 2187 struct delayed_work jack_detect_work; 2188 2189 int codec_type; 2190 int sysclk; 2191 int sysclk_src; 2192 int lrck[RT5645_AIFS]; 2193 int bclk[RT5645_AIFS]; 2194 int master[RT5645_AIFS]; 2195 2196 int pll_src; 2197 int pll_in; 2198 int pll_out; 2199}; 2200 2201int rt5645_set_jack_detect(struct snd_soc_codec *codec, 2202 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack); 2203 2204#endif /* __RT5645_H__ */ 2205