1/* 2 * rt5640.h -- RT5640 ALSA SoC audio driver 3 * 4 * Copyright 2011 Realtek Microelectronics 5 * Author: Johnny Hsu <johnnyhsu@realtek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12#ifndef _RT5640_H 13#define _RT5640_H 14 15#include <sound/rt5640.h> 16 17/* Info */ 18#define RT5640_RESET 0x00 19#define RT5640_VENDOR_ID 0xfd 20#define RT5640_VENDOR_ID1 0xfe 21#define RT5640_VENDOR_ID2 0xff 22/* I/O - Output */ 23#define RT5640_SPK_VOL 0x01 24#define RT5640_HP_VOL 0x02 25#define RT5640_OUTPUT 0x03 26#define RT5640_MONO_OUT 0x04 27/* I/O - Input */ 28#define RT5640_IN1_IN2 0x0d 29#define RT5640_IN3_IN4 0x0e 30#define RT5640_INL_INR_VOL 0x0f 31/* I/O - ADC/DAC/DMIC */ 32#define RT5640_DAC1_DIG_VOL 0x19 33#define RT5640_DAC2_DIG_VOL 0x1a 34#define RT5640_DAC2_CTRL 0x1b 35#define RT5640_ADC_DIG_VOL 0x1c 36#define RT5640_ADC_DATA 0x1d 37#define RT5640_ADC_BST_VOL 0x1e 38/* Mixer - D-D */ 39#define RT5640_STO_ADC_MIXER 0x27 40#define RT5640_MONO_ADC_MIXER 0x28 41#define RT5640_AD_DA_MIXER 0x29 42#define RT5640_STO_DAC_MIXER 0x2a 43#define RT5640_MONO_DAC_MIXER 0x2b 44#define RT5640_DIG_MIXER 0x2c 45#define RT5640_DSP_PATH1 0x2d 46#define RT5640_DSP_PATH2 0x2e 47#define RT5640_DIG_INF_DATA 0x2f 48/* Mixer - ADC */ 49#define RT5640_REC_L1_MIXER 0x3b 50#define RT5640_REC_L2_MIXER 0x3c 51#define RT5640_REC_R1_MIXER 0x3d 52#define RT5640_REC_R2_MIXER 0x3e 53/* Mixer - DAC */ 54#define RT5640_HPO_MIXER 0x45 55#define RT5640_SPK_L_MIXER 0x46 56#define RT5640_SPK_R_MIXER 0x47 57#define RT5640_SPO_L_MIXER 0x48 58#define RT5640_SPO_R_MIXER 0x49 59#define RT5640_SPO_CLSD_RATIO 0x4a 60#define RT5640_MONO_MIXER 0x4c 61#define RT5640_OUT_L1_MIXER 0x4d 62#define RT5640_OUT_L2_MIXER 0x4e 63#define RT5640_OUT_L3_MIXER 0x4f 64#define RT5640_OUT_R1_MIXER 0x50 65#define RT5640_OUT_R2_MIXER 0x51 66#define RT5640_OUT_R3_MIXER 0x52 67#define RT5640_LOUT_MIXER 0x53 68/* Power */ 69#define RT5640_PWR_DIG1 0x61 70#define RT5640_PWR_DIG2 0x62 71#define RT5640_PWR_ANLG1 0x63 72#define RT5640_PWR_ANLG2 0x64 73#define RT5640_PWR_MIXER 0x65 74#define RT5640_PWR_VOL 0x66 75/* Private Register Control */ 76#define RT5640_PRIV_INDEX 0x6a 77#define RT5640_PRIV_DATA 0x6c 78/* Format - ADC/DAC */ 79#define RT5640_I2S1_SDP 0x70 80#define RT5640_I2S2_SDP 0x71 81#define RT5640_ADDA_CLK1 0x73 82#define RT5640_ADDA_CLK2 0x74 83#define RT5640_DMIC 0x75 84/* Function - Analog */ 85#define RT5640_GLB_CLK 0x80 86#define RT5640_PLL_CTRL1 0x81 87#define RT5640_PLL_CTRL2 0x82 88#define RT5640_ASRC_1 0x83 89#define RT5640_ASRC_2 0x84 90#define RT5640_ASRC_3 0x85 91#define RT5640_ASRC_4 0x89 92#define RT5640_ASRC_5 0x8a 93#define RT5640_HP_OVCD 0x8b 94#define RT5640_CLS_D_OVCD 0x8c 95#define RT5640_CLS_D_OUT 0x8d 96#define RT5640_DEPOP_M1 0x8e 97#define RT5640_DEPOP_M2 0x8f 98#define RT5640_DEPOP_M3 0x90 99#define RT5640_CHARGE_PUMP 0x91 100#define RT5640_PV_DET_SPK_G 0x92 101#define RT5640_MICBIAS 0x93 102/* Function - Digital */ 103#define RT5640_EQ_CTRL1 0xb0 104#define RT5640_EQ_CTRL2 0xb1 105#define RT5640_WIND_FILTER 0xb2 106#define RT5640_DRC_AGC_1 0xb4 107#define RT5640_DRC_AGC_2 0xb5 108#define RT5640_DRC_AGC_3 0xb6 109#define RT5640_SVOL_ZC 0xb7 110#define RT5640_ANC_CTRL1 0xb8 111#define RT5640_ANC_CTRL2 0xb9 112#define RT5640_ANC_CTRL3 0xba 113#define RT5640_JD_CTRL 0xbb 114#define RT5640_ANC_JD 0xbc 115#define RT5640_IRQ_CTRL1 0xbd 116#define RT5640_IRQ_CTRL2 0xbe 117#define RT5640_INT_IRQ_ST 0xbf 118#define RT5640_GPIO_CTRL1 0xc0 119#define RT5640_GPIO_CTRL2 0xc1 120#define RT5640_GPIO_CTRL3 0xc2 121#define RT5640_DSP_CTRL1 0xc4 122#define RT5640_DSP_CTRL2 0xc5 123#define RT5640_DSP_CTRL3 0xc6 124#define RT5640_DSP_CTRL4 0xc7 125#define RT5640_PGM_REG_ARR1 0xc8 126#define RT5640_PGM_REG_ARR2 0xc9 127#define RT5640_PGM_REG_ARR3 0xca 128#define RT5640_PGM_REG_ARR4 0xcb 129#define RT5640_PGM_REG_ARR5 0xcc 130#define RT5640_SCB_FUNC 0xcd 131#define RT5640_SCB_CTRL 0xce 132#define RT5640_BASE_BACK 0xcf 133#define RT5640_MP3_PLUS1 0xd0 134#define RT5640_MP3_PLUS2 0xd1 135#define RT5640_3D_HP 0xd2 136#define RT5640_ADJ_HPF 0xd3 137#define RT5640_HP_CALIB_AMP_DET 0xd6 138#define RT5640_HP_CALIB2 0xd7 139#define RT5640_SV_ZCD1 0xd9 140#define RT5640_SV_ZCD2 0xda 141/* Dummy Register */ 142#define RT5640_DUMMY1 0xfa 143#define RT5640_DUMMY2 0xfb 144#define RT5640_DUMMY3 0xfc 145 146 147/* Index of Codec Private Register definition */ 148#define RT5640_CHPUMP_INT_REG1 0x24 149#define RT5640_MAMP_INT_REG2 0x37 150#define RT5640_3D_SPK 0x63 151#define RT5640_WND_1 0x6c 152#define RT5640_WND_2 0x6d 153#define RT5640_WND_3 0x6e 154#define RT5640_WND_4 0x6f 155#define RT5640_WND_5 0x70 156#define RT5640_WND_8 0x73 157#define RT5640_DIP_SPK_INF 0x75 158#define RT5640_HP_DCC_INT1 0x77 159#define RT5640_EQ_BW_LOP 0xa0 160#define RT5640_EQ_GN_LOP 0xa1 161#define RT5640_EQ_FC_BP1 0xa2 162#define RT5640_EQ_BW_BP1 0xa3 163#define RT5640_EQ_GN_BP1 0xa4 164#define RT5640_EQ_FC_BP2 0xa5 165#define RT5640_EQ_BW_BP2 0xa6 166#define RT5640_EQ_GN_BP2 0xa7 167#define RT5640_EQ_FC_BP3 0xa8 168#define RT5640_EQ_BW_BP3 0xa9 169#define RT5640_EQ_GN_BP3 0xaa 170#define RT5640_EQ_FC_BP4 0xab 171#define RT5640_EQ_BW_BP4 0xac 172#define RT5640_EQ_GN_BP4 0xad 173#define RT5640_EQ_FC_HIP1 0xae 174#define RT5640_EQ_GN_HIP1 0xaf 175#define RT5640_EQ_FC_HIP2 0xb0 176#define RT5640_EQ_BW_HIP2 0xb1 177#define RT5640_EQ_GN_HIP2 0xb2 178#define RT5640_EQ_PRE_VOL 0xb3 179#define RT5640_EQ_PST_VOL 0xb4 180 181/* global definition */ 182#define RT5640_L_MUTE (0x1 << 15) 183#define RT5640_L_MUTE_SFT 15 184#define RT5640_VOL_L_MUTE (0x1 << 14) 185#define RT5640_VOL_L_SFT 14 186#define RT5640_R_MUTE (0x1 << 7) 187#define RT5640_R_MUTE_SFT 7 188#define RT5640_VOL_R_MUTE (0x1 << 6) 189#define RT5640_VOL_R_SFT 6 190#define RT5640_L_VOL_MASK (0x3f << 8) 191#define RT5640_L_VOL_SFT 8 192#define RT5640_R_VOL_MASK (0x3f) 193#define RT5640_R_VOL_SFT 0 194 195/* SW Reset & Device ID (0x00) */ 196#define RT5640_ID_MASK (0x3 << 1) 197#define RT5640_ID_5639 (0x0 << 1) 198#define RT5640_ID_5640 (0x2 << 1) 199#define RT5640_ID_5642 (0x3 << 1) 200 201 202/* IN1 and IN2 Control (0x0d) */ 203/* IN3 and IN4 Control (0x0e) */ 204#define RT5640_BST_SFT1 12 205#define RT5640_BST_SFT2 8 206#define RT5640_IN_DF1 (0x1 << 7) 207#define RT5640_IN_SFT1 7 208#define RT5640_IN_DF2 (0x1 << 6) 209#define RT5640_IN_SFT2 6 210 211/* INL and INR Volume Control (0x0f) */ 212#define RT5640_INL_SEL_MASK (0x1 << 15) 213#define RT5640_INL_SEL_SFT 15 214#define RT5640_INL_SEL_IN4P (0x0 << 15) 215#define RT5640_INL_SEL_MONOP (0x1 << 15) 216#define RT5640_INL_VOL_MASK (0x1f << 8) 217#define RT5640_INL_VOL_SFT 8 218#define RT5640_INR_SEL_MASK (0x1 << 7) 219#define RT5640_INR_SEL_SFT 7 220#define RT5640_INR_SEL_IN4N (0x0 << 7) 221#define RT5640_INR_SEL_MONON (0x1 << 7) 222#define RT5640_INR_VOL_MASK (0x1f) 223#define RT5640_INR_VOL_SFT 0 224 225/* DAC1 Digital Volume (0x19) */ 226#define RT5640_DAC_L1_VOL_MASK (0xff << 8) 227#define RT5640_DAC_L1_VOL_SFT 8 228#define RT5640_DAC_R1_VOL_MASK (0xff) 229#define RT5640_DAC_R1_VOL_SFT 0 230 231/* DAC2 Digital Volume (0x1a) */ 232#define RT5640_DAC_L2_VOL_MASK (0xff << 8) 233#define RT5640_DAC_L2_VOL_SFT 8 234#define RT5640_DAC_R2_VOL_MASK (0xff) 235#define RT5640_DAC_R2_VOL_SFT 0 236 237/* DAC2 Control (0x1b) */ 238#define RT5640_M_DAC_L2_VOL (0x1 << 13) 239#define RT5640_M_DAC_L2_VOL_SFT 13 240#define RT5640_M_DAC_R2_VOL (0x1 << 12) 241#define RT5640_M_DAC_R2_VOL_SFT 12 242 243/* ADC Digital Volume Control (0x1c) */ 244#define RT5640_ADC_L_VOL_MASK (0x7f << 8) 245#define RT5640_ADC_L_VOL_SFT 8 246#define RT5640_ADC_R_VOL_MASK (0x7f) 247#define RT5640_ADC_R_VOL_SFT 0 248 249/* Mono ADC Digital Volume Control (0x1d) */ 250#define RT5640_MONO_ADC_L_VOL_MASK (0x7f << 8) 251#define RT5640_MONO_ADC_L_VOL_SFT 8 252#define RT5640_MONO_ADC_R_VOL_MASK (0x7f) 253#define RT5640_MONO_ADC_R_VOL_SFT 0 254 255/* ADC Boost Volume Control (0x1e) */ 256#define RT5640_ADC_L_BST_MASK (0x3 << 14) 257#define RT5640_ADC_L_BST_SFT 14 258#define RT5640_ADC_R_BST_MASK (0x3 << 12) 259#define RT5640_ADC_R_BST_SFT 12 260#define RT5640_ADC_COMP_MASK (0x3 << 10) 261#define RT5640_ADC_COMP_SFT 10 262 263/* Stereo ADC Mixer Control (0x27) */ 264#define RT5640_M_ADC_L1 (0x1 << 14) 265#define RT5640_M_ADC_L1_SFT 14 266#define RT5640_M_ADC_L2 (0x1 << 13) 267#define RT5640_M_ADC_L2_SFT 13 268#define RT5640_ADC_1_SRC_MASK (0x1 << 12) 269#define RT5640_ADC_1_SRC_SFT 12 270#define RT5640_ADC_1_SRC_ADC (0x1 << 12) 271#define RT5640_ADC_1_SRC_DACMIX (0x0 << 12) 272#define RT5640_ADC_2_SRC_MASK (0x3 << 10) 273#define RT5640_ADC_2_SRC_SFT 10 274#define RT5640_ADC_2_SRC_DMIC1 (0x0 << 10) 275#define RT5640_ADC_2_SRC_DMIC2 (0x1 << 10) 276#define RT5640_ADC_2_SRC_DACMIX (0x2 << 10) 277#define RT5640_M_ADC_R1 (0x1 << 6) 278#define RT5640_M_ADC_R1_SFT 6 279#define RT5640_M_ADC_R2 (0x1 << 5) 280#define RT5640_M_ADC_R2_SFT 5 281 282/* Mono ADC Mixer Control (0x28) */ 283#define RT5640_M_MONO_ADC_L1 (0x1 << 14) 284#define RT5640_M_MONO_ADC_L1_SFT 14 285#define RT5640_M_MONO_ADC_L2 (0x1 << 13) 286#define RT5640_M_MONO_ADC_L2_SFT 13 287#define RT5640_MONO_ADC_L1_SRC_MASK (0x1 << 12) 288#define RT5640_MONO_ADC_L1_SRC_SFT 12 289#define RT5640_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12) 290#define RT5640_MONO_ADC_L1_SRC_ADCL (0x1 << 12) 291#define RT5640_MONO_ADC_L2_SRC_MASK (0x3 << 10) 292#define RT5640_MONO_ADC_L2_SRC_SFT 10 293#define RT5640_MONO_ADC_L2_SRC_DMIC_L1 (0x0 << 10) 294#define RT5640_MONO_ADC_L2_SRC_DMIC_L2 (0x1 << 10) 295#define RT5640_MONO_ADC_L2_SRC_DACMIXL (0x2 << 10) 296#define RT5640_M_MONO_ADC_R1 (0x1 << 6) 297#define RT5640_M_MONO_ADC_R1_SFT 6 298#define RT5640_M_MONO_ADC_R2 (0x1 << 5) 299#define RT5640_M_MONO_ADC_R2_SFT 5 300#define RT5640_MONO_ADC_R1_SRC_MASK (0x1 << 4) 301#define RT5640_MONO_ADC_R1_SRC_SFT 4 302#define RT5640_MONO_ADC_R1_SRC_ADCR (0x1 << 4) 303#define RT5640_MONO_ADC_R1_SRC_DACMIXR (0x0 << 4) 304#define RT5640_MONO_ADC_R2_SRC_MASK (0x3 << 2) 305#define RT5640_MONO_ADC_R2_SRC_SFT 2 306#define RT5640_MONO_ADC_R2_SRC_DMIC_R1 (0x0 << 2) 307#define RT5640_MONO_ADC_R2_SRC_DMIC_R2 (0x1 << 2) 308#define RT5640_MONO_ADC_R2_SRC_DACMIXR (0x2 << 2) 309 310/* ADC Mixer to DAC Mixer Control (0x29) */ 311#define RT5640_M_ADCMIX_L (0x1 << 15) 312#define RT5640_M_ADCMIX_L_SFT 15 313#define RT5640_M_IF1_DAC_L (0x1 << 14) 314#define RT5640_M_IF1_DAC_L_SFT 14 315#define RT5640_M_ADCMIX_R (0x1 << 7) 316#define RT5640_M_ADCMIX_R_SFT 7 317#define RT5640_M_IF1_DAC_R (0x1 << 6) 318#define RT5640_M_IF1_DAC_R_SFT 6 319 320/* Stereo DAC Mixer Control (0x2a) */ 321#define RT5640_M_DAC_L1 (0x1 << 14) 322#define RT5640_M_DAC_L1_SFT 14 323#define RT5640_DAC_L1_STO_L_VOL_MASK (0x1 << 13) 324#define RT5640_DAC_L1_STO_L_VOL_SFT 13 325#define RT5640_M_DAC_L2 (0x1 << 12) 326#define RT5640_M_DAC_L2_SFT 12 327#define RT5640_DAC_L2_STO_L_VOL_MASK (0x1 << 11) 328#define RT5640_DAC_L2_STO_L_VOL_SFT 11 329#define RT5640_M_ANC_DAC_L (0x1 << 10) 330#define RT5640_M_ANC_DAC_L_SFT 10 331#define RT5640_M_DAC_R1 (0x1 << 6) 332#define RT5640_M_DAC_R1_SFT 6 333#define RT5640_DAC_R1_STO_R_VOL_MASK (0x1 << 5) 334#define RT5640_DAC_R1_STO_R_VOL_SFT 5 335#define RT5640_M_DAC_R2 (0x1 << 4) 336#define RT5640_M_DAC_R2_SFT 4 337#define RT5640_DAC_R2_STO_R_VOL_MASK (0x1 << 3) 338#define RT5640_DAC_R2_STO_R_VOL_SFT 3 339#define RT5640_M_ANC_DAC_R (0x1 << 2) 340#define RT5640_M_ANC_DAC_R_SFT 2 341 342/* Mono DAC Mixer Control (0x2b) */ 343#define RT5640_M_DAC_L1_MONO_L (0x1 << 14) 344#define RT5640_M_DAC_L1_MONO_L_SFT 14 345#define RT5640_DAC_L1_MONO_L_VOL_MASK (0x1 << 13) 346#define RT5640_DAC_L1_MONO_L_VOL_SFT 13 347#define RT5640_M_DAC_L2_MONO_L (0x1 << 12) 348#define RT5640_M_DAC_L2_MONO_L_SFT 12 349#define RT5640_DAC_L2_MONO_L_VOL_MASK (0x1 << 11) 350#define RT5640_DAC_L2_MONO_L_VOL_SFT 11 351#define RT5640_M_DAC_R2_MONO_L (0x1 << 10) 352#define RT5640_M_DAC_R2_MONO_L_SFT 10 353#define RT5640_DAC_R2_MONO_L_VOL_MASK (0x1 << 9) 354#define RT5640_DAC_R2_MONO_L_VOL_SFT 9 355#define RT5640_M_DAC_R1_MONO_R (0x1 << 6) 356#define RT5640_M_DAC_R1_MONO_R_SFT 6 357#define RT5640_DAC_R1_MONO_R_VOL_MASK (0x1 << 5) 358#define RT5640_DAC_R1_MONO_R_VOL_SFT 5 359#define RT5640_M_DAC_R2_MONO_R (0x1 << 4) 360#define RT5640_M_DAC_R2_MONO_R_SFT 4 361#define RT5640_DAC_R2_MONO_R_VOL_MASK (0x1 << 3) 362#define RT5640_DAC_R2_MONO_R_VOL_SFT 3 363#define RT5640_M_DAC_L2_MONO_R (0x1 << 2) 364#define RT5640_M_DAC_L2_MONO_R_SFT 2 365#define RT5640_DAC_L2_MONO_R_VOL_MASK (0x1 << 1) 366#define RT5640_DAC_L2_MONO_R_VOL_SFT 1 367 368/* Digital Mixer Control (0x2c) */ 369#define RT5640_M_STO_L_DAC_L (0x1 << 15) 370#define RT5640_M_STO_L_DAC_L_SFT 15 371#define RT5640_STO_L_DAC_L_VOL_MASK (0x1 << 14) 372#define RT5640_STO_L_DAC_L_VOL_SFT 14 373#define RT5640_M_DAC_L2_DAC_L (0x1 << 13) 374#define RT5640_M_DAC_L2_DAC_L_SFT 13 375#define RT5640_DAC_L2_DAC_L_VOL_MASK (0x1 << 12) 376#define RT5640_DAC_L2_DAC_L_VOL_SFT 12 377#define RT5640_M_STO_R_DAC_R (0x1 << 11) 378#define RT5640_M_STO_R_DAC_R_SFT 11 379#define RT5640_STO_R_DAC_R_VOL_MASK (0x1 << 10) 380#define RT5640_STO_R_DAC_R_VOL_SFT 10 381#define RT5640_M_DAC_R2_DAC_R (0x1 << 9) 382#define RT5640_M_DAC_R2_DAC_R_SFT 9 383#define RT5640_DAC_R2_DAC_R_VOL_MASK (0x1 << 8) 384#define RT5640_DAC_R2_DAC_R_VOL_SFT 8 385 386/* DSP Path Control 1 (0x2d) */ 387#define RT5640_RXDP_SRC_MASK (0x1 << 15) 388#define RT5640_RXDP_SRC_SFT 15 389#define RT5640_RXDP_SRC_NOR (0x0 << 15) 390#define RT5640_RXDP_SRC_DIV3 (0x1 << 15) 391#define RT5640_TXDP_SRC_MASK (0x1 << 14) 392#define RT5640_TXDP_SRC_SFT 14 393#define RT5640_TXDP_SRC_NOR (0x0 << 14) 394#define RT5640_TXDP_SRC_DIV3 (0x1 << 14) 395 396/* DSP Path Control 2 (0x2e) */ 397#define RT5640_DAC_L2_SEL_MASK (0x3 << 14) 398#define RT5640_DAC_L2_SEL_SFT 14 399#define RT5640_DAC_L2_SEL_IF2 (0x0 << 14) 400#define RT5640_DAC_L2_SEL_IF3 (0x1 << 14) 401#define RT5640_DAC_L2_SEL_TXDC (0x2 << 14) 402#define RT5640_DAC_L2_SEL_BASS (0x3 << 14) 403#define RT5640_DAC_R2_SEL_MASK (0x3 << 12) 404#define RT5640_DAC_R2_SEL_SFT 12 405#define RT5640_DAC_R2_SEL_IF2 (0x0 << 12) 406#define RT5640_DAC_R2_SEL_IF3 (0x1 << 12) 407#define RT5640_DAC_R2_SEL_TXDC (0x2 << 12) 408#define RT5640_IF2_ADC_L_SEL_MASK (0x1 << 11) 409#define RT5640_IF2_ADC_L_SEL_SFT 11 410#define RT5640_IF2_ADC_L_SEL_TXDP (0x0 << 11) 411#define RT5640_IF2_ADC_L_SEL_PASS (0x1 << 11) 412#define RT5640_IF2_ADC_R_SEL_MASK (0x1 << 10) 413#define RT5640_IF2_ADC_R_SEL_SFT 10 414#define RT5640_IF2_ADC_R_SEL_TXDP (0x0 << 10) 415#define RT5640_IF2_ADC_R_SEL_PASS (0x1 << 10) 416#define RT5640_RXDC_SEL_MASK (0x3 << 8) 417#define RT5640_RXDC_SEL_SFT 8 418#define RT5640_RXDC_SEL_NOR (0x0 << 8) 419#define RT5640_RXDC_SEL_L2R (0x1 << 8) 420#define RT5640_RXDC_SEL_R2L (0x2 << 8) 421#define RT5640_RXDC_SEL_SWAP (0x3 << 8) 422#define RT5640_RXDP_SEL_MASK (0x3 << 6) 423#define RT5640_RXDP_SEL_SFT 6 424#define RT5640_RXDP_SEL_NOR (0x0 << 6) 425#define RT5640_RXDP_SEL_L2R (0x1 << 6) 426#define RT5640_RXDP_SEL_R2L (0x2 << 6) 427#define RT5640_RXDP_SEL_SWAP (0x3 << 6) 428#define RT5640_TXDC_SEL_MASK (0x3 << 4) 429#define RT5640_TXDC_SEL_SFT 4 430#define RT5640_TXDC_SEL_NOR (0x0 << 4) 431#define RT5640_TXDC_SEL_L2R (0x1 << 4) 432#define RT5640_TXDC_SEL_R2L (0x2 << 4) 433#define RT5640_TXDC_SEL_SWAP (0x3 << 4) 434#define RT5640_TXDP_SEL_MASK (0x3 << 2) 435#define RT5640_TXDP_SEL_SFT 2 436#define RT5640_TXDP_SEL_NOR (0x0 << 2) 437#define RT5640_TXDP_SEL_L2R (0x1 << 2) 438#define RT5640_TXDP_SEL_R2L (0x2 << 2) 439#define RT5640_TRXDP_SEL_SWAP (0x3 << 2) 440 441/* Digital Interface Data Control (0x2f) */ 442#define RT5640_IF1_DAC_SEL_MASK (0x3 << 14) 443#define RT5640_IF1_DAC_SEL_SFT 14 444#define RT5640_IF1_DAC_SEL_NOR (0x0 << 14) 445#define RT5640_IF1_DAC_SEL_SWAP (0x1 << 14) 446#define RT5640_IF1_DAC_SEL_L2R (0x2 << 14) 447#define RT5640_IF1_DAC_SEL_R2L (0x3 << 14) 448#define RT5640_IF1_ADC_SEL_MASK (0x3 << 12) 449#define RT5640_IF1_ADC_SEL_SFT 12 450#define RT5640_IF1_ADC_SEL_NOR (0x0 << 12) 451#define RT5640_IF1_ADC_SEL_SWAP (0x1 << 12) 452#define RT5640_IF1_ADC_SEL_L2R (0x2 << 12) 453#define RT5640_IF1_ADC_SEL_R2L (0x3 << 12) 454#define RT5640_IF2_DAC_SEL_MASK (0x3 << 10) 455#define RT5640_IF2_DAC_SEL_SFT 10 456#define RT5640_IF2_DAC_SEL_NOR (0x0 << 10) 457#define RT5640_IF2_DAC_SEL_SWAP (0x1 << 10) 458#define RT5640_IF2_DAC_SEL_L2R (0x2 << 10) 459#define RT5640_IF2_DAC_SEL_R2L (0x3 << 10) 460#define RT5640_IF2_ADC_SEL_MASK (0x3 << 8) 461#define RT5640_IF2_ADC_SEL_SFT 8 462#define RT5640_IF2_ADC_SEL_NOR (0x0 << 8) 463#define RT5640_IF2_ADC_SEL_SWAP (0x1 << 8) 464#define RT5640_IF2_ADC_SEL_L2R (0x2 << 8) 465#define RT5640_IF2_ADC_SEL_R2L (0x3 << 8) 466#define RT5640_IF3_DAC_SEL_MASK (0x3 << 6) 467#define RT5640_IF3_DAC_SEL_SFT 6 468#define RT5640_IF3_DAC_SEL_NOR (0x0 << 6) 469#define RT5640_IF3_DAC_SEL_SWAP (0x1 << 6) 470#define RT5640_IF3_DAC_SEL_L2R (0x2 << 6) 471#define RT5640_IF3_DAC_SEL_R2L (0x3 << 6) 472#define RT5640_IF3_ADC_SEL_MASK (0x3 << 4) 473#define RT5640_IF3_ADC_SEL_SFT 4 474#define RT5640_IF3_ADC_SEL_NOR (0x0 << 4) 475#define RT5640_IF3_ADC_SEL_SWAP (0x1 << 4) 476#define RT5640_IF3_ADC_SEL_L2R (0x2 << 4) 477#define RT5640_IF3_ADC_SEL_R2L (0x3 << 4) 478 479/* REC Left Mixer Control 1 (0x3b) */ 480#define RT5640_G_HP_L_RM_L_MASK (0x7 << 13) 481#define RT5640_G_HP_L_RM_L_SFT 13 482#define RT5640_G_IN_L_RM_L_MASK (0x7 << 10) 483#define RT5640_G_IN_L_RM_L_SFT 10 484#define RT5640_G_BST4_RM_L_MASK (0x7 << 7) 485#define RT5640_G_BST4_RM_L_SFT 7 486#define RT5640_G_BST3_RM_L_MASK (0x7 << 4) 487#define RT5640_G_BST3_RM_L_SFT 4 488#define RT5640_G_BST2_RM_L_MASK (0x7 << 1) 489#define RT5640_G_BST2_RM_L_SFT 1 490 491/* REC Left Mixer Control 2 (0x3c) */ 492#define RT5640_G_BST1_RM_L_MASK (0x7 << 13) 493#define RT5640_G_BST1_RM_L_SFT 13 494#define RT5640_G_OM_L_RM_L_MASK (0x7 << 10) 495#define RT5640_G_OM_L_RM_L_SFT 10 496#define RT5640_M_HP_L_RM_L (0x1 << 6) 497#define RT5640_M_HP_L_RM_L_SFT 6 498#define RT5640_M_IN_L_RM_L (0x1 << 5) 499#define RT5640_M_IN_L_RM_L_SFT 5 500#define RT5640_M_BST4_RM_L (0x1 << 4) 501#define RT5640_M_BST4_RM_L_SFT 4 502#define RT5640_M_BST3_RM_L (0x1 << 3) 503#define RT5640_M_BST3_RM_L_SFT 3 504#define RT5640_M_BST2_RM_L (0x1 << 2) 505#define RT5640_M_BST2_RM_L_SFT 2 506#define RT5640_M_BST1_RM_L (0x1 << 1) 507#define RT5640_M_BST1_RM_L_SFT 1 508#define RT5640_M_OM_L_RM_L (0x1) 509#define RT5640_M_OM_L_RM_L_SFT 0 510 511/* REC Right Mixer Control 1 (0x3d) */ 512#define RT5640_G_HP_R_RM_R_MASK (0x7 << 13) 513#define RT5640_G_HP_R_RM_R_SFT 13 514#define RT5640_G_IN_R_RM_R_MASK (0x7 << 10) 515#define RT5640_G_IN_R_RM_R_SFT 10 516#define RT5640_G_BST4_RM_R_MASK (0x7 << 7) 517#define RT5640_G_BST4_RM_R_SFT 7 518#define RT5640_G_BST3_RM_R_MASK (0x7 << 4) 519#define RT5640_G_BST3_RM_R_SFT 4 520#define RT5640_G_BST2_RM_R_MASK (0x7 << 1) 521#define RT5640_G_BST2_RM_R_SFT 1 522 523/* REC Right Mixer Control 2 (0x3e) */ 524#define RT5640_G_BST1_RM_R_MASK (0x7 << 13) 525#define RT5640_G_BST1_RM_R_SFT 13 526#define RT5640_G_OM_R_RM_R_MASK (0x7 << 10) 527#define RT5640_G_OM_R_RM_R_SFT 10 528#define RT5640_M_HP_R_RM_R (0x1 << 6) 529#define RT5640_M_HP_R_RM_R_SFT 6 530#define RT5640_M_IN_R_RM_R (0x1 << 5) 531#define RT5640_M_IN_R_RM_R_SFT 5 532#define RT5640_M_BST4_RM_R (0x1 << 4) 533#define RT5640_M_BST4_RM_R_SFT 4 534#define RT5640_M_BST3_RM_R (0x1 << 3) 535#define RT5640_M_BST3_RM_R_SFT 3 536#define RT5640_M_BST2_RM_R (0x1 << 2) 537#define RT5640_M_BST2_RM_R_SFT 2 538#define RT5640_M_BST1_RM_R (0x1 << 1) 539#define RT5640_M_BST1_RM_R_SFT 1 540#define RT5640_M_OM_R_RM_R (0x1) 541#define RT5640_M_OM_R_RM_R_SFT 0 542 543/* HPMIX Control (0x45) */ 544#define RT5640_M_DAC2_HM (0x1 << 15) 545#define RT5640_M_DAC2_HM_SFT 15 546#define RT5640_M_DAC1_HM (0x1 << 14) 547#define RT5640_M_DAC1_HM_SFT 14 548#define RT5640_M_HPVOL_HM (0x1 << 13) 549#define RT5640_M_HPVOL_HM_SFT 13 550#define RT5640_G_HPOMIX_MASK (0x1 << 12) 551#define RT5640_G_HPOMIX_SFT 12 552 553/* SPK Left Mixer Control (0x46) */ 554#define RT5640_G_RM_L_SM_L_MASK (0x3 << 14) 555#define RT5640_G_RM_L_SM_L_SFT 14 556#define RT5640_G_IN_L_SM_L_MASK (0x3 << 12) 557#define RT5640_G_IN_L_SM_L_SFT 12 558#define RT5640_G_DAC_L1_SM_L_MASK (0x3 << 10) 559#define RT5640_G_DAC_L1_SM_L_SFT 10 560#define RT5640_G_DAC_L2_SM_L_MASK (0x3 << 8) 561#define RT5640_G_DAC_L2_SM_L_SFT 8 562#define RT5640_G_OM_L_SM_L_MASK (0x3 << 6) 563#define RT5640_G_OM_L_SM_L_SFT 6 564#define RT5640_M_RM_L_SM_L (0x1 << 5) 565#define RT5640_M_RM_L_SM_L_SFT 5 566#define RT5640_M_IN_L_SM_L (0x1 << 4) 567#define RT5640_M_IN_L_SM_L_SFT 4 568#define RT5640_M_DAC_L1_SM_L (0x1 << 3) 569#define RT5640_M_DAC_L1_SM_L_SFT 3 570#define RT5640_M_DAC_L2_SM_L (0x1 << 2) 571#define RT5640_M_DAC_L2_SM_L_SFT 2 572#define RT5640_M_OM_L_SM_L (0x1 << 1) 573#define RT5640_M_OM_L_SM_L_SFT 1 574 575/* SPK Right Mixer Control (0x47) */ 576#define RT5640_G_RM_R_SM_R_MASK (0x3 << 14) 577#define RT5640_G_RM_R_SM_R_SFT 14 578#define RT5640_G_IN_R_SM_R_MASK (0x3 << 12) 579#define RT5640_G_IN_R_SM_R_SFT 12 580#define RT5640_G_DAC_R1_SM_R_MASK (0x3 << 10) 581#define RT5640_G_DAC_R1_SM_R_SFT 10 582#define RT5640_G_DAC_R2_SM_R_MASK (0x3 << 8) 583#define RT5640_G_DAC_R2_SM_R_SFT 8 584#define RT5640_G_OM_R_SM_R_MASK (0x3 << 6) 585#define RT5640_G_OM_R_SM_R_SFT 6 586#define RT5640_M_RM_R_SM_R (0x1 << 5) 587#define RT5640_M_RM_R_SM_R_SFT 5 588#define RT5640_M_IN_R_SM_R (0x1 << 4) 589#define RT5640_M_IN_R_SM_R_SFT 4 590#define RT5640_M_DAC_R1_SM_R (0x1 << 3) 591#define RT5640_M_DAC_R1_SM_R_SFT 3 592#define RT5640_M_DAC_R2_SM_R (0x1 << 2) 593#define RT5640_M_DAC_R2_SM_R_SFT 2 594#define RT5640_M_OM_R_SM_R (0x1 << 1) 595#define RT5640_M_OM_R_SM_R_SFT 1 596 597/* SPOLMIX Control (0x48) */ 598#define RT5640_M_DAC_R1_SPM_L (0x1 << 15) 599#define RT5640_M_DAC_R1_SPM_L_SFT 15 600#define RT5640_M_DAC_L1_SPM_L (0x1 << 14) 601#define RT5640_M_DAC_L1_SPM_L_SFT 14 602#define RT5640_M_SV_R_SPM_L (0x1 << 13) 603#define RT5640_M_SV_R_SPM_L_SFT 13 604#define RT5640_M_SV_L_SPM_L (0x1 << 12) 605#define RT5640_M_SV_L_SPM_L_SFT 12 606#define RT5640_M_BST1_SPM_L (0x1 << 11) 607#define RT5640_M_BST1_SPM_L_SFT 11 608 609/* SPORMIX Control (0x49) */ 610#define RT5640_M_DAC_R1_SPM_R (0x1 << 13) 611#define RT5640_M_DAC_R1_SPM_R_SFT 13 612#define RT5640_M_SV_R_SPM_R (0x1 << 12) 613#define RT5640_M_SV_R_SPM_R_SFT 12 614#define RT5640_M_BST1_SPM_R (0x1 << 11) 615#define RT5640_M_BST1_SPM_R_SFT 11 616 617/* SPOLMIX / SPORMIX Ratio Control (0x4a) */ 618#define RT5640_SPO_CLSD_RATIO_MASK (0x7) 619#define RT5640_SPO_CLSD_RATIO_SFT 0 620 621/* Mono Output Mixer Control (0x4c) */ 622#define RT5640_M_DAC_R2_MM (0x1 << 15) 623#define RT5640_M_DAC_R2_MM_SFT 15 624#define RT5640_M_DAC_L2_MM (0x1 << 14) 625#define RT5640_M_DAC_L2_MM_SFT 14 626#define RT5640_M_OV_R_MM (0x1 << 13) 627#define RT5640_M_OV_R_MM_SFT 13 628#define RT5640_M_OV_L_MM (0x1 << 12) 629#define RT5640_M_OV_L_MM_SFT 12 630#define RT5640_M_BST1_MM (0x1 << 11) 631#define RT5640_M_BST1_MM_SFT 11 632#define RT5640_G_MONOMIX_MASK (0x1 << 10) 633#define RT5640_G_MONOMIX_SFT 10 634 635/* Output Left Mixer Control 1 (0x4d) */ 636#define RT5640_G_BST3_OM_L_MASK (0x7 << 13) 637#define RT5640_G_BST3_OM_L_SFT 13 638#define RT5640_G_BST2_OM_L_MASK (0x7 << 10) 639#define RT5640_G_BST2_OM_L_SFT 10 640#define RT5640_G_BST1_OM_L_MASK (0x7 << 7) 641#define RT5640_G_BST1_OM_L_SFT 7 642#define RT5640_G_IN_L_OM_L_MASK (0x7 << 4) 643#define RT5640_G_IN_L_OM_L_SFT 4 644#define RT5640_G_RM_L_OM_L_MASK (0x7 << 1) 645#define RT5640_G_RM_L_OM_L_SFT 1 646 647/* Output Left Mixer Control 2 (0x4e) */ 648#define RT5640_G_DAC_R2_OM_L_MASK (0x7 << 13) 649#define RT5640_G_DAC_R2_OM_L_SFT 13 650#define RT5640_G_DAC_L2_OM_L_MASK (0x7 << 10) 651#define RT5640_G_DAC_L2_OM_L_SFT 10 652#define RT5640_G_DAC_L1_OM_L_MASK (0x7 << 7) 653#define RT5640_G_DAC_L1_OM_L_SFT 7 654 655/* Output Left Mixer Control 3 (0x4f) */ 656#define RT5640_M_SM_L_OM_L (0x1 << 8) 657#define RT5640_M_SM_L_OM_L_SFT 8 658#define RT5640_M_BST3_OM_L (0x1 << 7) 659#define RT5640_M_BST3_OM_L_SFT 7 660#define RT5640_M_BST2_OM_L (0x1 << 6) 661#define RT5640_M_BST2_OM_L_SFT 6 662#define RT5640_M_BST1_OM_L (0x1 << 5) 663#define RT5640_M_BST1_OM_L_SFT 5 664#define RT5640_M_IN_L_OM_L (0x1 << 4) 665#define RT5640_M_IN_L_OM_L_SFT 4 666#define RT5640_M_RM_L_OM_L (0x1 << 3) 667#define RT5640_M_RM_L_OM_L_SFT 3 668#define RT5640_M_DAC_R2_OM_L (0x1 << 2) 669#define RT5640_M_DAC_R2_OM_L_SFT 2 670#define RT5640_M_DAC_L2_OM_L (0x1 << 1) 671#define RT5640_M_DAC_L2_OM_L_SFT 1 672#define RT5640_M_DAC_L1_OM_L (0x1) 673#define RT5640_M_DAC_L1_OM_L_SFT 0 674 675/* Output Right Mixer Control 1 (0x50) */ 676#define RT5640_G_BST4_OM_R_MASK (0x7 << 13) 677#define RT5640_G_BST4_OM_R_SFT 13 678#define RT5640_G_BST2_OM_R_MASK (0x7 << 10) 679#define RT5640_G_BST2_OM_R_SFT 10 680#define RT5640_G_BST1_OM_R_MASK (0x7 << 7) 681#define RT5640_G_BST1_OM_R_SFT 7 682#define RT5640_G_IN_R_OM_R_MASK (0x7 << 4) 683#define RT5640_G_IN_R_OM_R_SFT 4 684#define RT5640_G_RM_R_OM_R_MASK (0x7 << 1) 685#define RT5640_G_RM_R_OM_R_SFT 1 686 687/* Output Right Mixer Control 2 (0x51) */ 688#define RT5640_G_DAC_L2_OM_R_MASK (0x7 << 13) 689#define RT5640_G_DAC_L2_OM_R_SFT 13 690#define RT5640_G_DAC_R2_OM_R_MASK (0x7 << 10) 691#define RT5640_G_DAC_R2_OM_R_SFT 10 692#define RT5640_G_DAC_R1_OM_R_MASK (0x7 << 7) 693#define RT5640_G_DAC_R1_OM_R_SFT 7 694 695/* Output Right Mixer Control 3 (0x52) */ 696#define RT5640_M_SM_L_OM_R (0x1 << 8) 697#define RT5640_M_SM_L_OM_R_SFT 8 698#define RT5640_M_BST4_OM_R (0x1 << 7) 699#define RT5640_M_BST4_OM_R_SFT 7 700#define RT5640_M_BST2_OM_R (0x1 << 6) 701#define RT5640_M_BST2_OM_R_SFT 6 702#define RT5640_M_BST1_OM_R (0x1 << 5) 703#define RT5640_M_BST1_OM_R_SFT 5 704#define RT5640_M_IN_R_OM_R (0x1 << 4) 705#define RT5640_M_IN_R_OM_R_SFT 4 706#define RT5640_M_RM_R_OM_R (0x1 << 3) 707#define RT5640_M_RM_R_OM_R_SFT 3 708#define RT5640_M_DAC_L2_OM_R (0x1 << 2) 709#define RT5640_M_DAC_L2_OM_R_SFT 2 710#define RT5640_M_DAC_R2_OM_R (0x1 << 1) 711#define RT5640_M_DAC_R2_OM_R_SFT 1 712#define RT5640_M_DAC_R1_OM_R (0x1) 713#define RT5640_M_DAC_R1_OM_R_SFT 0 714 715/* LOUT Mixer Control (0x53) */ 716#define RT5640_M_DAC_L1_LM (0x1 << 15) 717#define RT5640_M_DAC_L1_LM_SFT 15 718#define RT5640_M_DAC_R1_LM (0x1 << 14) 719#define RT5640_M_DAC_R1_LM_SFT 14 720#define RT5640_M_OV_L_LM (0x1 << 13) 721#define RT5640_M_OV_L_LM_SFT 13 722#define RT5640_M_OV_R_LM (0x1 << 12) 723#define RT5640_M_OV_R_LM_SFT 12 724#define RT5640_G_LOUTMIX_MASK (0x1 << 11) 725#define RT5640_G_LOUTMIX_SFT 11 726 727/* Power Management for Digital 1 (0x61) */ 728#define RT5640_PWR_I2S1 (0x1 << 15) 729#define RT5640_PWR_I2S1_BIT 15 730#define RT5640_PWR_I2S2 (0x1 << 14) 731#define RT5640_PWR_I2S2_BIT 14 732#define RT5640_PWR_DAC_L1 (0x1 << 12) 733#define RT5640_PWR_DAC_L1_BIT 12 734#define RT5640_PWR_DAC_R1 (0x1 << 11) 735#define RT5640_PWR_DAC_R1_BIT 11 736#define RT5640_PWR_DAC_L2 (0x1 << 7) 737#define RT5640_PWR_DAC_L2_BIT 7 738#define RT5640_PWR_DAC_R2 (0x1 << 6) 739#define RT5640_PWR_DAC_R2_BIT 6 740#define RT5640_PWR_ADC_L (0x1 << 2) 741#define RT5640_PWR_ADC_L_BIT 2 742#define RT5640_PWR_ADC_R (0x1 << 1) 743#define RT5640_PWR_ADC_R_BIT 1 744#define RT5640_PWR_CLS_D (0x1) 745#define RT5640_PWR_CLS_D_BIT 0 746 747/* Power Management for Digital 2 (0x62) */ 748#define RT5640_PWR_ADC_SF (0x1 << 15) 749#define RT5640_PWR_ADC_SF_BIT 15 750#define RT5640_PWR_ADC_MF_L (0x1 << 14) 751#define RT5640_PWR_ADC_MF_L_BIT 14 752#define RT5640_PWR_ADC_MF_R (0x1 << 13) 753#define RT5640_PWR_ADC_MF_R_BIT 13 754#define RT5640_PWR_I2S_DSP (0x1 << 12) 755#define RT5640_PWR_I2S_DSP_BIT 12 756 757/* Power Management for Analog 1 (0x63) */ 758#define RT5640_PWR_VREF1 (0x1 << 15) 759#define RT5640_PWR_VREF1_BIT 15 760#define RT5640_PWR_FV1 (0x1 << 14) 761#define RT5640_PWR_FV1_BIT 14 762#define RT5640_PWR_MB (0x1 << 13) 763#define RT5640_PWR_MB_BIT 13 764#define RT5640_PWR_LM (0x1 << 12) 765#define RT5640_PWR_LM_BIT 12 766#define RT5640_PWR_BG (0x1 << 11) 767#define RT5640_PWR_BG_BIT 11 768#define RT5640_PWR_MM (0x1 << 10) 769#define RT5640_PWR_MM_BIT 10 770#define RT5640_PWR_MA (0x1 << 8) 771#define RT5640_PWR_MA_BIT 8 772#define RT5640_PWR_HP_L (0x1 << 7) 773#define RT5640_PWR_HP_L_BIT 7 774#define RT5640_PWR_HP_R (0x1 << 6) 775#define RT5640_PWR_HP_R_BIT 6 776#define RT5640_PWR_HA (0x1 << 5) 777#define RT5640_PWR_HA_BIT 5 778#define RT5640_PWR_VREF2 (0x1 << 4) 779#define RT5640_PWR_VREF2_BIT 4 780#define RT5640_PWR_FV2 (0x1 << 3) 781#define RT5640_PWR_FV2_BIT 3 782#define RT5640_PWR_LDO2 (0x1 << 2) 783#define RT5640_PWR_LDO2_BIT 2 784 785/* Power Management for Analog 2 (0x64) */ 786#define RT5640_PWR_BST1 (0x1 << 15) 787#define RT5640_PWR_BST1_BIT 15 788#define RT5640_PWR_BST2 (0x1 << 14) 789#define RT5640_PWR_BST2_BIT 14 790#define RT5640_PWR_BST3 (0x1 << 13) 791#define RT5640_PWR_BST3_BIT 13 792#define RT5640_PWR_BST4 (0x1 << 12) 793#define RT5640_PWR_BST4_BIT 12 794#define RT5640_PWR_MB1 (0x1 << 11) 795#define RT5640_PWR_MB1_BIT 11 796#define RT5640_PWR_PLL (0x1 << 9) 797#define RT5640_PWR_PLL_BIT 9 798 799/* Power Management for Mixer (0x65) */ 800#define RT5640_PWR_OM_L (0x1 << 15) 801#define RT5640_PWR_OM_L_BIT 15 802#define RT5640_PWR_OM_R (0x1 << 14) 803#define RT5640_PWR_OM_R_BIT 14 804#define RT5640_PWR_SM_L (0x1 << 13) 805#define RT5640_PWR_SM_L_BIT 13 806#define RT5640_PWR_SM_R (0x1 << 12) 807#define RT5640_PWR_SM_R_BIT 12 808#define RT5640_PWR_RM_L (0x1 << 11) 809#define RT5640_PWR_RM_L_BIT 11 810#define RT5640_PWR_RM_R (0x1 << 10) 811#define RT5640_PWR_RM_R_BIT 10 812 813/* Power Management for Volume (0x66) */ 814#define RT5640_PWR_SV_L (0x1 << 15) 815#define RT5640_PWR_SV_L_BIT 15 816#define RT5640_PWR_SV_R (0x1 << 14) 817#define RT5640_PWR_SV_R_BIT 14 818#define RT5640_PWR_OV_L (0x1 << 13) 819#define RT5640_PWR_OV_L_BIT 13 820#define RT5640_PWR_OV_R (0x1 << 12) 821#define RT5640_PWR_OV_R_BIT 12 822#define RT5640_PWR_HV_L (0x1 << 11) 823#define RT5640_PWR_HV_L_BIT 11 824#define RT5640_PWR_HV_R (0x1 << 10) 825#define RT5640_PWR_HV_R_BIT 10 826#define RT5640_PWR_IN_L (0x1 << 9) 827#define RT5640_PWR_IN_L_BIT 9 828#define RT5640_PWR_IN_R (0x1 << 8) 829#define RT5640_PWR_IN_R_BIT 8 830 831/* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71 0x72) */ 832#define RT5640_I2S_MS_MASK (0x1 << 15) 833#define RT5640_I2S_MS_SFT 15 834#define RT5640_I2S_MS_M (0x0 << 15) 835#define RT5640_I2S_MS_S (0x1 << 15) 836#define RT5640_I2S_IF_MASK (0x7 << 12) 837#define RT5640_I2S_IF_SFT 12 838#define RT5640_I2S_O_CP_MASK (0x3 << 10) 839#define RT5640_I2S_O_CP_SFT 10 840#define RT5640_I2S_O_CP_OFF (0x0 << 10) 841#define RT5640_I2S_O_CP_U_LAW (0x1 << 10) 842#define RT5640_I2S_O_CP_A_LAW (0x2 << 10) 843#define RT5640_I2S_I_CP_MASK (0x3 << 8) 844#define RT5640_I2S_I_CP_SFT 8 845#define RT5640_I2S_I_CP_OFF (0x0 << 8) 846#define RT5640_I2S_I_CP_U_LAW (0x1 << 8) 847#define RT5640_I2S_I_CP_A_LAW (0x2 << 8) 848#define RT5640_I2S_BP_MASK (0x1 << 7) 849#define RT5640_I2S_BP_SFT 7 850#define RT5640_I2S_BP_NOR (0x0 << 7) 851#define RT5640_I2S_BP_INV (0x1 << 7) 852#define RT5640_I2S_DL_MASK (0x3 << 2) 853#define RT5640_I2S_DL_SFT 2 854#define RT5640_I2S_DL_16 (0x0 << 2) 855#define RT5640_I2S_DL_20 (0x1 << 2) 856#define RT5640_I2S_DL_24 (0x2 << 2) 857#define RT5640_I2S_DL_8 (0x3 << 2) 858#define RT5640_I2S_DF_MASK (0x3) 859#define RT5640_I2S_DF_SFT 0 860#define RT5640_I2S_DF_I2S (0x0) 861#define RT5640_I2S_DF_LEFT (0x1) 862#define RT5640_I2S_DF_PCM_A (0x2) 863#define RT5640_I2S_DF_PCM_B (0x3) 864 865/* I2S2 Audio Serial Data Port Control (0x71) */ 866#define RT5640_I2S2_SDI_MASK (0x1 << 6) 867#define RT5640_I2S2_SDI_SFT 6 868#define RT5640_I2S2_SDI_I2S1 (0x0 << 6) 869#define RT5640_I2S2_SDI_I2S2 (0x1 << 6) 870 871/* ADC/DAC Clock Control 1 (0x73) */ 872#define RT5640_I2S_BCLK_MS1_MASK (0x1 << 15) 873#define RT5640_I2S_BCLK_MS1_SFT 15 874#define RT5640_I2S_BCLK_MS1_32 (0x0 << 15) 875#define RT5640_I2S_BCLK_MS1_64 (0x1 << 15) 876#define RT5640_I2S_PD1_MASK (0x7 << 12) 877#define RT5640_I2S_PD1_SFT 12 878#define RT5640_I2S_PD1_1 (0x0 << 12) 879#define RT5640_I2S_PD1_2 (0x1 << 12) 880#define RT5640_I2S_PD1_3 (0x2 << 12) 881#define RT5640_I2S_PD1_4 (0x3 << 12) 882#define RT5640_I2S_PD1_6 (0x4 << 12) 883#define RT5640_I2S_PD1_8 (0x5 << 12) 884#define RT5640_I2S_PD1_12 (0x6 << 12) 885#define RT5640_I2S_PD1_16 (0x7 << 12) 886#define RT5640_I2S_BCLK_MS2_MASK (0x1 << 11) 887#define RT5640_I2S_BCLK_MS2_SFT 11 888#define RT5640_I2S_BCLK_MS2_32 (0x0 << 11) 889#define RT5640_I2S_BCLK_MS2_64 (0x1 << 11) 890#define RT5640_I2S_PD2_MASK (0x7 << 8) 891#define RT5640_I2S_PD2_SFT 8 892#define RT5640_I2S_PD2_1 (0x0 << 8) 893#define RT5640_I2S_PD2_2 (0x1 << 8) 894#define RT5640_I2S_PD2_3 (0x2 << 8) 895#define RT5640_I2S_PD2_4 (0x3 << 8) 896#define RT5640_I2S_PD2_6 (0x4 << 8) 897#define RT5640_I2S_PD2_8 (0x5 << 8) 898#define RT5640_I2S_PD2_12 (0x6 << 8) 899#define RT5640_I2S_PD2_16 (0x7 << 8) 900#define RT5640_I2S_BCLK_MS3_MASK (0x1 << 7) 901#define RT5640_I2S_BCLK_MS3_SFT 7 902#define RT5640_I2S_BCLK_MS3_32 (0x0 << 7) 903#define RT5640_I2S_BCLK_MS3_64 (0x1 << 7) 904#define RT5640_I2S_PD3_MASK (0x7 << 4) 905#define RT5640_I2S_PD3_SFT 4 906#define RT5640_I2S_PD3_1 (0x0 << 4) 907#define RT5640_I2S_PD3_2 (0x1 << 4) 908#define RT5640_I2S_PD3_3 (0x2 << 4) 909#define RT5640_I2S_PD3_4 (0x3 << 4) 910#define RT5640_I2S_PD3_6 (0x4 << 4) 911#define RT5640_I2S_PD3_8 (0x5 << 4) 912#define RT5640_I2S_PD3_12 (0x6 << 4) 913#define RT5640_I2S_PD3_16 (0x7 << 4) 914#define RT5640_DAC_OSR_MASK (0x3 << 2) 915#define RT5640_DAC_OSR_SFT 2 916#define RT5640_DAC_OSR_128 (0x0 << 2) 917#define RT5640_DAC_OSR_64 (0x1 << 2) 918#define RT5640_DAC_OSR_32 (0x2 << 2) 919#define RT5640_DAC_OSR_16 (0x3 << 2) 920#define RT5640_ADC_OSR_MASK (0x3) 921#define RT5640_ADC_OSR_SFT 0 922#define RT5640_ADC_OSR_128 (0x0) 923#define RT5640_ADC_OSR_64 (0x1) 924#define RT5640_ADC_OSR_32 (0x2) 925#define RT5640_ADC_OSR_16 (0x3) 926 927/* ADC/DAC Clock Control 2 (0x74) */ 928#define RT5640_DAC_L_OSR_MASK (0x3 << 14) 929#define RT5640_DAC_L_OSR_SFT 14 930#define RT5640_DAC_L_OSR_128 (0x0 << 14) 931#define RT5640_DAC_L_OSR_64 (0x1 << 14) 932#define RT5640_DAC_L_OSR_32 (0x2 << 14) 933#define RT5640_DAC_L_OSR_16 (0x3 << 14) 934#define RT5640_ADC_R_OSR_MASK (0x3 << 12) 935#define RT5640_ADC_R_OSR_SFT 12 936#define RT5640_ADC_R_OSR_128 (0x0 << 12) 937#define RT5640_ADC_R_OSR_64 (0x1 << 12) 938#define RT5640_ADC_R_OSR_32 (0x2 << 12) 939#define RT5640_ADC_R_OSR_16 (0x3 << 12) 940#define RT5640_DAHPF_EN (0x1 << 11) 941#define RT5640_DAHPF_EN_SFT 11 942#define RT5640_ADHPF_EN (0x1 << 10) 943#define RT5640_ADHPF_EN_SFT 10 944 945/* Digital Microphone Control (0x75) */ 946#define RT5640_DMIC_1_EN_MASK (0x1 << 15) 947#define RT5640_DMIC_1_EN_SFT 15 948#define RT5640_DMIC_1_DIS (0x0 << 15) 949#define RT5640_DMIC_1_EN (0x1 << 15) 950#define RT5640_DMIC_2_EN_MASK (0x1 << 14) 951#define RT5640_DMIC_2_EN_SFT 14 952#define RT5640_DMIC_2_DIS (0x0 << 14) 953#define RT5640_DMIC_2_EN (0x1 << 14) 954#define RT5640_DMIC_1L_LH_MASK (0x1 << 13) 955#define RT5640_DMIC_1L_LH_SFT 13 956#define RT5640_DMIC_1L_LH_FALLING (0x0 << 13) 957#define RT5640_DMIC_1L_LH_RISING (0x1 << 13) 958#define RT5640_DMIC_1R_LH_MASK (0x1 << 12) 959#define RT5640_DMIC_1R_LH_SFT 12 960#define RT5640_DMIC_1R_LH_FALLING (0x0 << 12) 961#define RT5640_DMIC_1R_LH_RISING (0x1 << 12) 962#define RT5640_DMIC_1_DP_MASK (0x1 << 11) 963#define RT5640_DMIC_1_DP_SFT 11 964#define RT5640_DMIC_1_DP_GPIO3 (0x0 << 11) 965#define RT5640_DMIC_1_DP_IN1P (0x1 << 11) 966#define RT5640_DMIC_2_DP_MASK (0x1 << 10) 967#define RT5640_DMIC_2_DP_SFT 10 968#define RT5640_DMIC_2_DP_GPIO4 (0x0 << 10) 969#define RT5640_DMIC_2_DP_IN1N (0x1 << 10) 970#define RT5640_DMIC_2L_LH_MASK (0x1 << 9) 971#define RT5640_DMIC_2L_LH_SFT 9 972#define RT5640_DMIC_2L_LH_FALLING (0x0 << 9) 973#define RT5640_DMIC_2L_LH_RISING (0x1 << 9) 974#define RT5640_DMIC_2R_LH_MASK (0x1 << 8) 975#define RT5640_DMIC_2R_LH_SFT 8 976#define RT5640_DMIC_2R_LH_FALLING (0x0 << 8) 977#define RT5640_DMIC_2R_LH_RISING (0x1 << 8) 978#define RT5640_DMIC_CLK_MASK (0x7 << 5) 979#define RT5640_DMIC_CLK_SFT 5 980 981/* Global Clock Control (0x80) */ 982#define RT5640_SCLK_SRC_MASK (0x3 << 14) 983#define RT5640_SCLK_SRC_SFT 14 984#define RT5640_SCLK_SRC_MCLK (0x0 << 14) 985#define RT5640_SCLK_SRC_PLL1 (0x1 << 14) 986#define RT5640_PLL1_SRC_MASK (0x3 << 12) 987#define RT5640_PLL1_SRC_SFT 12 988#define RT5640_PLL1_SRC_MCLK (0x0 << 12) 989#define RT5640_PLL1_SRC_BCLK1 (0x1 << 12) 990#define RT5640_PLL1_SRC_BCLK2 (0x2 << 12) 991#define RT5640_PLL1_SRC_BCLK3 (0x3 << 12) 992#define RT5640_PLL1_PD_MASK (0x1 << 3) 993#define RT5640_PLL1_PD_SFT 3 994#define RT5640_PLL1_PD_1 (0x0 << 3) 995#define RT5640_PLL1_PD_2 (0x1 << 3) 996 997#define RT5640_PLL_INP_MAX 40000000 998#define RT5640_PLL_INP_MIN 256000 999/* PLL M/N/K Code Control 1 (0x81) */ 1000#define RT5640_PLL_N_MAX 0x1ff 1001#define RT5640_PLL_N_MASK (RT5640_PLL_N_MAX << 7) 1002#define RT5640_PLL_N_SFT 7 1003#define RT5640_PLL_K_MAX 0x1f 1004#define RT5640_PLL_K_MASK (RT5640_PLL_K_MAX) 1005#define RT5640_PLL_K_SFT 0 1006 1007/* PLL M/N/K Code Control 2 (0x82) */ 1008#define RT5640_PLL_M_MAX 0xf 1009#define RT5640_PLL_M_MASK (RT5640_PLL_M_MAX << 12) 1010#define RT5640_PLL_M_SFT 12 1011#define RT5640_PLL_M_BP (0x1 << 11) 1012#define RT5640_PLL_M_BP_SFT 11 1013 1014/* ASRC Control 1 (0x83) */ 1015#define RT5640_STO_T_MASK (0x1 << 15) 1016#define RT5640_STO_T_SFT 15 1017#define RT5640_STO_T_SCLK (0x0 << 15) 1018#define RT5640_STO_T_LRCK1 (0x1 << 15) 1019#define RT5640_M1_T_MASK (0x1 << 14) 1020#define RT5640_M1_T_SFT 14 1021#define RT5640_M1_T_I2S2 (0x0 << 14) 1022#define RT5640_M1_T_I2S2_D3 (0x1 << 14) 1023#define RT5640_I2S2_F_MASK (0x1 << 12) 1024#define RT5640_I2S2_F_SFT 12 1025#define RT5640_I2S2_F_I2S2_D2 (0x0 << 12) 1026#define RT5640_I2S2_F_I2S1_TCLK (0x1 << 12) 1027#define RT5640_DMIC_1_M_MASK (0x1 << 9) 1028#define RT5640_DMIC_1_M_SFT 9 1029#define RT5640_DMIC_1_M_NOR (0x0 << 9) 1030#define RT5640_DMIC_1_M_ASYN (0x1 << 9) 1031#define RT5640_DMIC_2_M_MASK (0x1 << 8) 1032#define RT5640_DMIC_2_M_SFT 8 1033#define RT5640_DMIC_2_M_NOR (0x0 << 8) 1034#define RT5640_DMIC_2_M_ASYN (0x1 << 8) 1035 1036/* ASRC Control 2 (0x84) */ 1037#define RT5640_MDA_L_M_MASK (0x1 << 15) 1038#define RT5640_MDA_L_M_SFT 15 1039#define RT5640_MDA_L_M_NOR (0x0 << 15) 1040#define RT5640_MDA_L_M_ASYN (0x1 << 15) 1041#define RT5640_MDA_R_M_MASK (0x1 << 14) 1042#define RT5640_MDA_R_M_SFT 14 1043#define RT5640_MDA_R_M_NOR (0x0 << 14) 1044#define RT5640_MDA_R_M_ASYN (0x1 << 14) 1045#define RT5640_MAD_L_M_MASK (0x1 << 13) 1046#define RT5640_MAD_L_M_SFT 13 1047#define RT5640_MAD_L_M_NOR (0x0 << 13) 1048#define RT5640_MAD_L_M_ASYN (0x1 << 13) 1049#define RT5640_MAD_R_M_MASK (0x1 << 12) 1050#define RT5640_MAD_R_M_SFT 12 1051#define RT5640_MAD_R_M_NOR (0x0 << 12) 1052#define RT5640_MAD_R_M_ASYN (0x1 << 12) 1053#define RT5640_ADC_M_MASK (0x1 << 11) 1054#define RT5640_ADC_M_SFT 11 1055#define RT5640_ADC_M_NOR (0x0 << 11) 1056#define RT5640_ADC_M_ASYN (0x1 << 11) 1057#define RT5640_STO_DAC_M_MASK (0x1 << 5) 1058#define RT5640_STO_DAC_M_SFT 5 1059#define RT5640_STO_DAC_M_NOR (0x0 << 5) 1060#define RT5640_STO_DAC_M_ASYN (0x1 << 5) 1061#define RT5640_I2S1_R_D_MASK (0x1 << 4) 1062#define RT5640_I2S1_R_D_SFT 4 1063#define RT5640_I2S1_R_D_DIS (0x0 << 4) 1064#define RT5640_I2S1_R_D_EN (0x1 << 4) 1065#define RT5640_I2S2_R_D_MASK (0x1 << 3) 1066#define RT5640_I2S2_R_D_SFT 3 1067#define RT5640_I2S2_R_D_DIS (0x0 << 3) 1068#define RT5640_I2S2_R_D_EN (0x1 << 3) 1069#define RT5640_PRE_SCLK_MASK (0x3) 1070#define RT5640_PRE_SCLK_SFT 0 1071#define RT5640_PRE_SCLK_512 (0x0) 1072#define RT5640_PRE_SCLK_1024 (0x1) 1073#define RT5640_PRE_SCLK_2048 (0x2) 1074 1075/* ASRC Control 3 (0x85) */ 1076#define RT5640_I2S1_RATE_MASK (0xf << 12) 1077#define RT5640_I2S1_RATE_SFT 12 1078#define RT5640_I2S2_RATE_MASK (0xf << 8) 1079#define RT5640_I2S2_RATE_SFT 8 1080 1081/* ASRC Control 4 (0x89) */ 1082#define RT5640_I2S1_PD_MASK (0x7 << 12) 1083#define RT5640_I2S1_PD_SFT 12 1084#define RT5640_I2S2_PD_MASK (0x7 << 8) 1085#define RT5640_I2S2_PD_SFT 8 1086 1087/* HPOUT Over Current Detection (0x8b) */ 1088#define RT5640_HP_OVCD_MASK (0x1 << 10) 1089#define RT5640_HP_OVCD_SFT 10 1090#define RT5640_HP_OVCD_DIS (0x0 << 10) 1091#define RT5640_HP_OVCD_EN (0x1 << 10) 1092#define RT5640_HP_OC_TH_MASK (0x3 << 8) 1093#define RT5640_HP_OC_TH_SFT 8 1094#define RT5640_HP_OC_TH_90 (0x0 << 8) 1095#define RT5640_HP_OC_TH_105 (0x1 << 8) 1096#define RT5640_HP_OC_TH_120 (0x2 << 8) 1097#define RT5640_HP_OC_TH_135 (0x3 << 8) 1098 1099/* Class D Over Current Control (0x8c) */ 1100#define RT5640_CLSD_OC_MASK (0x1 << 9) 1101#define RT5640_CLSD_OC_SFT 9 1102#define RT5640_CLSD_OC_PU (0x0 << 9) 1103#define RT5640_CLSD_OC_PD (0x1 << 9) 1104#define RT5640_AUTO_PD_MASK (0x1 << 8) 1105#define RT5640_AUTO_PD_SFT 8 1106#define RT5640_AUTO_PD_DIS (0x0 << 8) 1107#define RT5640_AUTO_PD_EN (0x1 << 8) 1108#define RT5640_CLSD_OC_TH_MASK (0x3f) 1109#define RT5640_CLSD_OC_TH_SFT 0 1110 1111/* Class D Output Control (0x8d) */ 1112#define RT5640_CLSD_RATIO_MASK (0xf << 12) 1113#define RT5640_CLSD_RATIO_SFT 12 1114#define RT5640_CLSD_OM_MASK (0x1 << 11) 1115#define RT5640_CLSD_OM_SFT 11 1116#define RT5640_CLSD_OM_MONO (0x0 << 11) 1117#define RT5640_CLSD_OM_STO (0x1 << 11) 1118#define RT5640_CLSD_SCH_MASK (0x1 << 10) 1119#define RT5640_CLSD_SCH_SFT 10 1120#define RT5640_CLSD_SCH_L (0x0 << 10) 1121#define RT5640_CLSD_SCH_S (0x1 << 10) 1122 1123/* Depop Mode Control 1 (0x8e) */ 1124#define RT5640_SMT_TRIG_MASK (0x1 << 15) 1125#define RT5640_SMT_TRIG_SFT 15 1126#define RT5640_SMT_TRIG_DIS (0x0 << 15) 1127#define RT5640_SMT_TRIG_EN (0x1 << 15) 1128#define RT5640_HP_L_SMT_MASK (0x1 << 9) 1129#define RT5640_HP_L_SMT_SFT 9 1130#define RT5640_HP_L_SMT_DIS (0x0 << 9) 1131#define RT5640_HP_L_SMT_EN (0x1 << 9) 1132#define RT5640_HP_R_SMT_MASK (0x1 << 8) 1133#define RT5640_HP_R_SMT_SFT 8 1134#define RT5640_HP_R_SMT_DIS (0x0 << 8) 1135#define RT5640_HP_R_SMT_EN (0x1 << 8) 1136#define RT5640_HP_CD_PD_MASK (0x1 << 7) 1137#define RT5640_HP_CD_PD_SFT 7 1138#define RT5640_HP_CD_PD_DIS (0x0 << 7) 1139#define RT5640_HP_CD_PD_EN (0x1 << 7) 1140#define RT5640_RSTN_MASK (0x1 << 6) 1141#define RT5640_RSTN_SFT 6 1142#define RT5640_RSTN_DIS (0x0 << 6) 1143#define RT5640_RSTN_EN (0x1 << 6) 1144#define RT5640_RSTP_MASK (0x1 << 5) 1145#define RT5640_RSTP_SFT 5 1146#define RT5640_RSTP_DIS (0x0 << 5) 1147#define RT5640_RSTP_EN (0x1 << 5) 1148#define RT5640_HP_CO_MASK (0x1 << 4) 1149#define RT5640_HP_CO_SFT 4 1150#define RT5640_HP_CO_DIS (0x0 << 4) 1151#define RT5640_HP_CO_EN (0x1 << 4) 1152#define RT5640_HP_CP_MASK (0x1 << 3) 1153#define RT5640_HP_CP_SFT 3 1154#define RT5640_HP_CP_PD (0x0 << 3) 1155#define RT5640_HP_CP_PU (0x1 << 3) 1156#define RT5640_HP_SG_MASK (0x1 << 2) 1157#define RT5640_HP_SG_SFT 2 1158#define RT5640_HP_SG_DIS (0x0 << 2) 1159#define RT5640_HP_SG_EN (0x1 << 2) 1160#define RT5640_HP_DP_MASK (0x1 << 1) 1161#define RT5640_HP_DP_SFT 1 1162#define RT5640_HP_DP_PD (0x0 << 1) 1163#define RT5640_HP_DP_PU (0x1 << 1) 1164#define RT5640_HP_CB_MASK (0x1) 1165#define RT5640_HP_CB_SFT 0 1166#define RT5640_HP_CB_PD (0x0) 1167#define RT5640_HP_CB_PU (0x1) 1168 1169/* Depop Mode Control 2 (0x8f) */ 1170#define RT5640_DEPOP_MASK (0x1 << 13) 1171#define RT5640_DEPOP_SFT 13 1172#define RT5640_DEPOP_AUTO (0x0 << 13) 1173#define RT5640_DEPOP_MAN (0x1 << 13) 1174#define RT5640_RAMP_MASK (0x1 << 12) 1175#define RT5640_RAMP_SFT 12 1176#define RT5640_RAMP_DIS (0x0 << 12) 1177#define RT5640_RAMP_EN (0x1 << 12) 1178#define RT5640_BPS_MASK (0x1 << 11) 1179#define RT5640_BPS_SFT 11 1180#define RT5640_BPS_DIS (0x0 << 11) 1181#define RT5640_BPS_EN (0x1 << 11) 1182#define RT5640_FAST_UPDN_MASK (0x1 << 10) 1183#define RT5640_FAST_UPDN_SFT 10 1184#define RT5640_FAST_UPDN_DIS (0x0 << 10) 1185#define RT5640_FAST_UPDN_EN (0x1 << 10) 1186#define RT5640_MRES_MASK (0x3 << 8) 1187#define RT5640_MRES_SFT 8 1188#define RT5640_MRES_15MO (0x0 << 8) 1189#define RT5640_MRES_25MO (0x1 << 8) 1190#define RT5640_MRES_35MO (0x2 << 8) 1191#define RT5640_MRES_45MO (0x3 << 8) 1192#define RT5640_VLO_MASK (0x1 << 7) 1193#define RT5640_VLO_SFT 7 1194#define RT5640_VLO_3V (0x0 << 7) 1195#define RT5640_VLO_32V (0x1 << 7) 1196#define RT5640_DIG_DP_MASK (0x1 << 6) 1197#define RT5640_DIG_DP_SFT 6 1198#define RT5640_DIG_DP_DIS (0x0 << 6) 1199#define RT5640_DIG_DP_EN (0x1 << 6) 1200#define RT5640_DP_TH_MASK (0x3 << 4) 1201#define RT5640_DP_TH_SFT 4 1202 1203/* Depop Mode Control 3 (0x90) */ 1204#define RT5640_CP_SYS_MASK (0x7 << 12) 1205#define RT5640_CP_SYS_SFT 12 1206#define RT5640_CP_FQ1_MASK (0x7 << 8) 1207#define RT5640_CP_FQ1_SFT 8 1208#define RT5640_CP_FQ2_MASK (0x7 << 4) 1209#define RT5640_CP_FQ2_SFT 4 1210#define RT5640_CP_FQ3_MASK (0x7) 1211#define RT5640_CP_FQ3_SFT 0 1212#define RT5640_CP_FQ_1_5_KHZ 0 1213#define RT5640_CP_FQ_3_KHZ 1 1214#define RT5640_CP_FQ_6_KHZ 2 1215#define RT5640_CP_FQ_12_KHZ 3 1216#define RT5640_CP_FQ_24_KHZ 4 1217#define RT5640_CP_FQ_48_KHZ 5 1218#define RT5640_CP_FQ_96_KHZ 6 1219#define RT5640_CP_FQ_192_KHZ 7 1220 1221/* HPOUT charge pump (0x91) */ 1222#define RT5640_OSW_L_MASK (0x1 << 11) 1223#define RT5640_OSW_L_SFT 11 1224#define RT5640_OSW_L_DIS (0x0 << 11) 1225#define RT5640_OSW_L_EN (0x1 << 11) 1226#define RT5640_OSW_R_MASK (0x1 << 10) 1227#define RT5640_OSW_R_SFT 10 1228#define RT5640_OSW_R_DIS (0x0 << 10) 1229#define RT5640_OSW_R_EN (0x1 << 10) 1230#define RT5640_PM_HP_MASK (0x3 << 8) 1231#define RT5640_PM_HP_SFT 8 1232#define RT5640_PM_HP_LV (0x0 << 8) 1233#define RT5640_PM_HP_MV (0x1 << 8) 1234#define RT5640_PM_HP_HV (0x2 << 8) 1235#define RT5640_IB_HP_MASK (0x3 << 6) 1236#define RT5640_IB_HP_SFT 6 1237#define RT5640_IB_HP_125IL (0x0 << 6) 1238#define RT5640_IB_HP_25IL (0x1 << 6) 1239#define RT5640_IB_HP_5IL (0x2 << 6) 1240#define RT5640_IB_HP_1IL (0x3 << 6) 1241 1242/* PV detection and SPK gain control (0x92) */ 1243#define RT5640_PVDD_DET_MASK (0x1 << 15) 1244#define RT5640_PVDD_DET_SFT 15 1245#define RT5640_PVDD_DET_DIS (0x0 << 15) 1246#define RT5640_PVDD_DET_EN (0x1 << 15) 1247#define RT5640_SPK_AG_MASK (0x1 << 14) 1248#define RT5640_SPK_AG_SFT 14 1249#define RT5640_SPK_AG_DIS (0x0 << 14) 1250#define RT5640_SPK_AG_EN (0x1 << 14) 1251 1252/* Micbias Control (0x93) */ 1253#define RT5640_MIC1_BS_MASK (0x1 << 15) 1254#define RT5640_MIC1_BS_SFT 15 1255#define RT5640_MIC1_BS_9AV (0x0 << 15) 1256#define RT5640_MIC1_BS_75AV (0x1 << 15) 1257#define RT5640_MIC2_BS_MASK (0x1 << 14) 1258#define RT5640_MIC2_BS_SFT 14 1259#define RT5640_MIC2_BS_9AV (0x0 << 14) 1260#define RT5640_MIC2_BS_75AV (0x1 << 14) 1261#define RT5640_MIC1_CLK_MASK (0x1 << 13) 1262#define RT5640_MIC1_CLK_SFT 13 1263#define RT5640_MIC1_CLK_DIS (0x0 << 13) 1264#define RT5640_MIC1_CLK_EN (0x1 << 13) 1265#define RT5640_MIC2_CLK_MASK (0x1 << 12) 1266#define RT5640_MIC2_CLK_SFT 12 1267#define RT5640_MIC2_CLK_DIS (0x0 << 12) 1268#define RT5640_MIC2_CLK_EN (0x1 << 12) 1269#define RT5640_MIC1_OVCD_MASK (0x1 << 11) 1270#define RT5640_MIC1_OVCD_SFT 11 1271#define RT5640_MIC1_OVCD_DIS (0x0 << 11) 1272#define RT5640_MIC1_OVCD_EN (0x1 << 11) 1273#define RT5640_MIC1_OVTH_MASK (0x3 << 9) 1274#define RT5640_MIC1_OVTH_SFT 9 1275#define RT5640_MIC1_OVTH_600UA (0x0 << 9) 1276#define RT5640_MIC1_OVTH_1500UA (0x1 << 9) 1277#define RT5640_MIC1_OVTH_2000UA (0x2 << 9) 1278#define RT5640_MIC2_OVCD_MASK (0x1 << 8) 1279#define RT5640_MIC2_OVCD_SFT 8 1280#define RT5640_MIC2_OVCD_DIS (0x0 << 8) 1281#define RT5640_MIC2_OVCD_EN (0x1 << 8) 1282#define RT5640_MIC2_OVTH_MASK (0x3 << 6) 1283#define RT5640_MIC2_OVTH_SFT 6 1284#define RT5640_MIC2_OVTH_600UA (0x0 << 6) 1285#define RT5640_MIC2_OVTH_1500UA (0x1 << 6) 1286#define RT5640_MIC2_OVTH_2000UA (0x2 << 6) 1287#define RT5640_PWR_MB_MASK (0x1 << 5) 1288#define RT5640_PWR_MB_SFT 5 1289#define RT5640_PWR_MB_PD (0x0 << 5) 1290#define RT5640_PWR_MB_PU (0x1 << 5) 1291#define RT5640_PWR_CLK25M_MASK (0x1 << 4) 1292#define RT5640_PWR_CLK25M_SFT 4 1293#define RT5640_PWR_CLK25M_PD (0x0 << 4) 1294#define RT5640_PWR_CLK25M_PU (0x1 << 4) 1295 1296/* EQ Control 1 (0xb0) */ 1297#define RT5640_EQ_SRC_MASK (0x1 << 15) 1298#define RT5640_EQ_SRC_SFT 15 1299#define RT5640_EQ_SRC_DAC (0x0 << 15) 1300#define RT5640_EQ_SRC_ADC (0x1 << 15) 1301#define RT5640_EQ_UPD (0x1 << 14) 1302#define RT5640_EQ_UPD_BIT 14 1303#define RT5640_EQ_CD_MASK (0x1 << 13) 1304#define RT5640_EQ_CD_SFT 13 1305#define RT5640_EQ_CD_DIS (0x0 << 13) 1306#define RT5640_EQ_CD_EN (0x1 << 13) 1307#define RT5640_EQ_DITH_MASK (0x3 << 8) 1308#define RT5640_EQ_DITH_SFT 8 1309#define RT5640_EQ_DITH_NOR (0x0 << 8) 1310#define RT5640_EQ_DITH_LSB (0x1 << 8) 1311#define RT5640_EQ_DITH_LSB_1 (0x2 << 8) 1312#define RT5640_EQ_DITH_LSB_2 (0x3 << 8) 1313 1314/* EQ Control 2 (0xb1) */ 1315#define RT5640_EQ_HPF1_M_MASK (0x1 << 8) 1316#define RT5640_EQ_HPF1_M_SFT 8 1317#define RT5640_EQ_HPF1_M_HI (0x0 << 8) 1318#define RT5640_EQ_HPF1_M_1ST (0x1 << 8) 1319#define RT5640_EQ_LPF1_M_MASK (0x1 << 7) 1320#define RT5640_EQ_LPF1_M_SFT 7 1321#define RT5640_EQ_LPF1_M_LO (0x0 << 7) 1322#define RT5640_EQ_LPF1_M_1ST (0x1 << 7) 1323#define RT5640_EQ_HPF2_MASK (0x1 << 6) 1324#define RT5640_EQ_HPF2_SFT 6 1325#define RT5640_EQ_HPF2_DIS (0x0 << 6) 1326#define RT5640_EQ_HPF2_EN (0x1 << 6) 1327#define RT5640_EQ_HPF1_MASK (0x1 << 5) 1328#define RT5640_EQ_HPF1_SFT 5 1329#define RT5640_EQ_HPF1_DIS (0x0 << 5) 1330#define RT5640_EQ_HPF1_EN (0x1 << 5) 1331#define RT5640_EQ_BPF4_MASK (0x1 << 4) 1332#define RT5640_EQ_BPF4_SFT 4 1333#define RT5640_EQ_BPF4_DIS (0x0 << 4) 1334#define RT5640_EQ_BPF4_EN (0x1 << 4) 1335#define RT5640_EQ_BPF3_MASK (0x1 << 3) 1336#define RT5640_EQ_BPF3_SFT 3 1337#define RT5640_EQ_BPF3_DIS (0x0 << 3) 1338#define RT5640_EQ_BPF3_EN (0x1 << 3) 1339#define RT5640_EQ_BPF2_MASK (0x1 << 2) 1340#define RT5640_EQ_BPF2_SFT 2 1341#define RT5640_EQ_BPF2_DIS (0x0 << 2) 1342#define RT5640_EQ_BPF2_EN (0x1 << 2) 1343#define RT5640_EQ_BPF1_MASK (0x1 << 1) 1344#define RT5640_EQ_BPF1_SFT 1 1345#define RT5640_EQ_BPF1_DIS (0x0 << 1) 1346#define RT5640_EQ_BPF1_EN (0x1 << 1) 1347#define RT5640_EQ_LPF_MASK (0x1) 1348#define RT5640_EQ_LPF_SFT 0 1349#define RT5640_EQ_LPF_DIS (0x0) 1350#define RT5640_EQ_LPF_EN (0x1) 1351 1352/* Memory Test (0xb2) */ 1353#define RT5640_MT_MASK (0x1 << 15) 1354#define RT5640_MT_SFT 15 1355#define RT5640_MT_DIS (0x0 << 15) 1356#define RT5640_MT_EN (0x1 << 15) 1357 1358/* DRC/AGC Control 1 (0xb4) */ 1359#define RT5640_DRC_AGC_P_MASK (0x1 << 15) 1360#define RT5640_DRC_AGC_P_SFT 15 1361#define RT5640_DRC_AGC_P_DAC (0x0 << 15) 1362#define RT5640_DRC_AGC_P_ADC (0x1 << 15) 1363#define RT5640_DRC_AGC_MASK (0x1 << 14) 1364#define RT5640_DRC_AGC_SFT 14 1365#define RT5640_DRC_AGC_DIS (0x0 << 14) 1366#define RT5640_DRC_AGC_EN (0x1 << 14) 1367#define RT5640_DRC_AGC_UPD (0x1 << 13) 1368#define RT5640_DRC_AGC_UPD_BIT 13 1369#define RT5640_DRC_AGC_AR_MASK (0x1f << 8) 1370#define RT5640_DRC_AGC_AR_SFT 8 1371#define RT5640_DRC_AGC_R_MASK (0x7 << 5) 1372#define RT5640_DRC_AGC_R_SFT 5 1373#define RT5640_DRC_AGC_R_48K (0x1 << 5) 1374#define RT5640_DRC_AGC_R_96K (0x2 << 5) 1375#define RT5640_DRC_AGC_R_192K (0x3 << 5) 1376#define RT5640_DRC_AGC_R_441K (0x5 << 5) 1377#define RT5640_DRC_AGC_R_882K (0x6 << 5) 1378#define RT5640_DRC_AGC_R_1764K (0x7 << 5) 1379#define RT5640_DRC_AGC_RC_MASK (0x1f) 1380#define RT5640_DRC_AGC_RC_SFT 0 1381 1382/* DRC/AGC Control 2 (0xb5) */ 1383#define RT5640_DRC_AGC_POB_MASK (0x3f << 8) 1384#define RT5640_DRC_AGC_POB_SFT 8 1385#define RT5640_DRC_AGC_CP_MASK (0x1 << 7) 1386#define RT5640_DRC_AGC_CP_SFT 7 1387#define RT5640_DRC_AGC_CP_DIS (0x0 << 7) 1388#define RT5640_DRC_AGC_CP_EN (0x1 << 7) 1389#define RT5640_DRC_AGC_CPR_MASK (0x3 << 5) 1390#define RT5640_DRC_AGC_CPR_SFT 5 1391#define RT5640_DRC_AGC_CPR_1_1 (0x0 << 5) 1392#define RT5640_DRC_AGC_CPR_1_2 (0x1 << 5) 1393#define RT5640_DRC_AGC_CPR_1_3 (0x2 << 5) 1394#define RT5640_DRC_AGC_CPR_1_4 (0x3 << 5) 1395#define RT5640_DRC_AGC_PRB_MASK (0x1f) 1396#define RT5640_DRC_AGC_PRB_SFT 0 1397 1398/* DRC/AGC Control 3 (0xb6) */ 1399#define RT5640_DRC_AGC_NGB_MASK (0xf << 12) 1400#define RT5640_DRC_AGC_NGB_SFT 12 1401#define RT5640_DRC_AGC_TAR_MASK (0x1f << 7) 1402#define RT5640_DRC_AGC_TAR_SFT 7 1403#define RT5640_DRC_AGC_NG_MASK (0x1 << 6) 1404#define RT5640_DRC_AGC_NG_SFT 6 1405#define RT5640_DRC_AGC_NG_DIS (0x0 << 6) 1406#define RT5640_DRC_AGC_NG_EN (0x1 << 6) 1407#define RT5640_DRC_AGC_NGH_MASK (0x1 << 5) 1408#define RT5640_DRC_AGC_NGH_SFT 5 1409#define RT5640_DRC_AGC_NGH_DIS (0x0 << 5) 1410#define RT5640_DRC_AGC_NGH_EN (0x1 << 5) 1411#define RT5640_DRC_AGC_NGT_MASK (0x1f) 1412#define RT5640_DRC_AGC_NGT_SFT 0 1413 1414/* ANC Control 1 (0xb8) */ 1415#define RT5640_ANC_M_MASK (0x1 << 15) 1416#define RT5640_ANC_M_SFT 15 1417#define RT5640_ANC_M_NOR (0x0 << 15) 1418#define RT5640_ANC_M_REV (0x1 << 15) 1419#define RT5640_ANC_MASK (0x1 << 14) 1420#define RT5640_ANC_SFT 14 1421#define RT5640_ANC_DIS (0x0 << 14) 1422#define RT5640_ANC_EN (0x1 << 14) 1423#define RT5640_ANC_MD_MASK (0x3 << 12) 1424#define RT5640_ANC_MD_SFT 12 1425#define RT5640_ANC_MD_DIS (0x0 << 12) 1426#define RT5640_ANC_MD_67MS (0x1 << 12) 1427#define RT5640_ANC_MD_267MS (0x2 << 12) 1428#define RT5640_ANC_MD_1067MS (0x3 << 12) 1429#define RT5640_ANC_SN_MASK (0x1 << 11) 1430#define RT5640_ANC_SN_SFT 11 1431#define RT5640_ANC_SN_DIS (0x0 << 11) 1432#define RT5640_ANC_SN_EN (0x1 << 11) 1433#define RT5640_ANC_CLK_MASK (0x1 << 10) 1434#define RT5640_ANC_CLK_SFT 10 1435#define RT5640_ANC_CLK_ANC (0x0 << 10) 1436#define RT5640_ANC_CLK_REG (0x1 << 10) 1437#define RT5640_ANC_ZCD_MASK (0x3 << 8) 1438#define RT5640_ANC_ZCD_SFT 8 1439#define RT5640_ANC_ZCD_DIS (0x0 << 8) 1440#define RT5640_ANC_ZCD_T1 (0x1 << 8) 1441#define RT5640_ANC_ZCD_T2 (0x2 << 8) 1442#define RT5640_ANC_ZCD_WT (0x3 << 8) 1443#define RT5640_ANC_CS_MASK (0x1 << 7) 1444#define RT5640_ANC_CS_SFT 7 1445#define RT5640_ANC_CS_DIS (0x0 << 7) 1446#define RT5640_ANC_CS_EN (0x1 << 7) 1447#define RT5640_ANC_SW_MASK (0x1 << 6) 1448#define RT5640_ANC_SW_SFT 6 1449#define RT5640_ANC_SW_NOR (0x0 << 6) 1450#define RT5640_ANC_SW_AUTO (0x1 << 6) 1451#define RT5640_ANC_CO_L_MASK (0x3f) 1452#define RT5640_ANC_CO_L_SFT 0 1453 1454/* ANC Control 2 (0xb6) */ 1455#define RT5640_ANC_FG_R_MASK (0xf << 12) 1456#define RT5640_ANC_FG_R_SFT 12 1457#define RT5640_ANC_FG_L_MASK (0xf << 8) 1458#define RT5640_ANC_FG_L_SFT 8 1459#define RT5640_ANC_CG_R_MASK (0xf << 4) 1460#define RT5640_ANC_CG_R_SFT 4 1461#define RT5640_ANC_CG_L_MASK (0xf) 1462#define RT5640_ANC_CG_L_SFT 0 1463 1464/* ANC Control 3 (0xb6) */ 1465#define RT5640_ANC_CD_MASK (0x1 << 6) 1466#define RT5640_ANC_CD_SFT 6 1467#define RT5640_ANC_CD_BOTH (0x0 << 6) 1468#define RT5640_ANC_CD_IND (0x1 << 6) 1469#define RT5640_ANC_CO_R_MASK (0x3f) 1470#define RT5640_ANC_CO_R_SFT 0 1471 1472/* Jack Detect Control (0xbb) */ 1473#define RT5640_JD_MASK (0x7 << 13) 1474#define RT5640_JD_SFT 13 1475#define RT5640_JD_DIS (0x0 << 13) 1476#define RT5640_JD_GPIO1 (0x1 << 13) 1477#define RT5640_JD_JD1_IN4P (0x2 << 13) 1478#define RT5640_JD_JD2_IN4N (0x3 << 13) 1479#define RT5640_JD_GPIO2 (0x4 << 13) 1480#define RT5640_JD_GPIO3 (0x5 << 13) 1481#define RT5640_JD_GPIO4 (0x6 << 13) 1482#define RT5640_JD_HP_MASK (0x1 << 11) 1483#define RT5640_JD_HP_SFT 11 1484#define RT5640_JD_HP_DIS (0x0 << 11) 1485#define RT5640_JD_HP_EN (0x1 << 11) 1486#define RT5640_JD_HP_TRG_MASK (0x1 << 10) 1487#define RT5640_JD_HP_TRG_SFT 10 1488#define RT5640_JD_HP_TRG_LO (0x0 << 10) 1489#define RT5640_JD_HP_TRG_HI (0x1 << 10) 1490#define RT5640_JD_SPL_MASK (0x1 << 9) 1491#define RT5640_JD_SPL_SFT 9 1492#define RT5640_JD_SPL_DIS (0x0 << 9) 1493#define RT5640_JD_SPL_EN (0x1 << 9) 1494#define RT5640_JD_SPL_TRG_MASK (0x1 << 8) 1495#define RT5640_JD_SPL_TRG_SFT 8 1496#define RT5640_JD_SPL_TRG_LO (0x0 << 8) 1497#define RT5640_JD_SPL_TRG_HI (0x1 << 8) 1498#define RT5640_JD_SPR_MASK (0x1 << 7) 1499#define RT5640_JD_SPR_SFT 7 1500#define RT5640_JD_SPR_DIS (0x0 << 7) 1501#define RT5640_JD_SPR_EN (0x1 << 7) 1502#define RT5640_JD_SPR_TRG_MASK (0x1 << 6) 1503#define RT5640_JD_SPR_TRG_SFT 6 1504#define RT5640_JD_SPR_TRG_LO (0x0 << 6) 1505#define RT5640_JD_SPR_TRG_HI (0x1 << 6) 1506#define RT5640_JD_MO_MASK (0x1 << 5) 1507#define RT5640_JD_MO_SFT 5 1508#define RT5640_JD_MO_DIS (0x0 << 5) 1509#define RT5640_JD_MO_EN (0x1 << 5) 1510#define RT5640_JD_MO_TRG_MASK (0x1 << 4) 1511#define RT5640_JD_MO_TRG_SFT 4 1512#define RT5640_JD_MO_TRG_LO (0x0 << 4) 1513#define RT5640_JD_MO_TRG_HI (0x1 << 4) 1514#define RT5640_JD_LO_MASK (0x1 << 3) 1515#define RT5640_JD_LO_SFT 3 1516#define RT5640_JD_LO_DIS (0x0 << 3) 1517#define RT5640_JD_LO_EN (0x1 << 3) 1518#define RT5640_JD_LO_TRG_MASK (0x1 << 2) 1519#define RT5640_JD_LO_TRG_SFT 2 1520#define RT5640_JD_LO_TRG_LO (0x0 << 2) 1521#define RT5640_JD_LO_TRG_HI (0x1 << 2) 1522#define RT5640_JD1_IN4P_MASK (0x1 << 1) 1523#define RT5640_JD1_IN4P_SFT 1 1524#define RT5640_JD1_IN4P_DIS (0x0 << 1) 1525#define RT5640_JD1_IN4P_EN (0x1 << 1) 1526#define RT5640_JD2_IN4N_MASK (0x1) 1527#define RT5640_JD2_IN4N_SFT 0 1528#define RT5640_JD2_IN4N_DIS (0x0) 1529#define RT5640_JD2_IN4N_EN (0x1) 1530 1531/* Jack detect for ANC (0xbc) */ 1532#define RT5640_ANC_DET_MASK (0x3 << 4) 1533#define RT5640_ANC_DET_SFT 4 1534#define RT5640_ANC_DET_DIS (0x0 << 4) 1535#define RT5640_ANC_DET_MB1 (0x1 << 4) 1536#define RT5640_ANC_DET_MB2 (0x2 << 4) 1537#define RT5640_ANC_DET_JD (0x3 << 4) 1538#define RT5640_AD_TRG_MASK (0x1 << 3) 1539#define RT5640_AD_TRG_SFT 3 1540#define RT5640_AD_TRG_LO (0x0 << 3) 1541#define RT5640_AD_TRG_HI (0x1 << 3) 1542#define RT5640_ANCM_DET_MASK (0x3 << 4) 1543#define RT5640_ANCM_DET_SFT 4 1544#define RT5640_ANCM_DET_DIS (0x0 << 4) 1545#define RT5640_ANCM_DET_MB1 (0x1 << 4) 1546#define RT5640_ANCM_DET_MB2 (0x2 << 4) 1547#define RT5640_ANCM_DET_JD (0x3 << 4) 1548#define RT5640_AMD_TRG_MASK (0x1 << 3) 1549#define RT5640_AMD_TRG_SFT 3 1550#define RT5640_AMD_TRG_LO (0x0 << 3) 1551#define RT5640_AMD_TRG_HI (0x1 << 3) 1552 1553/* IRQ Control 1 (0xbd) */ 1554#define RT5640_IRQ_JD_MASK (0x1 << 15) 1555#define RT5640_IRQ_JD_SFT 15 1556#define RT5640_IRQ_JD_BP (0x0 << 15) 1557#define RT5640_IRQ_JD_NOR (0x1 << 15) 1558#define RT5640_IRQ_OT_MASK (0x1 << 14) 1559#define RT5640_IRQ_OT_SFT 14 1560#define RT5640_IRQ_OT_BP (0x0 << 14) 1561#define RT5640_IRQ_OT_NOR (0x1 << 14) 1562#define RT5640_JD_STKY_MASK (0x1 << 13) 1563#define RT5640_JD_STKY_SFT 13 1564#define RT5640_JD_STKY_DIS (0x0 << 13) 1565#define RT5640_JD_STKY_EN (0x1 << 13) 1566#define RT5640_OT_STKY_MASK (0x1 << 12) 1567#define RT5640_OT_STKY_SFT 12 1568#define RT5640_OT_STKY_DIS (0x0 << 12) 1569#define RT5640_OT_STKY_EN (0x1 << 12) 1570#define RT5640_JD_P_MASK (0x1 << 11) 1571#define RT5640_JD_P_SFT 11 1572#define RT5640_JD_P_NOR (0x0 << 11) 1573#define RT5640_JD_P_INV (0x1 << 11) 1574#define RT5640_OT_P_MASK (0x1 << 10) 1575#define RT5640_OT_P_SFT 10 1576#define RT5640_OT_P_NOR (0x0 << 10) 1577#define RT5640_OT_P_INV (0x1 << 10) 1578 1579/* IRQ Control 2 (0xbe) */ 1580#define RT5640_IRQ_MB1_OC_MASK (0x1 << 15) 1581#define RT5640_IRQ_MB1_OC_SFT 15 1582#define RT5640_IRQ_MB1_OC_BP (0x0 << 15) 1583#define RT5640_IRQ_MB1_OC_NOR (0x1 << 15) 1584#define RT5640_IRQ_MB2_OC_MASK (0x1 << 14) 1585#define RT5640_IRQ_MB2_OC_SFT 14 1586#define RT5640_IRQ_MB2_OC_BP (0x0 << 14) 1587#define RT5640_IRQ_MB2_OC_NOR (0x1 << 14) 1588#define RT5640_MB1_OC_STKY_MASK (0x1 << 11) 1589#define RT5640_MB1_OC_STKY_SFT 11 1590#define RT5640_MB1_OC_STKY_DIS (0x0 << 11) 1591#define RT5640_MB1_OC_STKY_EN (0x1 << 11) 1592#define RT5640_MB2_OC_STKY_MASK (0x1 << 10) 1593#define RT5640_MB2_OC_STKY_SFT 10 1594#define RT5640_MB2_OC_STKY_DIS (0x0 << 10) 1595#define RT5640_MB2_OC_STKY_EN (0x1 << 10) 1596#define RT5640_MB1_OC_P_MASK (0x1 << 7) 1597#define RT5640_MB1_OC_P_SFT 7 1598#define RT5640_MB1_OC_P_NOR (0x0 << 7) 1599#define RT5640_MB1_OC_P_INV (0x1 << 7) 1600#define RT5640_MB2_OC_P_MASK (0x1 << 6) 1601#define RT5640_MB2_OC_P_SFT 6 1602#define RT5640_MB2_OC_P_NOR (0x0 << 6) 1603#define RT5640_MB2_OC_P_INV (0x1 << 6) 1604#define RT5640_MB1_OC_CLR (0x1 << 3) 1605#define RT5640_MB1_OC_CLR_SFT 3 1606#define RT5640_MB2_OC_CLR (0x1 << 2) 1607#define RT5640_MB2_OC_CLR_SFT 2 1608 1609/* GPIO Control 1 (0xc0) */ 1610#define RT5640_GP1_PIN_MASK (0x1 << 15) 1611#define RT5640_GP1_PIN_SFT 15 1612#define RT5640_GP1_PIN_GPIO1 (0x0 << 15) 1613#define RT5640_GP1_PIN_IRQ (0x1 << 15) 1614#define RT5640_GP2_PIN_MASK (0x1 << 14) 1615#define RT5640_GP2_PIN_SFT 14 1616#define RT5640_GP2_PIN_GPIO2 (0x0 << 14) 1617#define RT5640_GP2_PIN_DMIC1_SCL (0x1 << 14) 1618#define RT5640_GP3_PIN_MASK (0x3 << 12) 1619#define RT5640_GP3_PIN_SFT 12 1620#define RT5640_GP3_PIN_GPIO3 (0x0 << 12) 1621#define RT5640_GP3_PIN_DMIC1_SDA (0x1 << 12) 1622#define RT5640_GP3_PIN_IRQ (0x2 << 12) 1623#define RT5640_GP4_PIN_MASK (0x1 << 11) 1624#define RT5640_GP4_PIN_SFT 11 1625#define RT5640_GP4_PIN_GPIO4 (0x0 << 11) 1626#define RT5640_GP4_PIN_DMIC2_SDA (0x1 << 11) 1627#define RT5640_DP_SIG_MASK (0x1 << 10) 1628#define RT5640_DP_SIG_SFT 10 1629#define RT5640_DP_SIG_TEST (0x0 << 10) 1630#define RT5640_DP_SIG_AP (0x1 << 10) 1631#define RT5640_GPIO_M_MASK (0x1 << 9) 1632#define RT5640_GPIO_M_SFT 9 1633#define RT5640_GPIO_M_FLT (0x0 << 9) 1634#define RT5640_GPIO_M_PH (0x1 << 9) 1635 1636/* GPIO Control 3 (0xc2) */ 1637#define RT5640_GP4_PF_MASK (0x1 << 11) 1638#define RT5640_GP4_PF_SFT 11 1639#define RT5640_GP4_PF_IN (0x0 << 11) 1640#define RT5640_GP4_PF_OUT (0x1 << 11) 1641#define RT5640_GP4_OUT_MASK (0x1 << 10) 1642#define RT5640_GP4_OUT_SFT 10 1643#define RT5640_GP4_OUT_LO (0x0 << 10) 1644#define RT5640_GP4_OUT_HI (0x1 << 10) 1645#define RT5640_GP4_P_MASK (0x1 << 9) 1646#define RT5640_GP4_P_SFT 9 1647#define RT5640_GP4_P_NOR (0x0 << 9) 1648#define RT5640_GP4_P_INV (0x1 << 9) 1649#define RT5640_GP3_PF_MASK (0x1 << 8) 1650#define RT5640_GP3_PF_SFT 8 1651#define RT5640_GP3_PF_IN (0x0 << 8) 1652#define RT5640_GP3_PF_OUT (0x1 << 8) 1653#define RT5640_GP3_OUT_MASK (0x1 << 7) 1654#define RT5640_GP3_OUT_SFT 7 1655#define RT5640_GP3_OUT_LO (0x0 << 7) 1656#define RT5640_GP3_OUT_HI (0x1 << 7) 1657#define RT5640_GP3_P_MASK (0x1 << 6) 1658#define RT5640_GP3_P_SFT 6 1659#define RT5640_GP3_P_NOR (0x0 << 6) 1660#define RT5640_GP3_P_INV (0x1 << 6) 1661#define RT5640_GP2_PF_MASK (0x1 << 5) 1662#define RT5640_GP2_PF_SFT 5 1663#define RT5640_GP2_PF_IN (0x0 << 5) 1664#define RT5640_GP2_PF_OUT (0x1 << 5) 1665#define RT5640_GP2_OUT_MASK (0x1 << 4) 1666#define RT5640_GP2_OUT_SFT 4 1667#define RT5640_GP2_OUT_LO (0x0 << 4) 1668#define RT5640_GP2_OUT_HI (0x1 << 4) 1669#define RT5640_GP2_P_MASK (0x1 << 3) 1670#define RT5640_GP2_P_SFT 3 1671#define RT5640_GP2_P_NOR (0x0 << 3) 1672#define RT5640_GP2_P_INV (0x1 << 3) 1673#define RT5640_GP1_PF_MASK (0x1 << 2) 1674#define RT5640_GP1_PF_SFT 2 1675#define RT5640_GP1_PF_IN (0x0 << 2) 1676#define RT5640_GP1_PF_OUT (0x1 << 2) 1677#define RT5640_GP1_OUT_MASK (0x1 << 1) 1678#define RT5640_GP1_OUT_SFT 1 1679#define RT5640_GP1_OUT_LO (0x0 << 1) 1680#define RT5640_GP1_OUT_HI (0x1 << 1) 1681#define RT5640_GP1_P_MASK (0x1) 1682#define RT5640_GP1_P_SFT 0 1683#define RT5640_GP1_P_NOR (0x0) 1684#define RT5640_GP1_P_INV (0x1) 1685 1686/* FM34-500 Register Control 1 (0xc4) */ 1687#define RT5640_DSP_ADD_SFT 0 1688 1689/* FM34-500 Register Control 2 (0xc5) */ 1690#define RT5640_DSP_DAT_SFT 0 1691 1692/* FM34-500 Register Control 3 (0xc6) */ 1693#define RT5640_DSP_BUSY_MASK (0x1 << 15) 1694#define RT5640_DSP_BUSY_BIT 15 1695#define RT5640_DSP_DS_MASK (0x1 << 14) 1696#define RT5640_DSP_DS_SFT 14 1697#define RT5640_DSP_DS_FM3010 (0x1 << 14) 1698#define RT5640_DSP_DS_TEMP (0x1 << 14) 1699#define RT5640_DSP_CLK_MASK (0x3 << 12) 1700#define RT5640_DSP_CLK_SFT 12 1701#define RT5640_DSP_CLK_384K (0x0 << 12) 1702#define RT5640_DSP_CLK_192K (0x1 << 12) 1703#define RT5640_DSP_CLK_96K (0x2 << 12) 1704#define RT5640_DSP_CLK_64K (0x3 << 12) 1705#define RT5640_DSP_PD_PIN_MASK (0x1 << 11) 1706#define RT5640_DSP_PD_PIN_SFT 11 1707#define RT5640_DSP_PD_PIN_LO (0x0 << 11) 1708#define RT5640_DSP_PD_PIN_HI (0x1 << 11) 1709#define RT5640_DSP_RST_PIN_MASK (0x1 << 10) 1710#define RT5640_DSP_RST_PIN_SFT 10 1711#define RT5640_DSP_RST_PIN_LO (0x0 << 10) 1712#define RT5640_DSP_RST_PIN_HI (0x1 << 10) 1713#define RT5640_DSP_R_EN (0x1 << 9) 1714#define RT5640_DSP_R_EN_BIT 9 1715#define RT5640_DSP_W_EN (0x1 << 8) 1716#define RT5640_DSP_W_EN_BIT 8 1717#define RT5640_DSP_CMD_MASK (0xff) 1718#define RT5640_DSP_CMD_SFT 0 1719#define RT5640_DSP_CMD_MW (0x3B) /* Memory Write */ 1720#define RT5640_DSP_CMD_MR (0x37) /* Memory Read */ 1721#define RT5640_DSP_CMD_RR (0x60) /* Register Read */ 1722#define RT5640_DSP_CMD_RW (0x68) /* Register Write */ 1723 1724/* Programmable Register Array Control 1 (0xc8) */ 1725#define RT5640_REG_SEQ_MASK (0xf << 12) 1726#define RT5640_REG_SEQ_SFT 12 1727#define RT5640_SEQ1_ST_MASK (0x1 << 11) /*RO*/ 1728#define RT5640_SEQ1_ST_SFT 11 1729#define RT5640_SEQ1_ST_RUN (0x0 << 11) 1730#define RT5640_SEQ1_ST_FIN (0x1 << 11) 1731#define RT5640_SEQ2_ST_MASK (0x1 << 10) /*RO*/ 1732#define RT5640_SEQ2_ST_SFT 10 1733#define RT5640_SEQ2_ST_RUN (0x0 << 10) 1734#define RT5640_SEQ2_ST_FIN (0x1 << 10) 1735#define RT5640_REG_LV_MASK (0x1 << 9) 1736#define RT5640_REG_LV_SFT 9 1737#define RT5640_REG_LV_MX (0x0 << 9) 1738#define RT5640_REG_LV_PR (0x1 << 9) 1739#define RT5640_SEQ_2_PT_MASK (0x1 << 8) 1740#define RT5640_SEQ_2_PT_BIT 8 1741#define RT5640_REG_IDX_MASK (0xff) 1742#define RT5640_REG_IDX_SFT 0 1743 1744/* Programmable Register Array Control 2 (0xc9) */ 1745#define RT5640_REG_DAT_MASK (0xffff) 1746#define RT5640_REG_DAT_SFT 0 1747 1748/* Programmable Register Array Control 3 (0xca) */ 1749#define RT5640_SEQ_DLY_MASK (0xff << 8) 1750#define RT5640_SEQ_DLY_SFT 8 1751#define RT5640_PROG_MASK (0x1 << 7) 1752#define RT5640_PROG_SFT 7 1753#define RT5640_PROG_DIS (0x0 << 7) 1754#define RT5640_PROG_EN (0x1 << 7) 1755#define RT5640_SEQ1_PT_RUN (0x1 << 6) 1756#define RT5640_SEQ1_PT_RUN_BIT 6 1757#define RT5640_SEQ2_PT_RUN (0x1 << 5) 1758#define RT5640_SEQ2_PT_RUN_BIT 5 1759 1760/* Programmable Register Array Control 4 (0xcb) */ 1761#define RT5640_SEQ1_START_MASK (0xf << 8) 1762#define RT5640_SEQ1_START_SFT 8 1763#define RT5640_SEQ1_END_MASK (0xf) 1764#define RT5640_SEQ1_END_SFT 0 1765 1766/* Programmable Register Array Control 5 (0xcc) */ 1767#define RT5640_SEQ2_START_MASK (0xf << 8) 1768#define RT5640_SEQ2_START_SFT 8 1769#define RT5640_SEQ2_END_MASK (0xf) 1770#define RT5640_SEQ2_END_SFT 0 1771 1772/* Scramble Function (0xcd) */ 1773#define RT5640_SCB_KEY_MASK (0xff) 1774#define RT5640_SCB_KEY_SFT 0 1775 1776/* Scramble Control (0xce) */ 1777#define RT5640_SCB_SWAP_MASK (0x1 << 15) 1778#define RT5640_SCB_SWAP_SFT 15 1779#define RT5640_SCB_SWAP_DIS (0x0 << 15) 1780#define RT5640_SCB_SWAP_EN (0x1 << 15) 1781#define RT5640_SCB_MASK (0x1 << 14) 1782#define RT5640_SCB_SFT 14 1783#define RT5640_SCB_DIS (0x0 << 14) 1784#define RT5640_SCB_EN (0x1 << 14) 1785 1786/* Baseback Control (0xcf) */ 1787#define RT5640_BB_MASK (0x1 << 15) 1788#define RT5640_BB_SFT 15 1789#define RT5640_BB_DIS (0x0 << 15) 1790#define RT5640_BB_EN (0x1 << 15) 1791#define RT5640_BB_CT_MASK (0x7 << 12) 1792#define RT5640_BB_CT_SFT 12 1793#define RT5640_BB_CT_A (0x0 << 12) 1794#define RT5640_BB_CT_B (0x1 << 12) 1795#define RT5640_BB_CT_C (0x2 << 12) 1796#define RT5640_BB_CT_D (0x3 << 12) 1797#define RT5640_M_BB_L_MASK (0x1 << 9) 1798#define RT5640_M_BB_L_SFT 9 1799#define RT5640_M_BB_R_MASK (0x1 << 8) 1800#define RT5640_M_BB_R_SFT 8 1801#define RT5640_M_BB_HPF_L_MASK (0x1 << 7) 1802#define RT5640_M_BB_HPF_L_SFT 7 1803#define RT5640_M_BB_HPF_R_MASK (0x1 << 6) 1804#define RT5640_M_BB_HPF_R_SFT 6 1805#define RT5640_G_BB_BST_MASK (0x3f) 1806#define RT5640_G_BB_BST_SFT 0 1807 1808/* MP3 Plus Control 1 (0xd0) */ 1809#define RT5640_M_MP3_L_MASK (0x1 << 15) 1810#define RT5640_M_MP3_L_SFT 15 1811#define RT5640_M_MP3_R_MASK (0x1 << 14) 1812#define RT5640_M_MP3_R_SFT 14 1813#define RT5640_M_MP3_MASK (0x1 << 13) 1814#define RT5640_M_MP3_SFT 13 1815#define RT5640_M_MP3_DIS (0x0 << 13) 1816#define RT5640_M_MP3_EN (0x1 << 13) 1817#define RT5640_EG_MP3_MASK (0x1f << 8) 1818#define RT5640_EG_MP3_SFT 8 1819#define RT5640_MP3_HLP_MASK (0x1 << 7) 1820#define RT5640_MP3_HLP_SFT 7 1821#define RT5640_MP3_HLP_DIS (0x0 << 7) 1822#define RT5640_MP3_HLP_EN (0x1 << 7) 1823#define RT5640_M_MP3_ORG_L_MASK (0x1 << 6) 1824#define RT5640_M_MP3_ORG_L_SFT 6 1825#define RT5640_M_MP3_ORG_R_MASK (0x1 << 5) 1826#define RT5640_M_MP3_ORG_R_SFT 5 1827 1828/* MP3 Plus Control 2 (0xd1) */ 1829#define RT5640_MP3_WT_MASK (0x1 << 13) 1830#define RT5640_MP3_WT_SFT 13 1831#define RT5640_MP3_WT_1_4 (0x0 << 13) 1832#define RT5640_MP3_WT_1_2 (0x1 << 13) 1833#define RT5640_OG_MP3_MASK (0x1f << 8) 1834#define RT5640_OG_MP3_SFT 8 1835#define RT5640_HG_MP3_MASK (0x3f) 1836#define RT5640_HG_MP3_SFT 0 1837 1838/* 3D HP Control 1 (0xd2) */ 1839#define RT5640_3D_CF_MASK (0x1 << 15) 1840#define RT5640_3D_CF_SFT 15 1841#define RT5640_3D_CF_DIS (0x0 << 15) 1842#define RT5640_3D_CF_EN (0x1 << 15) 1843#define RT5640_3D_HP_MASK (0x1 << 14) 1844#define RT5640_3D_HP_SFT 14 1845#define RT5640_3D_HP_DIS (0x0 << 14) 1846#define RT5640_3D_HP_EN (0x1 << 14) 1847#define RT5640_3D_BT_MASK (0x1 << 13) 1848#define RT5640_3D_BT_SFT 13 1849#define RT5640_3D_BT_DIS (0x0 << 13) 1850#define RT5640_3D_BT_EN (0x1 << 13) 1851#define RT5640_3D_1F_MIX_MASK (0x3 << 11) 1852#define RT5640_3D_1F_MIX_SFT 11 1853#define RT5640_3D_HP_M_MASK (0x1 << 10) 1854#define RT5640_3D_HP_M_SFT 10 1855#define RT5640_3D_HP_M_SUR (0x0 << 10) 1856#define RT5640_3D_HP_M_FRO (0x1 << 10) 1857#define RT5640_M_3D_HRTF_MASK (0x1 << 9) 1858#define RT5640_M_3D_HRTF_SFT 9 1859#define RT5640_M_3D_D2H_MASK (0x1 << 8) 1860#define RT5640_M_3D_D2H_SFT 8 1861#define RT5640_M_3D_D2R_MASK (0x1 << 7) 1862#define RT5640_M_3D_D2R_SFT 7 1863#define RT5640_M_3D_REVB_MASK (0x1 << 6) 1864#define RT5640_M_3D_REVB_SFT 6 1865 1866/* Adjustable high pass filter control 1 (0xd3) */ 1867#define RT5640_2ND_HPF_MASK (0x1 << 15) 1868#define RT5640_2ND_HPF_SFT 15 1869#define RT5640_2ND_HPF_DIS (0x0 << 15) 1870#define RT5640_2ND_HPF_EN (0x1 << 15) 1871#define RT5640_HPF_CF_L_MASK (0x7 << 12) 1872#define RT5640_HPF_CF_L_SFT 12 1873#define RT5640_1ST_HPF_MASK (0x1 << 11) 1874#define RT5640_1ST_HPF_SFT 11 1875#define RT5640_1ST_HPF_DIS (0x0 << 11) 1876#define RT5640_1ST_HPF_EN (0x1 << 11) 1877#define RT5640_HPF_CF_R_MASK (0x7 << 8) 1878#define RT5640_HPF_CF_R_SFT 8 1879#define RT5640_ZD_T_MASK (0x3 << 6) 1880#define RT5640_ZD_T_SFT 6 1881#define RT5640_ZD_F_MASK (0x3 << 4) 1882#define RT5640_ZD_F_SFT 4 1883#define RT5640_ZD_F_IM (0x0 << 4) 1884#define RT5640_ZD_F_ZC_IM (0x1 << 4) 1885#define RT5640_ZD_F_ZC_IOD (0x2 << 4) 1886#define RT5640_ZD_F_UN (0x3 << 4) 1887 1888/* HP calibration control and Amp detection (0xd6) */ 1889#define RT5640_SI_DAC_MASK (0x1 << 11) 1890#define RT5640_SI_DAC_SFT 11 1891#define RT5640_SI_DAC_AUTO (0x0 << 11) 1892#define RT5640_SI_DAC_TEST (0x1 << 11) 1893#define RT5640_DC_CAL_M_MASK (0x1 << 10) 1894#define RT5640_DC_CAL_M_SFT 10 1895#define RT5640_DC_CAL_M_CAL (0x0 << 10) 1896#define RT5640_DC_CAL_M_NOR (0x1 << 10) 1897#define RT5640_DC_CAL_MASK (0x1 << 9) 1898#define RT5640_DC_CAL_SFT 9 1899#define RT5640_DC_CAL_DIS (0x0 << 9) 1900#define RT5640_DC_CAL_EN (0x1 << 9) 1901#define RT5640_HPD_RCV_MASK (0x7 << 6) 1902#define RT5640_HPD_RCV_SFT 6 1903#define RT5640_HPD_PS_MASK (0x1 << 5) 1904#define RT5640_HPD_PS_SFT 5 1905#define RT5640_HPD_PS_DIS (0x0 << 5) 1906#define RT5640_HPD_PS_EN (0x1 << 5) 1907#define RT5640_CAL_M_MASK (0x1 << 4) 1908#define RT5640_CAL_M_SFT 4 1909#define RT5640_CAL_M_DEP (0x0 << 4) 1910#define RT5640_CAL_M_CAL (0x1 << 4) 1911#define RT5640_CAL_MASK (0x1 << 3) 1912#define RT5640_CAL_SFT 3 1913#define RT5640_CAL_DIS (0x0 << 3) 1914#define RT5640_CAL_EN (0x1 << 3) 1915#define RT5640_CAL_TEST_MASK (0x1 << 2) 1916#define RT5640_CAL_TEST_SFT 2 1917#define RT5640_CAL_TEST_DIS (0x0 << 2) 1918#define RT5640_CAL_TEST_EN (0x1 << 2) 1919#define RT5640_CAL_P_MASK (0x3) 1920#define RT5640_CAL_P_SFT 0 1921#define RT5640_CAL_P_NONE (0x0) 1922#define RT5640_CAL_P_CAL (0x1) 1923#define RT5640_CAL_P_DAC_CAL (0x2) 1924 1925/* Soft volume and zero cross control 1 (0xd9) */ 1926#define RT5640_SV_MASK (0x1 << 15) 1927#define RT5640_SV_SFT 15 1928#define RT5640_SV_DIS (0x0 << 15) 1929#define RT5640_SV_EN (0x1 << 15) 1930#define RT5640_SPO_SV_MASK (0x1 << 14) 1931#define RT5640_SPO_SV_SFT 14 1932#define RT5640_SPO_SV_DIS (0x0 << 14) 1933#define RT5640_SPO_SV_EN (0x1 << 14) 1934#define RT5640_OUT_SV_MASK (0x1 << 13) 1935#define RT5640_OUT_SV_SFT 13 1936#define RT5640_OUT_SV_DIS (0x0 << 13) 1937#define RT5640_OUT_SV_EN (0x1 << 13) 1938#define RT5640_HP_SV_MASK (0x1 << 12) 1939#define RT5640_HP_SV_SFT 12 1940#define RT5640_HP_SV_DIS (0x0 << 12) 1941#define RT5640_HP_SV_EN (0x1 << 12) 1942#define RT5640_ZCD_DIG_MASK (0x1 << 11) 1943#define RT5640_ZCD_DIG_SFT 11 1944#define RT5640_ZCD_DIG_DIS (0x0 << 11) 1945#define RT5640_ZCD_DIG_EN (0x1 << 11) 1946#define RT5640_ZCD_MASK (0x1 << 10) 1947#define RT5640_ZCD_SFT 10 1948#define RT5640_ZCD_PD (0x0 << 10) 1949#define RT5640_ZCD_PU (0x1 << 10) 1950#define RT5640_M_ZCD_MASK (0x3f << 4) 1951#define RT5640_M_ZCD_SFT 4 1952#define RT5640_M_ZCD_RM_L (0x1 << 9) 1953#define RT5640_M_ZCD_RM_R (0x1 << 8) 1954#define RT5640_M_ZCD_SM_L (0x1 << 7) 1955#define RT5640_M_ZCD_SM_R (0x1 << 6) 1956#define RT5640_M_ZCD_OM_L (0x1 << 5) 1957#define RT5640_M_ZCD_OM_R (0x1 << 4) 1958#define RT5640_SV_DLY_MASK (0xf) 1959#define RT5640_SV_DLY_SFT 0 1960 1961/* Soft volume and zero cross control 2 (0xda) */ 1962#define RT5640_ZCD_HP_MASK (0x1 << 15) 1963#define RT5640_ZCD_HP_SFT 15 1964#define RT5640_ZCD_HP_DIS (0x0 << 15) 1965#define RT5640_ZCD_HP_EN (0x1 << 15) 1966 1967 1968/* Codec Private Register definition */ 1969/* 3D Speaker Control (0x63) */ 1970#define RT5640_3D_SPK_MASK (0x1 << 15) 1971#define RT5640_3D_SPK_SFT 15 1972#define RT5640_3D_SPK_DIS (0x0 << 15) 1973#define RT5640_3D_SPK_EN (0x1 << 15) 1974#define RT5640_3D_SPK_M_MASK (0x3 << 13) 1975#define RT5640_3D_SPK_M_SFT 13 1976#define RT5640_3D_SPK_CG_MASK (0x1f << 8) 1977#define RT5640_3D_SPK_CG_SFT 8 1978#define RT5640_3D_SPK_SG_MASK (0x1f) 1979#define RT5640_3D_SPK_SG_SFT 0 1980 1981/* Wind Noise Detection Control 1 (0x6c) */ 1982#define RT5640_WND_MASK (0x1 << 15) 1983#define RT5640_WND_SFT 15 1984#define RT5640_WND_DIS (0x0 << 15) 1985#define RT5640_WND_EN (0x1 << 15) 1986 1987/* Wind Noise Detection Control 2 (0x6d) */ 1988#define RT5640_WND_FC_NW_MASK (0x3f << 10) 1989#define RT5640_WND_FC_NW_SFT 10 1990#define RT5640_WND_FC_WK_MASK (0x3f << 4) 1991#define RT5640_WND_FC_WK_SFT 4 1992 1993/* Wind Noise Detection Control 3 (0x6e) */ 1994#define RT5640_HPF_FC_MASK (0x3f << 6) 1995#define RT5640_HPF_FC_SFT 6 1996#define RT5640_WND_FC_ST_MASK (0x3f) 1997#define RT5640_WND_FC_ST_SFT 0 1998 1999/* Wind Noise Detection Control 4 (0x6f) */ 2000#define RT5640_WND_TH_LO_MASK (0x3ff) 2001#define RT5640_WND_TH_LO_SFT 0 2002 2003/* Wind Noise Detection Control 5 (0x70) */ 2004#define RT5640_WND_TH_HI_MASK (0x3ff) 2005#define RT5640_WND_TH_HI_SFT 0 2006 2007/* Wind Noise Detection Control 8 (0x73) */ 2008#define RT5640_WND_WIND_MASK (0x1 << 13) /* Read-Only */ 2009#define RT5640_WND_WIND_SFT 13 2010#define RT5640_WND_STRONG_MASK (0x1 << 12) /* Read-Only */ 2011#define RT5640_WND_STRONG_SFT 12 2012enum { 2013 RT5640_NO_WIND, 2014 RT5640_BREEZE, 2015 RT5640_STORM, 2016}; 2017 2018/* Dipole Speaker Interface (0x75) */ 2019#define RT5640_DP_ATT_MASK (0x3 << 14) 2020#define RT5640_DP_ATT_SFT 14 2021#define RT5640_DP_SPK_MASK (0x1 << 10) 2022#define RT5640_DP_SPK_SFT 10 2023#define RT5640_DP_SPK_DIS (0x0 << 10) 2024#define RT5640_DP_SPK_EN (0x1 << 10) 2025 2026/* EQ Pre Volume Control (0xb3) */ 2027#define RT5640_EQ_PRE_VOL_MASK (0xffff) 2028#define RT5640_EQ_PRE_VOL_SFT 0 2029 2030/* EQ Post Volume Control (0xb4) */ 2031#define RT5640_EQ_PST_VOL_MASK (0xffff) 2032#define RT5640_EQ_PST_VOL_SFT 0 2033 2034#define RT5640_NO_JACK BIT(0) 2035#define RT5640_HEADSET_DET BIT(1) 2036#define RT5640_HEADPHO_DET BIT(2) 2037 2038/* System Clock Source */ 2039#define RT5640_SCLK_S_MCLK 0 2040#define RT5640_SCLK_S_PLL1 1 2041#define RT5640_SCLK_S_PLL1_TK 2 2042#define RT5640_SCLK_S_RCCLK 3 2043 2044/* PLL1 Source */ 2045#define RT5640_PLL1_S_MCLK 0 2046#define RT5640_PLL1_S_BCLK1 1 2047#define RT5640_PLL1_S_BCLK2 2 2048#define RT5640_PLL1_S_BCLK3 3 2049 2050 2051enum { 2052 RT5640_AIF1, 2053 RT5640_AIF2, 2054 RT5640_AIF3, 2055 RT5640_AIFS, 2056}; 2057 2058enum { 2059 RT5640_U_IF1 = 0x1, 2060 RT5640_U_IF2 = 0x2, 2061 RT5640_U_IF3 = 0x4, 2062}; 2063 2064enum { 2065 RT5640_IF_123, 2066 RT5640_IF_132, 2067 RT5640_IF_312, 2068 RT5640_IF_321, 2069 RT5640_IF_231, 2070 RT5640_IF_213, 2071 RT5640_IF_113, 2072 RT5640_IF_223, 2073 RT5640_IF_ALL, 2074}; 2075 2076enum { 2077 RT5640_DMIC_DIS, 2078 RT5640_DMIC1, 2079 RT5640_DMIC2, 2080}; 2081 2082struct rt5640_priv { 2083 struct snd_soc_codec *codec; 2084 struct rt5640_platform_data pdata; 2085 struct regmap *regmap; 2086 2087 int sysclk; 2088 int sysclk_src; 2089 int lrck[RT5640_AIFS]; 2090 int bclk[RT5640_AIFS]; 2091 int master[RT5640_AIFS]; 2092 2093 int pll_src; 2094 int pll_in; 2095 int pll_out; 2096 2097 bool hp_mute; 2098}; 2099 2100int rt5640_dmic_enable(struct snd_soc_codec *codec, 2101 bool dmic1_data_pin, bool dmic2_data_pin); 2102 2103#endif 2104