1/* 2 * Au12x0/Au1550 PSC ALSA ASoC audio support. 3 * 4 * (c) 2007-2009 MSC Vertriebsges.m.b.H., 5 * Manuel Lauss <manuel.lauss@gmail.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * Au1xxx-PSC AC97 glue. 12 * 13 */ 14 15#include <linux/init.h> 16#include <linux/module.h> 17#include <linux/slab.h> 18#include <linux/device.h> 19#include <linux/delay.h> 20#include <linux/mutex.h> 21#include <linux/suspend.h> 22#include <sound/core.h> 23#include <sound/pcm.h> 24#include <sound/initval.h> 25#include <sound/soc.h> 26#include <asm/mach-au1x00/au1000.h> 27#include <asm/mach-au1x00/au1xxx_psc.h> 28 29#include "psc.h" 30 31/* how often to retry failed codec register reads/writes */ 32#define AC97_RW_RETRIES 5 33 34#define AC97_DIR \ 35 (SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE) 36 37#define AC97_RATES \ 38 SNDRV_PCM_RATE_8000_48000 39 40#define AC97_FMTS \ 41 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3BE) 42 43#define AC97PCR_START(stype) \ 44 ((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_AC97PCR_TS : PSC_AC97PCR_RS) 45#define AC97PCR_STOP(stype) \ 46 ((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_AC97PCR_TP : PSC_AC97PCR_RP) 47#define AC97PCR_CLRFIFO(stype) \ 48 ((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_AC97PCR_TC : PSC_AC97PCR_RC) 49 50#define AC97STAT_BUSY(stype) \ 51 ((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_AC97STAT_TB : PSC_AC97STAT_RB) 52 53/* instance data. There can be only one, MacLeod!!!! */ 54static struct au1xpsc_audio_data *au1xpsc_ac97_workdata; 55 56#if 0 57 58/* this could theoretically work, but ac97->bus->card->private_data can be NULL 59 * when snd_ac97_mixer() is called; I don't know if the rest further down the 60 * chain are always valid either. 61 */ 62static inline struct au1xpsc_audio_data *ac97_to_pscdata(struct snd_ac97 *x) 63{ 64 struct snd_soc_card *c = x->bus->card->private_data; 65 return snd_soc_dai_get_drvdata(c->rtd->cpu_dai); 66} 67 68#else 69 70#define ac97_to_pscdata(x) au1xpsc_ac97_workdata 71 72#endif 73 74/* AC97 controller reads codec register */ 75static unsigned short au1xpsc_ac97_read(struct snd_ac97 *ac97, 76 unsigned short reg) 77{ 78 struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97); 79 unsigned short retry, tmo; 80 unsigned long data; 81 82 __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata)); 83 wmb(); /* drain writebuffer */ 84 85 retry = AC97_RW_RETRIES; 86 do { 87 mutex_lock(&pscdata->lock); 88 89 __raw_writel(PSC_AC97CDC_RD | PSC_AC97CDC_INDX(reg), 90 AC97_CDC(pscdata)); 91 wmb(); /* drain writebuffer */ 92 93 tmo = 20; 94 do { 95 udelay(21); 96 if (__raw_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD) 97 break; 98 } while (--tmo); 99 100 data = __raw_readl(AC97_CDC(pscdata)); 101 102 __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata)); 103 wmb(); /* drain writebuffer */ 104 105 mutex_unlock(&pscdata->lock); 106 107 if (reg != ((data >> 16) & 0x7f)) 108 tmo = 1; /* wrong register, try again */ 109 110 } while (--retry && !tmo); 111 112 return retry ? data & 0xffff : 0xffff; 113} 114 115/* AC97 controller writes to codec register */ 116static void au1xpsc_ac97_write(struct snd_ac97 *ac97, unsigned short reg, 117 unsigned short val) 118{ 119 struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97); 120 unsigned int tmo, retry; 121 122 __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata)); 123 wmb(); /* drain writebuffer */ 124 125 retry = AC97_RW_RETRIES; 126 do { 127 mutex_lock(&pscdata->lock); 128 129 __raw_writel(PSC_AC97CDC_INDX(reg) | (val & 0xffff), 130 AC97_CDC(pscdata)); 131 wmb(); /* drain writebuffer */ 132 133 tmo = 20; 134 do { 135 udelay(21); 136 if (__raw_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD) 137 break; 138 } while (--tmo); 139 140 __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata)); 141 wmb(); /* drain writebuffer */ 142 143 mutex_unlock(&pscdata->lock); 144 } while (--retry && !tmo); 145} 146 147/* AC97 controller asserts a warm reset */ 148static void au1xpsc_ac97_warm_reset(struct snd_ac97 *ac97) 149{ 150 struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97); 151 152 __raw_writel(PSC_AC97RST_SNC, AC97_RST(pscdata)); 153 wmb(); /* drain writebuffer */ 154 msleep(10); 155 __raw_writel(0, AC97_RST(pscdata)); 156 wmb(); /* drain writebuffer */ 157} 158 159static void au1xpsc_ac97_cold_reset(struct snd_ac97 *ac97) 160{ 161 struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97); 162 int i; 163 164 /* disable PSC during cold reset */ 165 __raw_writel(0, AC97_CFG(au1xpsc_ac97_workdata)); 166 wmb(); /* drain writebuffer */ 167 __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(pscdata)); 168 wmb(); /* drain writebuffer */ 169 170 /* issue cold reset */ 171 __raw_writel(PSC_AC97RST_RST, AC97_RST(pscdata)); 172 wmb(); /* drain writebuffer */ 173 msleep(500); 174 __raw_writel(0, AC97_RST(pscdata)); 175 wmb(); /* drain writebuffer */ 176 177 /* enable PSC */ 178 __raw_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata)); 179 wmb(); /* drain writebuffer */ 180 181 /* wait for PSC to indicate it's ready */ 182 i = 1000; 183 while (!((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_SR)) && (--i)) 184 msleep(1); 185 186 if (i == 0) { 187 printk(KERN_ERR "au1xpsc-ac97: PSC not ready!\n"); 188 return; 189 } 190 191 /* enable the ac97 function */ 192 __raw_writel(pscdata->cfg | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata)); 193 wmb(); /* drain writebuffer */ 194 195 /* wait for AC97 core to become ready */ 196 i = 1000; 197 while (!((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && (--i)) 198 msleep(1); 199 if (i == 0) 200 printk(KERN_ERR "au1xpsc-ac97: AC97 ctrl not ready\n"); 201} 202 203/* AC97 controller operations */ 204static struct snd_ac97_bus_ops psc_ac97_ops = { 205 .read = au1xpsc_ac97_read, 206 .write = au1xpsc_ac97_write, 207 .reset = au1xpsc_ac97_cold_reset, 208 .warm_reset = au1xpsc_ac97_warm_reset, 209}; 210 211static int au1xpsc_ac97_hw_params(struct snd_pcm_substream *substream, 212 struct snd_pcm_hw_params *params, 213 struct snd_soc_dai *dai) 214{ 215 struct au1xpsc_audio_data *pscdata = snd_soc_dai_get_drvdata(dai); 216 unsigned long r, ro, stat; 217 int chans, t, stype = substream->stream; 218 219 chans = params_channels(params); 220 221 r = ro = __raw_readl(AC97_CFG(pscdata)); 222 stat = __raw_readl(AC97_STAT(pscdata)); 223 224 /* already active? */ 225 if (stat & (PSC_AC97STAT_TB | PSC_AC97STAT_RB)) { 226 /* reject parameters not currently set up */ 227 if ((PSC_AC97CFG_GET_LEN(r) != params->msbits) || 228 (pscdata->rate != params_rate(params))) 229 return -EINVAL; 230 } else { 231 232 /* set sample bitdepth: REG[24:21]=(BITS-2)/2 */ 233 r &= ~PSC_AC97CFG_LEN_MASK; 234 r |= PSC_AC97CFG_SET_LEN(params->msbits); 235 236 /* channels: enable slots for front L/R channel */ 237 if (stype == SNDRV_PCM_STREAM_PLAYBACK) { 238 r &= ~PSC_AC97CFG_TXSLOT_MASK; 239 r |= PSC_AC97CFG_TXSLOT_ENA(3); 240 r |= PSC_AC97CFG_TXSLOT_ENA(4); 241 } else { 242 r &= ~PSC_AC97CFG_RXSLOT_MASK; 243 r |= PSC_AC97CFG_RXSLOT_ENA(3); 244 r |= PSC_AC97CFG_RXSLOT_ENA(4); 245 } 246 247 /* do we need to poke the hardware? */ 248 if (!(r ^ ro)) 249 goto out; 250 251 /* ac97 engine is about to be disabled */ 252 mutex_lock(&pscdata->lock); 253 254 /* disable AC97 device controller first... */ 255 __raw_writel(r & ~PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata)); 256 wmb(); /* drain writebuffer */ 257 258 /* ...wait for it... */ 259 t = 100; 260 while ((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR) && --t) 261 msleep(1); 262 263 if (!t) 264 printk(KERN_ERR "PSC-AC97: can't disable!\n"); 265 266 /* ...write config... */ 267 __raw_writel(r, AC97_CFG(pscdata)); 268 wmb(); /* drain writebuffer */ 269 270 /* ...enable the AC97 controller again... */ 271 __raw_writel(r | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata)); 272 wmb(); /* drain writebuffer */ 273 274 /* ...and wait for ready bit */ 275 t = 100; 276 while ((!(__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && --t) 277 msleep(1); 278 279 if (!t) 280 printk(KERN_ERR "PSC-AC97: can't enable!\n"); 281 282 mutex_unlock(&pscdata->lock); 283 284 pscdata->cfg = r; 285 pscdata->rate = params_rate(params); 286 } 287 288out: 289 return 0; 290} 291 292static int au1xpsc_ac97_trigger(struct snd_pcm_substream *substream, 293 int cmd, struct snd_soc_dai *dai) 294{ 295 struct au1xpsc_audio_data *pscdata = snd_soc_dai_get_drvdata(dai); 296 int ret, stype = substream->stream; 297 298 ret = 0; 299 300 switch (cmd) { 301 case SNDRV_PCM_TRIGGER_START: 302 case SNDRV_PCM_TRIGGER_RESUME: 303 __raw_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata)); 304 wmb(); /* drain writebuffer */ 305 __raw_writel(AC97PCR_START(stype), AC97_PCR(pscdata)); 306 wmb(); /* drain writebuffer */ 307 break; 308 case SNDRV_PCM_TRIGGER_STOP: 309 case SNDRV_PCM_TRIGGER_SUSPEND: 310 __raw_writel(AC97PCR_STOP(stype), AC97_PCR(pscdata)); 311 wmb(); /* drain writebuffer */ 312 313 while (__raw_readl(AC97_STAT(pscdata)) & AC97STAT_BUSY(stype)) 314 asm volatile ("nop"); 315 316 __raw_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata)); 317 wmb(); /* drain writebuffer */ 318 319 break; 320 default: 321 ret = -EINVAL; 322 } 323 return ret; 324} 325 326static int au1xpsc_ac97_startup(struct snd_pcm_substream *substream, 327 struct snd_soc_dai *dai) 328{ 329 struct au1xpsc_audio_data *pscdata = snd_soc_dai_get_drvdata(dai); 330 snd_soc_dai_set_dma_data(dai, substream, &pscdata->dmaids[0]); 331 return 0; 332} 333 334static int au1xpsc_ac97_probe(struct snd_soc_dai *dai) 335{ 336 return au1xpsc_ac97_workdata ? 0 : -ENODEV; 337} 338 339static const struct snd_soc_dai_ops au1xpsc_ac97_dai_ops = { 340 .startup = au1xpsc_ac97_startup, 341 .trigger = au1xpsc_ac97_trigger, 342 .hw_params = au1xpsc_ac97_hw_params, 343}; 344 345static const struct snd_soc_dai_driver au1xpsc_ac97_dai_template = { 346 .bus_control = true, 347 .probe = au1xpsc_ac97_probe, 348 .playback = { 349 .rates = AC97_RATES, 350 .formats = AC97_FMTS, 351 .channels_min = 2, 352 .channels_max = 2, 353 }, 354 .capture = { 355 .rates = AC97_RATES, 356 .formats = AC97_FMTS, 357 .channels_min = 2, 358 .channels_max = 2, 359 }, 360 .ops = &au1xpsc_ac97_dai_ops, 361}; 362 363static const struct snd_soc_component_driver au1xpsc_ac97_component = { 364 .name = "au1xpsc-ac97", 365}; 366 367static int au1xpsc_ac97_drvprobe(struct platform_device *pdev) 368{ 369 int ret; 370 struct resource *iores, *dmares; 371 unsigned long sel; 372 struct au1xpsc_audio_data *wd; 373 374 wd = devm_kzalloc(&pdev->dev, sizeof(struct au1xpsc_audio_data), 375 GFP_KERNEL); 376 if (!wd) 377 return -ENOMEM; 378 379 mutex_init(&wd->lock); 380 381 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 382 wd->mmio = devm_ioremap_resource(&pdev->dev, iores); 383 if (IS_ERR(wd->mmio)) 384 return PTR_ERR(wd->mmio); 385 386 dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0); 387 if (!dmares) 388 return -EBUSY; 389 wd->dmaids[SNDRV_PCM_STREAM_PLAYBACK] = dmares->start; 390 391 dmares = platform_get_resource(pdev, IORESOURCE_DMA, 1); 392 if (!dmares) 393 return -EBUSY; 394 wd->dmaids[SNDRV_PCM_STREAM_CAPTURE] = dmares->start; 395 396 /* configuration: max dma trigger threshold, enable ac97 */ 397 wd->cfg = PSC_AC97CFG_RT_FIFO8 | PSC_AC97CFG_TT_FIFO8 | 398 PSC_AC97CFG_DE_ENABLE; 399 400 /* preserve PSC clock source set up by platform */ 401 sel = __raw_readl(PSC_SEL(wd)) & PSC_SEL_CLK_MASK; 402 __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd)); 403 wmb(); /* drain writebuffer */ 404 __raw_writel(0, PSC_SEL(wd)); 405 wmb(); /* drain writebuffer */ 406 __raw_writel(PSC_SEL_PS_AC97MODE | sel, PSC_SEL(wd)); 407 wmb(); /* drain writebuffer */ 408 409 /* name the DAI like this device instance ("au1xpsc-ac97.PSCINDEX") */ 410 memcpy(&wd->dai_drv, &au1xpsc_ac97_dai_template, 411 sizeof(struct snd_soc_dai_driver)); 412 wd->dai_drv.name = dev_name(&pdev->dev); 413 414 platform_set_drvdata(pdev, wd); 415 416 ret = snd_soc_set_ac97_ops(&psc_ac97_ops); 417 if (ret) 418 return ret; 419 420 ret = snd_soc_register_component(&pdev->dev, &au1xpsc_ac97_component, 421 &wd->dai_drv, 1); 422 if (ret) 423 return ret; 424 425 au1xpsc_ac97_workdata = wd; 426 return 0; 427} 428 429static int au1xpsc_ac97_drvremove(struct platform_device *pdev) 430{ 431 struct au1xpsc_audio_data *wd = platform_get_drvdata(pdev); 432 433 snd_soc_unregister_component(&pdev->dev); 434 435 /* disable PSC completely */ 436 __raw_writel(0, AC97_CFG(wd)); 437 wmb(); /* drain writebuffer */ 438 __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd)); 439 wmb(); /* drain writebuffer */ 440 441 au1xpsc_ac97_workdata = NULL; /* MDEV */ 442 443 return 0; 444} 445 446#ifdef CONFIG_PM 447static int au1xpsc_ac97_drvsuspend(struct device *dev) 448{ 449 struct au1xpsc_audio_data *wd = dev_get_drvdata(dev); 450 451 /* save interesting registers and disable PSC */ 452 wd->pm[0] = __raw_readl(PSC_SEL(wd)); 453 454 __raw_writel(0, AC97_CFG(wd)); 455 wmb(); /* drain writebuffer */ 456 __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd)); 457 wmb(); /* drain writebuffer */ 458 459 return 0; 460} 461 462static int au1xpsc_ac97_drvresume(struct device *dev) 463{ 464 struct au1xpsc_audio_data *wd = dev_get_drvdata(dev); 465 466 /* restore PSC clock config */ 467 __raw_writel(wd->pm[0] | PSC_SEL_PS_AC97MODE, PSC_SEL(wd)); 468 wmb(); /* drain writebuffer */ 469 470 /* after this point the ac97 core will cold-reset the codec. 471 * During cold-reset the PSC is reinitialized and the last 472 * configuration set up in hw_params() is restored. 473 */ 474 return 0; 475} 476 477static struct dev_pm_ops au1xpscac97_pmops = { 478 .suspend = au1xpsc_ac97_drvsuspend, 479 .resume = au1xpsc_ac97_drvresume, 480}; 481 482#define AU1XPSCAC97_PMOPS &au1xpscac97_pmops 483 484#else 485 486#define AU1XPSCAC97_PMOPS NULL 487 488#endif 489 490static struct platform_driver au1xpsc_ac97_driver = { 491 .driver = { 492 .name = "au1xpsc_ac97", 493 .pm = AU1XPSCAC97_PMOPS, 494 }, 495 .probe = au1xpsc_ac97_drvprobe, 496 .remove = au1xpsc_ac97_drvremove, 497}; 498 499module_platform_driver(au1xpsc_ac97_driver); 500 501MODULE_LICENSE("GPL"); 502MODULE_DESCRIPTION("Au12x0/Au1550 PSC AC97 ALSA ASoC audio driver"); 503MODULE_AUTHOR("Manuel Lauss"); 504 505