1/* 2 * 3 * hda_intel.c - Implementation of primary alsa driver code base 4 * for Intel HD Audio. 5 * 6 * Copyright(c) 2004 Intel Corporation. All rights reserved. 7 * 8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 9 * PeiSen Hou <pshou@realtek.com.tw> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the Free 13 * Software Foundation; either version 2 of the License, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 19 * more details. 20 * 21 * You should have received a copy of the GNU General Public License along with 22 * this program; if not, write to the Free Software Foundation, Inc., 59 23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 24 * 25 * CONTACTS: 26 * 27 * Matt Jared matt.jared@intel.com 28 * Andy Kopp andy.kopp@intel.com 29 * Dan Kogan dan.d.kogan@intel.com 30 * 31 * CHANGES: 32 * 33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 34 * 35 */ 36 37#include <linux/delay.h> 38#include <linux/interrupt.h> 39#include <linux/kernel.h> 40#include <linux/module.h> 41#include <linux/dma-mapping.h> 42#include <linux/moduleparam.h> 43#include <linux/init.h> 44#include <linux/slab.h> 45#include <linux/pci.h> 46#include <linux/mutex.h> 47#include <linux/io.h> 48#include <linux/pm_runtime.h> 49#include <linux/clocksource.h> 50#include <linux/time.h> 51#include <linux/completion.h> 52 53#ifdef CONFIG_X86 54/* for snoop control */ 55#include <asm/pgtable.h> 56#include <asm/cacheflush.h> 57#endif 58#include <sound/core.h> 59#include <sound/initval.h> 60#include <linux/vgaarb.h> 61#include <linux/vga_switcheroo.h> 62#include <linux/firmware.h> 63#include "hda_codec.h" 64#include "hda_controller.h" 65#include "hda_intel.h" 66 67/* position fix mode */ 68enum { 69 POS_FIX_AUTO, 70 POS_FIX_LPIB, 71 POS_FIX_POSBUF, 72 POS_FIX_VIACOMBO, 73 POS_FIX_COMBO, 74}; 75 76/* Defines for ATI HD Audio support in SB450 south bridge */ 77#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 78#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 79 80/* Defines for Nvidia HDA support */ 81#define NVIDIA_HDA_TRANSREG_ADDR 0x4e 82#define NVIDIA_HDA_ENABLE_COHBITS 0x0f 83#define NVIDIA_HDA_ISTRM_COH 0x4d 84#define NVIDIA_HDA_OSTRM_COH 0x4c 85#define NVIDIA_HDA_ENABLE_COHBIT 0x01 86 87/* Defines for Intel SCH HDA snoop control */ 88#define INTEL_SCH_HDA_DEVC 0x78 89#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 90 91/* Define IN stream 0 FIFO size offset in VIA controller */ 92#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90 93/* Define VIA HD Audio Device ID*/ 94#define VIA_HDAC_DEVICE_ID 0x3288 95 96/* max number of SDs */ 97/* ICH, ATI and VIA have 4 playback and 4 capture */ 98#define ICH6_NUM_CAPTURE 4 99#define ICH6_NUM_PLAYBACK 4 100 101/* ULI has 6 playback and 5 capture */ 102#define ULI_NUM_CAPTURE 5 103#define ULI_NUM_PLAYBACK 6 104 105/* ATI HDMI may have up to 8 playbacks and 0 capture */ 106#define ATIHDMI_NUM_CAPTURE 0 107#define ATIHDMI_NUM_PLAYBACK 8 108 109/* TERA has 4 playback and 3 capture */ 110#define TERA_NUM_CAPTURE 3 111#define TERA_NUM_PLAYBACK 4 112 113 114static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 115static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 116static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 117static char *model[SNDRV_CARDS]; 118static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 119static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 120static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 121static int probe_only[SNDRV_CARDS]; 122static int jackpoll_ms[SNDRV_CARDS]; 123static bool single_cmd; 124static int enable_msi = -1; 125#ifdef CONFIG_SND_HDA_PATCH_LOADER 126static char *patch[SNDRV_CARDS]; 127#endif 128#ifdef CONFIG_SND_HDA_INPUT_BEEP 129static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 130 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 131#endif 132 133module_param_array(index, int, NULL, 0444); 134MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 135module_param_array(id, charp, NULL, 0444); 136MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 137module_param_array(enable, bool, NULL, 0444); 138MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 139module_param_array(model, charp, NULL, 0444); 140MODULE_PARM_DESC(model, "Use the given board model."); 141module_param_array(position_fix, int, NULL, 0444); 142MODULE_PARM_DESC(position_fix, "DMA pointer read method." 143 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO)."); 144module_param_array(bdl_pos_adj, int, NULL, 0644); 145MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 146module_param_array(probe_mask, int, NULL, 0444); 147MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 148module_param_array(probe_only, int, NULL, 0444); 149MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 150module_param_array(jackpoll_ms, int, NULL, 0444); 151MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 152module_param(single_cmd, bool, 0444); 153MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 154 "(for debugging only)."); 155module_param(enable_msi, bint, 0444); 156MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 157#ifdef CONFIG_SND_HDA_PATCH_LOADER 158module_param_array(patch, charp, NULL, 0444); 159MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 160#endif 161#ifdef CONFIG_SND_HDA_INPUT_BEEP 162module_param_array(beep_mode, bool, NULL, 0444); 163MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 164 "(0=off, 1=on) (default=1)."); 165#endif 166 167#ifdef CONFIG_PM 168static int param_set_xint(const char *val, const struct kernel_param *kp); 169static struct kernel_param_ops param_ops_xint = { 170 .set = param_set_xint, 171 .get = param_get_int, 172}; 173#define param_check_xint param_check_int 174 175static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 176module_param(power_save, xint, 0644); 177MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 178 "(in second, 0 = disable)."); 179 180/* reset the HD-audio controller in power save mode. 181 * this may give more power-saving, but will take longer time to 182 * wake up. 183 */ 184static bool power_save_controller = 1; 185module_param(power_save_controller, bool, 0644); 186MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 187#else 188#define power_save 0 189#endif /* CONFIG_PM */ 190 191static int align_buffer_size = -1; 192module_param(align_buffer_size, bint, 0644); 193MODULE_PARM_DESC(align_buffer_size, 194 "Force buffer and period sizes to be multiple of 128 bytes."); 195 196#ifdef CONFIG_X86 197static int hda_snoop = -1; 198module_param_named(snoop, hda_snoop, bint, 0444); 199MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 200#else 201#define hda_snoop true 202#endif 203 204 205MODULE_LICENSE("GPL"); 206MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," 207 "{Intel, ICH6M}," 208 "{Intel, ICH7}," 209 "{Intel, ESB2}," 210 "{Intel, ICH8}," 211 "{Intel, ICH9}," 212 "{Intel, ICH10}," 213 "{Intel, PCH}," 214 "{Intel, CPT}," 215 "{Intel, PPT}," 216 "{Intel, LPT}," 217 "{Intel, LPT_LP}," 218 "{Intel, WPT_LP}," 219 "{Intel, SPT}," 220 "{Intel, SPT_LP}," 221 "{Intel, HPT}," 222 "{Intel, PBG}," 223 "{Intel, SCH}," 224 "{ATI, SB450}," 225 "{ATI, SB600}," 226 "{ATI, RS600}," 227 "{ATI, RS690}," 228 "{ATI, RS780}," 229 "{ATI, R600}," 230 "{ATI, RV630}," 231 "{ATI, RV610}," 232 "{ATI, RV670}," 233 "{ATI, RV635}," 234 "{ATI, RV620}," 235 "{ATI, RV770}," 236 "{VIA, VT8251}," 237 "{VIA, VT8237A}," 238 "{SiS, SIS966}," 239 "{ULI, M5461}}"); 240MODULE_DESCRIPTION("Intel HDA driver"); 241 242#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 243#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 244#define SUPPORT_VGA_SWITCHEROO 245#endif 246#endif 247 248 249/* 250 */ 251 252/* driver types */ 253enum { 254 AZX_DRIVER_ICH, 255 AZX_DRIVER_PCH, 256 AZX_DRIVER_SCH, 257 AZX_DRIVER_HDMI, 258 AZX_DRIVER_ATI, 259 AZX_DRIVER_ATIHDMI, 260 AZX_DRIVER_ATIHDMI_NS, 261 AZX_DRIVER_VIA, 262 AZX_DRIVER_SIS, 263 AZX_DRIVER_ULI, 264 AZX_DRIVER_NVIDIA, 265 AZX_DRIVER_TERA, 266 AZX_DRIVER_CTX, 267 AZX_DRIVER_CTHDA, 268 AZX_DRIVER_CMEDIA, 269 AZX_DRIVER_GENERIC, 270 AZX_NUM_DRIVERS, /* keep this as last entry */ 271}; 272 273#define azx_get_snoop_type(chip) \ 274 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) 275#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) 276 277/* quirks for old Intel chipsets */ 278#define AZX_DCAPS_INTEL_ICH \ 279 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE) 280 281/* quirks for Intel PCH */ 282#define AZX_DCAPS_INTEL_PCH_NOPM \ 283 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ 284 AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH)) 285 286#define AZX_DCAPS_INTEL_PCH \ 287 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME) 288 289#define AZX_DCAPS_INTEL_HASWELL \ 290 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ 291 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\ 292 AZX_DCAPS_SNOOP_TYPE(SCH)) 293 294/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ 295#define AZX_DCAPS_INTEL_BROADWELL \ 296 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ 297 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\ 298 AZX_DCAPS_SNOOP_TYPE(SCH)) 299 300#define AZX_DCAPS_INTEL_BAYTRAIL \ 301 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL) 302 303#define AZX_DCAPS_INTEL_BRASWELL \ 304 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL) 305 306#define AZX_DCAPS_INTEL_SKYLAKE \ 307 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\ 308 AZX_DCAPS_I915_POWERWELL) 309 310#define AZX_DCAPS_INTEL_BROXTON \ 311 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\ 312 AZX_DCAPS_I915_POWERWELL) 313 314/* quirks for ATI SB / AMD Hudson */ 315#define AZX_DCAPS_PRESET_ATI_SB \ 316 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\ 317 AZX_DCAPS_SNOOP_TYPE(ATI)) 318 319/* quirks for ATI/AMD HDMI */ 320#define AZX_DCAPS_PRESET_ATI_HDMI \ 321 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\ 322 AZX_DCAPS_NO_MSI64) 323 324/* quirks for ATI HDMI with snoop off */ 325#define AZX_DCAPS_PRESET_ATI_HDMI_NS \ 326 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF) 327 328/* quirks for Nvidia */ 329#define AZX_DCAPS_PRESET_NVIDIA \ 330 (AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \ 331 AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\ 332 AZX_DCAPS_SNOOP_TYPE(NVIDIA)) 333 334#define AZX_DCAPS_PRESET_CTHDA \ 335 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ 336 AZX_DCAPS_NO_64BIT |\ 337 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) 338 339/* 340 * VGA-switcher support 341 */ 342#ifdef SUPPORT_VGA_SWITCHEROO 343#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 344#else 345#define use_vga_switcheroo(chip) 0 346#endif 347 348#define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \ 349 ((pci)->device == 0x0c0c) || \ 350 ((pci)->device == 0x0d0c) || \ 351 ((pci)->device == 0x160c)) 352 353static char *driver_short_names[] = { 354 [AZX_DRIVER_ICH] = "HDA Intel", 355 [AZX_DRIVER_PCH] = "HDA Intel PCH", 356 [AZX_DRIVER_SCH] = "HDA Intel MID", 357 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 358 [AZX_DRIVER_ATI] = "HDA ATI SB", 359 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 360 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 361 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 362 [AZX_DRIVER_SIS] = "HDA SIS966", 363 [AZX_DRIVER_ULI] = "HDA ULI M5461", 364 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 365 [AZX_DRIVER_TERA] = "HDA Teradici", 366 [AZX_DRIVER_CTX] = "HDA Creative", 367 [AZX_DRIVER_CTHDA] = "HDA Creative", 368 [AZX_DRIVER_CMEDIA] = "HDA C-Media", 369 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 370}; 371 372#ifdef CONFIG_X86 373static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on) 374{ 375 int pages; 376 377 if (azx_snoop(chip)) 378 return; 379 if (!dmab || !dmab->area || !dmab->bytes) 380 return; 381 382#ifdef CONFIG_SND_DMA_SGBUF 383 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) { 384 struct snd_sg_buf *sgbuf = dmab->private_data; 385 if (chip->driver_type == AZX_DRIVER_CMEDIA) 386 return; /* deal with only CORB/RIRB buffers */ 387 if (on) 388 set_pages_array_wc(sgbuf->page_table, sgbuf->pages); 389 else 390 set_pages_array_wb(sgbuf->page_table, sgbuf->pages); 391 return; 392 } 393#endif 394 395 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT; 396 if (on) 397 set_memory_wc((unsigned long)dmab->area, pages); 398 else 399 set_memory_wb((unsigned long)dmab->area, pages); 400} 401 402static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, 403 bool on) 404{ 405 __mark_pages_wc(chip, buf, on); 406} 407static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, 408 struct snd_pcm_substream *substream, bool on) 409{ 410 if (azx_dev->wc_marked != on) { 411 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on); 412 azx_dev->wc_marked = on; 413 } 414} 415#else 416/* NOP for other archs */ 417static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, 418 bool on) 419{ 420} 421static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, 422 struct snd_pcm_substream *substream, bool on) 423{ 424} 425#endif 426 427static int azx_acquire_irq(struct azx *chip, int do_disconnect); 428 429/* 430 * initialize the PCI registers 431 */ 432/* update bits in a PCI register byte */ 433static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 434 unsigned char mask, unsigned char val) 435{ 436 unsigned char data; 437 438 pci_read_config_byte(pci, reg, &data); 439 data &= ~mask; 440 data |= (val & mask); 441 pci_write_config_byte(pci, reg, data); 442} 443 444static void azx_init_pci(struct azx *chip) 445{ 446 int snoop_type = azx_get_snoop_type(chip); 447 448 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 449 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 450 * Ensuring these bits are 0 clears playback static on some HD Audio 451 * codecs. 452 * The PCI register TCSEL is defined in the Intel manuals. 453 */ 454 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 455 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 456 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); 457 } 458 459 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 460 * we need to enable snoop. 461 */ 462 if (snoop_type == AZX_SNOOP_TYPE_ATI) { 463 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", 464 azx_snoop(chip)); 465 update_pci_byte(chip->pci, 466 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 467 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 468 } 469 470 /* For NVIDIA HDA, enable snoop */ 471 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { 472 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", 473 azx_snoop(chip)); 474 update_pci_byte(chip->pci, 475 NVIDIA_HDA_TRANSREG_ADDR, 476 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 477 update_pci_byte(chip->pci, 478 NVIDIA_HDA_ISTRM_COH, 479 0x01, NVIDIA_HDA_ENABLE_COHBIT); 480 update_pci_byte(chip->pci, 481 NVIDIA_HDA_OSTRM_COH, 482 0x01, NVIDIA_HDA_ENABLE_COHBIT); 483 } 484 485 /* Enable SCH/PCH snoop if needed */ 486 if (snoop_type == AZX_SNOOP_TYPE_SCH) { 487 unsigned short snoop; 488 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 489 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 490 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 491 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 492 if (!azx_snoop(chip)) 493 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 494 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 495 pci_read_config_word(chip->pci, 496 INTEL_SCH_HDA_DEVC, &snoop); 497 } 498 dev_dbg(chip->card->dev, "SCH snoop: %s\n", 499 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? 500 "Disabled" : "Enabled"); 501 } 502} 503 504/* calculate runtime delay from LPIB */ 505static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, 506 unsigned int pos) 507{ 508 struct snd_pcm_substream *substream = azx_dev->substream; 509 int stream = substream->stream; 510 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); 511 int delay; 512 513 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 514 delay = pos - lpib_pos; 515 else 516 delay = lpib_pos - pos; 517 if (delay < 0) { 518 if (delay >= azx_dev->delay_negative_threshold) 519 delay = 0; 520 else 521 delay += azx_dev->bufsize; 522 } 523 524 if (delay >= azx_dev->period_bytes) { 525 dev_info(chip->card->dev, 526 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", 527 delay, azx_dev->period_bytes); 528 delay = 0; 529 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 530 chip->get_delay[stream] = NULL; 531 } 532 533 return bytes_to_frames(substream->runtime, delay); 534} 535 536static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 537 538/* called from IRQ */ 539static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 540{ 541 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 542 int ok; 543 544 ok = azx_position_ok(chip, azx_dev); 545 if (ok == 1) { 546 azx_dev->irq_pending = 0; 547 return ok; 548 } else if (ok == 0) { 549 /* bogus IRQ, process it later */ 550 azx_dev->irq_pending = 1; 551 schedule_work(&hda->irq_pending_work); 552 } 553 return 0; 554} 555 556/* 557 * Check whether the current DMA position is acceptable for updating 558 * periods. Returns non-zero if it's OK. 559 * 560 * Many HD-audio controllers appear pretty inaccurate about 561 * the update-IRQ timing. The IRQ is issued before actually the 562 * data is processed. So, we need to process it afterwords in a 563 * workqueue. 564 */ 565static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 566{ 567 struct snd_pcm_substream *substream = azx_dev->substream; 568 int stream = substream->stream; 569 u32 wallclk; 570 unsigned int pos; 571 572 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk; 573 if (wallclk < (azx_dev->period_wallclk * 2) / 3) 574 return -1; /* bogus (too early) interrupt */ 575 576 if (chip->get_position[stream]) 577 pos = chip->get_position[stream](chip, azx_dev); 578 else { /* use the position buffer as default */ 579 pos = azx_get_pos_posbuf(chip, azx_dev); 580 if (!pos || pos == (u32)-1) { 581 dev_info(chip->card->dev, 582 "Invalid position buffer, using LPIB read method instead.\n"); 583 chip->get_position[stream] = azx_get_pos_lpib; 584 pos = azx_get_pos_lpib(chip, azx_dev); 585 chip->get_delay[stream] = NULL; 586 } else { 587 chip->get_position[stream] = azx_get_pos_posbuf; 588 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) 589 chip->get_delay[stream] = azx_get_delay_from_lpib; 590 } 591 } 592 593 if (pos >= azx_dev->bufsize) 594 pos = 0; 595 596 if (WARN_ONCE(!azx_dev->period_bytes, 597 "hda-intel: zero azx_dev->period_bytes")) 598 return -1; /* this shouldn't happen! */ 599 if (wallclk < (azx_dev->period_wallclk * 5) / 4 && 600 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2) 601 /* NG - it's below the first next period boundary */ 602 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1; 603 azx_dev->start_wallclk += wallclk; 604 return 1; /* OK, it's fine */ 605} 606 607/* 608 * The work for pending PCM period updates. 609 */ 610static void azx_irq_pending_work(struct work_struct *work) 611{ 612 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); 613 struct azx *chip = &hda->chip; 614 int i, pending, ok; 615 616 if (!hda->irq_pending_warned) { 617 dev_info(chip->card->dev, 618 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 619 chip->card->number); 620 hda->irq_pending_warned = 1; 621 } 622 623 for (;;) { 624 pending = 0; 625 spin_lock_irq(&chip->reg_lock); 626 for (i = 0; i < chip->num_streams; i++) { 627 struct azx_dev *azx_dev = &chip->azx_dev[i]; 628 if (!azx_dev->irq_pending || 629 !azx_dev->substream || 630 !azx_dev->running) 631 continue; 632 ok = azx_position_ok(chip, azx_dev); 633 if (ok > 0) { 634 azx_dev->irq_pending = 0; 635 spin_unlock(&chip->reg_lock); 636 snd_pcm_period_elapsed(azx_dev->substream); 637 spin_lock(&chip->reg_lock); 638 } else if (ok < 0) { 639 pending = 0; /* too early */ 640 } else 641 pending++; 642 } 643 spin_unlock_irq(&chip->reg_lock); 644 if (!pending) 645 return; 646 msleep(1); 647 } 648} 649 650/* clear irq_pending flags and assure no on-going workq */ 651static void azx_clear_irq_pending(struct azx *chip) 652{ 653 int i; 654 655 spin_lock_irq(&chip->reg_lock); 656 for (i = 0; i < chip->num_streams; i++) 657 chip->azx_dev[i].irq_pending = 0; 658 spin_unlock_irq(&chip->reg_lock); 659} 660 661static int azx_acquire_irq(struct azx *chip, int do_disconnect) 662{ 663 if (request_irq(chip->pci->irq, azx_interrupt, 664 chip->msi ? 0 : IRQF_SHARED, 665 KBUILD_MODNAME, chip)) { 666 dev_err(chip->card->dev, 667 "unable to grab IRQ %d, disabling device\n", 668 chip->pci->irq); 669 if (do_disconnect) 670 snd_card_disconnect(chip->card); 671 return -1; 672 } 673 chip->irq = chip->pci->irq; 674 pci_intx(chip->pci, !chip->msi); 675 return 0; 676} 677 678/* get the current DMA position with correction on VIA chips */ 679static unsigned int azx_via_get_position(struct azx *chip, 680 struct azx_dev *azx_dev) 681{ 682 unsigned int link_pos, mini_pos, bound_pos; 683 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 684 unsigned int fifo_size; 685 686 link_pos = azx_sd_readl(chip, azx_dev, SD_LPIB); 687 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 688 /* Playback, no problem using link position */ 689 return link_pos; 690 } 691 692 /* Capture */ 693 /* For new chipset, 694 * use mod to get the DMA position just like old chipset 695 */ 696 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf); 697 mod_dma_pos %= azx_dev->period_bytes; 698 699 /* azx_dev->fifo_size can't get FIFO size of in stream. 700 * Get from base address + offset. 701 */ 702 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET); 703 704 if (azx_dev->insufficient) { 705 /* Link position never gather than FIFO size */ 706 if (link_pos <= fifo_size) 707 return 0; 708 709 azx_dev->insufficient = 0; 710 } 711 712 if (link_pos <= fifo_size) 713 mini_pos = azx_dev->bufsize + link_pos - fifo_size; 714 else 715 mini_pos = link_pos - fifo_size; 716 717 /* Find nearest previous boudary */ 718 mod_mini_pos = mini_pos % azx_dev->period_bytes; 719 mod_link_pos = link_pos % azx_dev->period_bytes; 720 if (mod_link_pos >= fifo_size) 721 bound_pos = link_pos - mod_link_pos; 722 else if (mod_dma_pos >= mod_mini_pos) 723 bound_pos = mini_pos - mod_mini_pos; 724 else { 725 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes; 726 if (bound_pos >= azx_dev->bufsize) 727 bound_pos = 0; 728 } 729 730 /* Calculate real DMA position we want */ 731 return bound_pos + mod_dma_pos; 732} 733 734#ifdef CONFIG_PM 735static DEFINE_MUTEX(card_list_lock); 736static LIST_HEAD(card_list); 737 738static void azx_add_card_list(struct azx *chip) 739{ 740 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 741 mutex_lock(&card_list_lock); 742 list_add(&hda->list, &card_list); 743 mutex_unlock(&card_list_lock); 744} 745 746static void azx_del_card_list(struct azx *chip) 747{ 748 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 749 mutex_lock(&card_list_lock); 750 list_del_init(&hda->list); 751 mutex_unlock(&card_list_lock); 752} 753 754/* trigger power-save check at writing parameter */ 755static int param_set_xint(const char *val, const struct kernel_param *kp) 756{ 757 struct hda_intel *hda; 758 struct azx *chip; 759 int prev = power_save; 760 int ret = param_set_int(val, kp); 761 762 if (ret || prev == power_save) 763 return ret; 764 765 mutex_lock(&card_list_lock); 766 list_for_each_entry(hda, &card_list, list) { 767 chip = &hda->chip; 768 if (!chip->bus || chip->disabled) 769 continue; 770 snd_hda_set_power_save(chip->bus, power_save * 1000); 771 } 772 mutex_unlock(&card_list_lock); 773 return 0; 774} 775#else 776#define azx_add_card_list(chip) /* NOP */ 777#define azx_del_card_list(chip) /* NOP */ 778#endif /* CONFIG_PM */ 779 780#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO) 781/* 782 * power management 783 */ 784static int azx_suspend(struct device *dev) 785{ 786 struct snd_card *card = dev_get_drvdata(dev); 787 struct azx *chip; 788 struct hda_intel *hda; 789 790 if (!card) 791 return 0; 792 793 chip = card->private_data; 794 hda = container_of(chip, struct hda_intel, chip); 795 if (chip->disabled || hda->init_failed) 796 return 0; 797 798 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 799 azx_clear_irq_pending(chip); 800 azx_stop_chip(chip); 801 azx_enter_link_reset(chip); 802 if (chip->irq >= 0) { 803 free_irq(chip->irq, chip); 804 chip->irq = -1; 805 } 806 807 if (chip->msi) 808 pci_disable_msi(chip->pci); 809 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 810 hda_display_power(hda, false); 811 return 0; 812} 813 814static int azx_resume(struct device *dev) 815{ 816 struct pci_dev *pci = to_pci_dev(dev); 817 struct snd_card *card = dev_get_drvdata(dev); 818 struct azx *chip; 819 struct hda_intel *hda; 820 821 if (!card) 822 return 0; 823 824 chip = card->private_data; 825 hda = container_of(chip, struct hda_intel, chip); 826 if (chip->disabled || hda->init_failed) 827 return 0; 828 829 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 830 hda_display_power(hda, true); 831 haswell_set_bclk(hda); 832 } 833 if (chip->msi) 834 if (pci_enable_msi(pci) < 0) 835 chip->msi = 0; 836 if (azx_acquire_irq(chip, 1) < 0) 837 return -EIO; 838 azx_init_pci(chip); 839 840 azx_init_chip(chip, true); 841 842 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 843 return 0; 844} 845#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */ 846 847#ifdef CONFIG_PM_SLEEP 848/* put codec down to D3 at hibernation for Intel SKL+; 849 * otherwise BIOS may still access the codec and screw up the driver 850 */ 851#define IS_SKL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa170) 852#define IS_SKL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d70) 853#define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98) 854#define IS_SKL_PLUS(pci) (IS_SKL(pci) || IS_SKL_LP(pci) || IS_BXT(pci)) 855 856static int azx_freeze_noirq(struct device *dev) 857{ 858 struct pci_dev *pci = to_pci_dev(dev); 859 860 if (IS_SKL_PLUS(pci)) 861 pci_set_power_state(pci, PCI_D3hot); 862 863 return 0; 864} 865 866static int azx_thaw_noirq(struct device *dev) 867{ 868 struct pci_dev *pci = to_pci_dev(dev); 869 870 if (IS_SKL_PLUS(pci)) 871 pci_set_power_state(pci, PCI_D0); 872 873 return 0; 874} 875#endif /* CONFIG_PM_SLEEP */ 876 877#ifdef CONFIG_PM 878static int azx_runtime_suspend(struct device *dev) 879{ 880 struct snd_card *card = dev_get_drvdata(dev); 881 struct azx *chip; 882 struct hda_intel *hda; 883 884 if (!card) 885 return 0; 886 887 chip = card->private_data; 888 hda = container_of(chip, struct hda_intel, chip); 889 if (chip->disabled || hda->init_failed) 890 return 0; 891 892 if (!azx_has_pm_runtime(chip)) 893 return 0; 894 895 /* enable controller wake up event */ 896 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | 897 STATESTS_INT_MASK); 898 899 azx_stop_chip(chip); 900 azx_enter_link_reset(chip); 901 azx_clear_irq_pending(chip); 902 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 903 hda_display_power(hda, false); 904 905 return 0; 906} 907 908static int azx_runtime_resume(struct device *dev) 909{ 910 struct snd_card *card = dev_get_drvdata(dev); 911 struct azx *chip; 912 struct hda_intel *hda; 913 struct hda_bus *bus; 914 struct hda_codec *codec; 915 int status; 916 917 if (!card) 918 return 0; 919 920 chip = card->private_data; 921 hda = container_of(chip, struct hda_intel, chip); 922 if (chip->disabled || hda->init_failed) 923 return 0; 924 925 if (!azx_has_pm_runtime(chip)) 926 return 0; 927 928 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 929 hda_display_power(hda, true); 930 haswell_set_bclk(hda); 931 } 932 933 /* Read STATESTS before controller reset */ 934 status = azx_readw(chip, STATESTS); 935 936 azx_init_pci(chip); 937 azx_init_chip(chip, true); 938 939 bus = chip->bus; 940 if (status && bus) { 941 list_for_each_codec(codec, bus) 942 if (status & (1 << codec->addr)) 943 schedule_delayed_work(&codec->jackpoll_work, 944 codec->jackpoll_interval); 945 } 946 947 /* disable controller Wake Up event*/ 948 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & 949 ~STATESTS_INT_MASK); 950 951 return 0; 952} 953 954static int azx_runtime_idle(struct device *dev) 955{ 956 struct snd_card *card = dev_get_drvdata(dev); 957 struct azx *chip; 958 struct hda_intel *hda; 959 960 if (!card) 961 return 0; 962 963 chip = card->private_data; 964 hda = container_of(chip, struct hda_intel, chip); 965 if (chip->disabled || hda->init_failed) 966 return 0; 967 968 if (!power_save_controller || !azx_has_pm_runtime(chip) || 969 chip->bus->core.codec_powered) 970 return -EBUSY; 971 972 return 0; 973} 974 975static const struct dev_pm_ops azx_pm = { 976 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 977#ifdef CONFIG_PM_SLEEP 978 .freeze_noirq = azx_freeze_noirq, 979 .thaw_noirq = azx_thaw_noirq, 980#endif 981 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 982}; 983 984#define AZX_PM_OPS &azx_pm 985#else 986#define AZX_PM_OPS NULL 987#endif /* CONFIG_PM */ 988 989 990static int azx_probe_continue(struct azx *chip); 991 992#ifdef SUPPORT_VGA_SWITCHEROO 993static struct pci_dev *get_bound_vga(struct pci_dev *pci); 994 995static void azx_vs_set_state(struct pci_dev *pci, 996 enum vga_switcheroo_state state) 997{ 998 struct snd_card *card = pci_get_drvdata(pci); 999 struct azx *chip = card->private_data; 1000 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1001 bool disabled; 1002 1003 wait_for_completion(&hda->probe_wait); 1004 if (hda->init_failed) 1005 return; 1006 1007 disabled = (state == VGA_SWITCHEROO_OFF); 1008 if (chip->disabled == disabled) 1009 return; 1010 1011 if (!chip->bus) { 1012 chip->disabled = disabled; 1013 if (!disabled) { 1014 dev_info(chip->card->dev, 1015 "Start delayed initialization\n"); 1016 if (azx_probe_continue(chip) < 0) { 1017 dev_err(chip->card->dev, "initialization error\n"); 1018 hda->init_failed = true; 1019 } 1020 } 1021 } else { 1022 dev_info(chip->card->dev, "%s via VGA-switcheroo\n", 1023 disabled ? "Disabling" : "Enabling"); 1024 if (disabled) { 1025 pm_runtime_put_sync_suspend(card->dev); 1026 azx_suspend(card->dev); 1027 /* when we get suspended by vga switcheroo we end up in D3cold, 1028 * however we have no ACPI handle, so pci/acpi can't put us there, 1029 * put ourselves there */ 1030 pci->current_state = PCI_D3cold; 1031 chip->disabled = true; 1032 if (snd_hda_lock_devices(chip->bus)) 1033 dev_warn(chip->card->dev, 1034 "Cannot lock devices!\n"); 1035 } else { 1036 snd_hda_unlock_devices(chip->bus); 1037 pm_runtime_get_noresume(card->dev); 1038 chip->disabled = false; 1039 azx_resume(card->dev); 1040 } 1041 } 1042} 1043 1044static bool azx_vs_can_switch(struct pci_dev *pci) 1045{ 1046 struct snd_card *card = pci_get_drvdata(pci); 1047 struct azx *chip = card->private_data; 1048 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1049 1050 wait_for_completion(&hda->probe_wait); 1051 if (hda->init_failed) 1052 return false; 1053 if (chip->disabled || !chip->bus) 1054 return true; 1055 if (snd_hda_lock_devices(chip->bus)) 1056 return false; 1057 snd_hda_unlock_devices(chip->bus); 1058 return true; 1059} 1060 1061static void init_vga_switcheroo(struct azx *chip) 1062{ 1063 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1064 struct pci_dev *p = get_bound_vga(chip->pci); 1065 if (p) { 1066 dev_info(chip->card->dev, 1067 "Handle VGA-switcheroo audio client\n"); 1068 hda->use_vga_switcheroo = 1; 1069 pci_dev_put(p); 1070 } 1071} 1072 1073static const struct vga_switcheroo_client_ops azx_vs_ops = { 1074 .set_gpu_state = azx_vs_set_state, 1075 .can_switch = azx_vs_can_switch, 1076}; 1077 1078static int register_vga_switcheroo(struct azx *chip) 1079{ 1080 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1081 int err; 1082 1083 if (!hda->use_vga_switcheroo) 1084 return 0; 1085 /* FIXME: currently only handling DIS controller 1086 * is there any machine with two switchable HDMI audio controllers? 1087 */ 1088 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, 1089 VGA_SWITCHEROO_DIS, 1090 chip->bus != NULL); 1091 if (err < 0) 1092 return err; 1093 hda->vga_switcheroo_registered = 1; 1094 1095 /* register as an optimus hdmi audio power domain */ 1096 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev, 1097 &hda->hdmi_pm_domain); 1098 return 0; 1099} 1100#else 1101#define init_vga_switcheroo(chip) /* NOP */ 1102#define register_vga_switcheroo(chip) 0 1103#define check_hdmi_disabled(pci) false 1104#endif /* SUPPORT_VGA_SWITCHER */ 1105 1106/* 1107 * destructor 1108 */ 1109static int azx_free(struct azx *chip) 1110{ 1111 struct pci_dev *pci = chip->pci; 1112 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1113 int i; 1114 1115 if (azx_has_pm_runtime(chip) && chip->running) 1116 pm_runtime_get_noresume(&pci->dev); 1117 1118 azx_del_card_list(chip); 1119 1120 hda->init_failed = 1; /* to be sure */ 1121 complete_all(&hda->probe_wait); 1122 1123 if (use_vga_switcheroo(hda)) { 1124 if (chip->disabled && chip->bus) 1125 snd_hda_unlock_devices(chip->bus); 1126 if (hda->vga_switcheroo_registered) 1127 vga_switcheroo_unregister_client(chip->pci); 1128 } 1129 1130 if (chip->initialized) { 1131 azx_clear_irq_pending(chip); 1132 for (i = 0; i < chip->num_streams; i++) 1133 azx_stream_stop(chip, &chip->azx_dev[i]); 1134 azx_stop_chip(chip); 1135 } 1136 1137 if (chip->irq >= 0) 1138 free_irq(chip->irq, (void*)chip); 1139 if (chip->msi) 1140 pci_disable_msi(chip->pci); 1141 iounmap(chip->remap_addr); 1142 1143 azx_free_stream_pages(chip); 1144 if (chip->region_requested) 1145 pci_release_regions(chip->pci); 1146 pci_disable_device(chip->pci); 1147 kfree(chip->azx_dev); 1148#ifdef CONFIG_SND_HDA_PATCH_LOADER 1149 release_firmware(chip->fw); 1150#endif 1151 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 1152 hda_display_power(hda, false); 1153 hda_i915_exit(hda); 1154 } 1155 kfree(hda); 1156 1157 return 0; 1158} 1159 1160static int azx_dev_free(struct snd_device *device) 1161{ 1162 return azx_free(device->device_data); 1163} 1164 1165#ifdef SUPPORT_VGA_SWITCHEROO 1166/* 1167 * Check of disabled HDMI controller by vga-switcheroo 1168 */ 1169static struct pci_dev *get_bound_vga(struct pci_dev *pci) 1170{ 1171 struct pci_dev *p; 1172 1173 /* check only discrete GPU */ 1174 switch (pci->vendor) { 1175 case PCI_VENDOR_ID_ATI: 1176 case PCI_VENDOR_ID_AMD: 1177 case PCI_VENDOR_ID_NVIDIA: 1178 if (pci->devfn == 1) { 1179 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1180 pci->bus->number, 0); 1181 if (p) { 1182 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA) 1183 return p; 1184 pci_dev_put(p); 1185 } 1186 } 1187 break; 1188 } 1189 return NULL; 1190} 1191 1192static bool check_hdmi_disabled(struct pci_dev *pci) 1193{ 1194 bool vga_inactive = false; 1195 struct pci_dev *p = get_bound_vga(pci); 1196 1197 if (p) { 1198 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 1199 vga_inactive = true; 1200 pci_dev_put(p); 1201 } 1202 return vga_inactive; 1203} 1204#endif /* SUPPORT_VGA_SWITCHEROO */ 1205 1206/* 1207 * white/black-listing for position_fix 1208 */ 1209static struct snd_pci_quirk position_fix_list[] = { 1210 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1211 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1212 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 1213 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1214 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 1215 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 1216 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 1217 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 1218 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 1219 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 1220 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 1221 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 1222 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 1223 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 1224 {} 1225}; 1226 1227static int check_position_fix(struct azx *chip, int fix) 1228{ 1229 const struct snd_pci_quirk *q; 1230 1231 switch (fix) { 1232 case POS_FIX_AUTO: 1233 case POS_FIX_LPIB: 1234 case POS_FIX_POSBUF: 1235 case POS_FIX_VIACOMBO: 1236 case POS_FIX_COMBO: 1237 return fix; 1238 } 1239 1240 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1241 if (q) { 1242 dev_info(chip->card->dev, 1243 "position_fix set to %d for device %04x:%04x\n", 1244 q->value, q->subvendor, q->subdevice); 1245 return q->value; 1246 } 1247 1248 /* Check VIA/ATI HD Audio Controller exist */ 1249 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) { 1250 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); 1251 return POS_FIX_VIACOMBO; 1252 } 1253 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 1254 dev_dbg(chip->card->dev, "Using LPIB position fix\n"); 1255 return POS_FIX_LPIB; 1256 } 1257 return POS_FIX_AUTO; 1258} 1259 1260static void assign_position_fix(struct azx *chip, int fix) 1261{ 1262 static azx_get_pos_callback_t callbacks[] = { 1263 [POS_FIX_AUTO] = NULL, 1264 [POS_FIX_LPIB] = azx_get_pos_lpib, 1265 [POS_FIX_POSBUF] = azx_get_pos_posbuf, 1266 [POS_FIX_VIACOMBO] = azx_via_get_position, 1267 [POS_FIX_COMBO] = azx_get_pos_lpib, 1268 }; 1269 1270 chip->get_position[0] = chip->get_position[1] = callbacks[fix]; 1271 1272 /* combo mode uses LPIB only for playback */ 1273 if (fix == POS_FIX_COMBO) 1274 chip->get_position[1] = NULL; 1275 1276 if (fix == POS_FIX_POSBUF && 1277 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 1278 chip->get_delay[0] = chip->get_delay[1] = 1279 azx_get_delay_from_lpib; 1280 } 1281 1282} 1283 1284/* 1285 * black-lists for probe_mask 1286 */ 1287static struct snd_pci_quirk probe_mask_list[] = { 1288 /* Thinkpad often breaks the controller communication when accessing 1289 * to the non-working (or non-existing) modem codec slot. 1290 */ 1291 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1292 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1293 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1294 /* broken BIOS */ 1295 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 1296 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 1297 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 1298 /* forced codec slots */ 1299 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 1300 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 1301 /* WinFast VP200 H (Teradici) user reported broken communication */ 1302 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 1303 {} 1304}; 1305 1306#define AZX_FORCE_CODEC_MASK 0x100 1307 1308static void check_probe_mask(struct azx *chip, int dev) 1309{ 1310 const struct snd_pci_quirk *q; 1311 1312 chip->codec_probe_mask = probe_mask[dev]; 1313 if (chip->codec_probe_mask == -1) { 1314 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1315 if (q) { 1316 dev_info(chip->card->dev, 1317 "probe_mask set to 0x%x for device %04x:%04x\n", 1318 q->value, q->subvendor, q->subdevice); 1319 chip->codec_probe_mask = q->value; 1320 } 1321 } 1322 1323 /* check forced option */ 1324 if (chip->codec_probe_mask != -1 && 1325 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 1326 chip->codec_mask = chip->codec_probe_mask & 0xff; 1327 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", 1328 chip->codec_mask); 1329 } 1330} 1331 1332/* 1333 * white/black-list for enable_msi 1334 */ 1335static struct snd_pci_quirk msi_black_list[] = { 1336 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 1337 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 1338 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 1339 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 1340 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 1341 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 1342 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 1343 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 1344 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 1345 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 1346 {} 1347}; 1348 1349static void check_msi(struct azx *chip) 1350{ 1351 const struct snd_pci_quirk *q; 1352 1353 if (enable_msi >= 0) { 1354 chip->msi = !!enable_msi; 1355 return; 1356 } 1357 chip->msi = 1; /* enable MSI as default */ 1358 q = snd_pci_quirk_lookup(chip->pci, msi_black_list); 1359 if (q) { 1360 dev_info(chip->card->dev, 1361 "msi for device %04x:%04x set to %d\n", 1362 q->subvendor, q->subdevice, q->value); 1363 chip->msi = q->value; 1364 return; 1365 } 1366 1367 /* NVidia chipsets seem to cause troubles with MSI */ 1368 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 1369 dev_info(chip->card->dev, "Disabling MSI\n"); 1370 chip->msi = 0; 1371 } 1372} 1373 1374/* check the snoop mode availability */ 1375static void azx_check_snoop_available(struct azx *chip) 1376{ 1377 int snoop = hda_snoop; 1378 1379 if (snoop >= 0) { 1380 dev_info(chip->card->dev, "Force to %s mode by module option\n", 1381 snoop ? "snoop" : "non-snoop"); 1382 chip->snoop = snoop; 1383 return; 1384 } 1385 1386 snoop = true; 1387 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && 1388 chip->driver_type == AZX_DRIVER_VIA) { 1389 /* force to non-snoop mode for a new VIA controller 1390 * when BIOS is set 1391 */ 1392 u8 val; 1393 pci_read_config_byte(chip->pci, 0x42, &val); 1394 if (!(val & 0x80) && chip->pci->revision == 0x30) 1395 snoop = false; 1396 } 1397 1398 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) 1399 snoop = false; 1400 1401 chip->snoop = snoop; 1402 if (!snoop) 1403 dev_info(chip->card->dev, "Force to non-snoop mode\n"); 1404} 1405 1406static void azx_probe_work(struct work_struct *work) 1407{ 1408 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work); 1409 azx_probe_continue(&hda->chip); 1410} 1411 1412/* 1413 * constructor 1414 */ 1415static int azx_create(struct snd_card *card, struct pci_dev *pci, 1416 int dev, unsigned int driver_caps, 1417 const struct hda_controller_ops *hda_ops, 1418 struct azx **rchip) 1419{ 1420 static struct snd_device_ops ops = { 1421 .dev_free = azx_dev_free, 1422 }; 1423 struct hda_intel *hda; 1424 struct azx *chip; 1425 int err; 1426 1427 *rchip = NULL; 1428 1429 err = pci_enable_device(pci); 1430 if (err < 0) 1431 return err; 1432 1433 hda = kzalloc(sizeof(*hda), GFP_KERNEL); 1434 if (!hda) { 1435 pci_disable_device(pci); 1436 return -ENOMEM; 1437 } 1438 1439 chip = &hda->chip; 1440 spin_lock_init(&chip->reg_lock); 1441 mutex_init(&chip->open_mutex); 1442 chip->card = card; 1443 chip->pci = pci; 1444 chip->ops = hda_ops; 1445 chip->irq = -1; 1446 chip->driver_caps = driver_caps; 1447 chip->driver_type = driver_caps & 0xff; 1448 check_msi(chip); 1449 chip->dev_index = dev; 1450 chip->jackpoll_ms = jackpoll_ms; 1451 INIT_LIST_HEAD(&chip->pcm_list); 1452 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); 1453 INIT_LIST_HEAD(&hda->list); 1454 init_vga_switcheroo(chip); 1455 init_completion(&hda->probe_wait); 1456 1457 assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); 1458 1459 check_probe_mask(chip, dev); 1460 1461 chip->single_cmd = single_cmd; 1462 azx_check_snoop_available(chip); 1463 1464 if (bdl_pos_adj[dev] < 0) { 1465 switch (chip->driver_type) { 1466 case AZX_DRIVER_ICH: 1467 case AZX_DRIVER_PCH: 1468 bdl_pos_adj[dev] = 1; 1469 break; 1470 default: 1471 bdl_pos_adj[dev] = 32; 1472 break; 1473 } 1474 } 1475 chip->bdl_pos_adj = bdl_pos_adj; 1476 1477 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1478 if (err < 0) { 1479 dev_err(card->dev, "Error creating device [card]!\n"); 1480 azx_free(chip); 1481 return err; 1482 } 1483 1484 /* continue probing in work context as may trigger request module */ 1485 INIT_WORK(&hda->probe_work, azx_probe_work); 1486 1487 *rchip = chip; 1488 1489 return 0; 1490} 1491 1492static int azx_first_init(struct azx *chip) 1493{ 1494 int dev = chip->dev_index; 1495 struct pci_dev *pci = chip->pci; 1496 struct snd_card *card = chip->card; 1497 int err; 1498 unsigned short gcap; 1499 unsigned int dma_bits = 64; 1500 1501#if BITS_PER_LONG != 64 1502 /* Fix up base address on ULI M5461 */ 1503 if (chip->driver_type == AZX_DRIVER_ULI) { 1504 u16 tmp3; 1505 pci_read_config_word(pci, 0x40, &tmp3); 1506 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1507 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1508 } 1509#endif 1510 1511 err = pci_request_regions(pci, "ICH HD audio"); 1512 if (err < 0) 1513 return err; 1514 chip->region_requested = 1; 1515 1516 chip->addr = pci_resource_start(pci, 0); 1517 chip->remap_addr = pci_ioremap_bar(pci, 0); 1518 if (chip->remap_addr == NULL) { 1519 dev_err(card->dev, "ioremap error\n"); 1520 return -ENXIO; 1521 } 1522 1523 if (chip->msi) { 1524 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) { 1525 dev_dbg(card->dev, "Disabling 64bit MSI\n"); 1526 pci->no_64bit_msi = true; 1527 } 1528 if (pci_enable_msi(pci) < 0) 1529 chip->msi = 0; 1530 } 1531 1532 if (azx_acquire_irq(chip, 0) < 0) 1533 return -EBUSY; 1534 1535 pci_set_master(pci); 1536 synchronize_irq(chip->irq); 1537 1538 gcap = azx_readw(chip, GCAP); 1539 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 1540 1541 /* AMD devices support 40 or 48bit DMA, take the safe one */ 1542 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 1543 dma_bits = 40; 1544 1545 /* disable SB600 64bit support for safety */ 1546 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1547 struct pci_dev *p_smbus; 1548 dma_bits = 40; 1549 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 1550 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1551 NULL); 1552 if (p_smbus) { 1553 if (p_smbus->revision < 0x30) 1554 gcap &= ~AZX_GCAP_64OK; 1555 pci_dev_put(p_smbus); 1556 } 1557 } 1558 1559 /* disable 64bit DMA address on some devices */ 1560 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1561 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1562 gcap &= ~AZX_GCAP_64OK; 1563 } 1564 1565 /* disable buffer size rounding to 128-byte multiples if supported */ 1566 if (align_buffer_size >= 0) 1567 chip->align_buffer_size = !!align_buffer_size; 1568 else { 1569 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) 1570 chip->align_buffer_size = 0; 1571 else 1572 chip->align_buffer_size = 1; 1573 } 1574 1575 /* allow 64bit DMA address if supported by H/W */ 1576 if (!(gcap & AZX_GCAP_64OK)) 1577 dma_bits = 32; 1578 if (!pci_set_dma_mask(pci, DMA_BIT_MASK(dma_bits))) { 1579 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(dma_bits)); 1580 } else { 1581 pci_set_dma_mask(pci, DMA_BIT_MASK(32)); 1582 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32)); 1583 } 1584 1585 /* read number of streams from GCAP register instead of using 1586 * hardcoded value 1587 */ 1588 chip->capture_streams = (gcap >> 8) & 0x0f; 1589 chip->playback_streams = (gcap >> 12) & 0x0f; 1590 if (!chip->playback_streams && !chip->capture_streams) { 1591 /* gcap didn't give any info, switching to old method */ 1592 1593 switch (chip->driver_type) { 1594 case AZX_DRIVER_ULI: 1595 chip->playback_streams = ULI_NUM_PLAYBACK; 1596 chip->capture_streams = ULI_NUM_CAPTURE; 1597 break; 1598 case AZX_DRIVER_ATIHDMI: 1599 case AZX_DRIVER_ATIHDMI_NS: 1600 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 1601 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 1602 break; 1603 case AZX_DRIVER_GENERIC: 1604 default: 1605 chip->playback_streams = ICH6_NUM_PLAYBACK; 1606 chip->capture_streams = ICH6_NUM_CAPTURE; 1607 break; 1608 } 1609 } 1610 chip->capture_index_offset = 0; 1611 chip->playback_index_offset = chip->capture_streams; 1612 chip->num_streams = chip->playback_streams + chip->capture_streams; 1613 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev), 1614 GFP_KERNEL); 1615 if (!chip->azx_dev) 1616 return -ENOMEM; 1617 1618 err = azx_alloc_stream_pages(chip); 1619 if (err < 0) 1620 return err; 1621 1622 /* initialize streams */ 1623 azx_init_stream(chip); 1624 1625 /* initialize chip */ 1626 azx_init_pci(chip); 1627 1628 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 1629 struct hda_intel *hda; 1630 1631 hda = container_of(chip, struct hda_intel, chip); 1632 haswell_set_bclk(hda); 1633 } 1634 1635 azx_init_chip(chip, (probe_only[dev] & 2) == 0); 1636 1637 /* codec detection */ 1638 if (!chip->codec_mask) { 1639 dev_err(card->dev, "no codecs found!\n"); 1640 return -ENODEV; 1641 } 1642 1643 strcpy(card->driver, "HDA-Intel"); 1644 strlcpy(card->shortname, driver_short_names[chip->driver_type], 1645 sizeof(card->shortname)); 1646 snprintf(card->longname, sizeof(card->longname), 1647 "%s at 0x%lx irq %i", 1648 card->shortname, chip->addr, chip->irq); 1649 1650 return 0; 1651} 1652 1653#ifdef CONFIG_SND_HDA_PATCH_LOADER 1654/* callback from request_firmware_nowait() */ 1655static void azx_firmware_cb(const struct firmware *fw, void *context) 1656{ 1657 struct snd_card *card = context; 1658 struct azx *chip = card->private_data; 1659 struct pci_dev *pci = chip->pci; 1660 1661 if (!fw) { 1662 dev_err(card->dev, "Cannot load firmware, aborting\n"); 1663 goto error; 1664 } 1665 1666 chip->fw = fw; 1667 if (!chip->disabled) { 1668 /* continue probing */ 1669 if (azx_probe_continue(chip)) 1670 goto error; 1671 } 1672 return; /* OK */ 1673 1674 error: 1675 snd_card_free(card); 1676 pci_set_drvdata(pci, NULL); 1677} 1678#endif 1679 1680/* 1681 * HDA controller ops. 1682 */ 1683 1684/* PCI register access. */ 1685static void pci_azx_writel(u32 value, u32 __iomem *addr) 1686{ 1687 writel(value, addr); 1688} 1689 1690static u32 pci_azx_readl(u32 __iomem *addr) 1691{ 1692 return readl(addr); 1693} 1694 1695static void pci_azx_writew(u16 value, u16 __iomem *addr) 1696{ 1697 writew(value, addr); 1698} 1699 1700static u16 pci_azx_readw(u16 __iomem *addr) 1701{ 1702 return readw(addr); 1703} 1704 1705static void pci_azx_writeb(u8 value, u8 __iomem *addr) 1706{ 1707 writeb(value, addr); 1708} 1709 1710static u8 pci_azx_readb(u8 __iomem *addr) 1711{ 1712 return readb(addr); 1713} 1714 1715static int disable_msi_reset_irq(struct azx *chip) 1716{ 1717 int err; 1718 1719 free_irq(chip->irq, chip); 1720 chip->irq = -1; 1721 pci_disable_msi(chip->pci); 1722 chip->msi = 0; 1723 err = azx_acquire_irq(chip, 1); 1724 if (err < 0) 1725 return err; 1726 1727 return 0; 1728} 1729 1730/* DMA page allocation helpers. */ 1731static int dma_alloc_pages(struct azx *chip, 1732 int type, 1733 size_t size, 1734 struct snd_dma_buffer *buf) 1735{ 1736 int err; 1737 1738 err = snd_dma_alloc_pages(type, 1739 chip->card->dev, 1740 size, buf); 1741 if (err < 0) 1742 return err; 1743 mark_pages_wc(chip, buf, true); 1744 return 0; 1745} 1746 1747static void dma_free_pages(struct azx *chip, struct snd_dma_buffer *buf) 1748{ 1749 mark_pages_wc(chip, buf, false); 1750 snd_dma_free_pages(buf); 1751} 1752 1753static int substream_alloc_pages(struct azx *chip, 1754 struct snd_pcm_substream *substream, 1755 size_t size) 1756{ 1757 struct azx_dev *azx_dev = get_azx_dev(substream); 1758 int ret; 1759 1760 mark_runtime_wc(chip, azx_dev, substream, false); 1761 azx_dev->bufsize = 0; 1762 azx_dev->period_bytes = 0; 1763 azx_dev->format_val = 0; 1764 ret = snd_pcm_lib_malloc_pages(substream, size); 1765 if (ret < 0) 1766 return ret; 1767 mark_runtime_wc(chip, azx_dev, substream, true); 1768 return 0; 1769} 1770 1771static int substream_free_pages(struct azx *chip, 1772 struct snd_pcm_substream *substream) 1773{ 1774 struct azx_dev *azx_dev = get_azx_dev(substream); 1775 mark_runtime_wc(chip, azx_dev, substream, false); 1776 return snd_pcm_lib_free_pages(substream); 1777} 1778 1779static void pcm_mmap_prepare(struct snd_pcm_substream *substream, 1780 struct vm_area_struct *area) 1781{ 1782#ifdef CONFIG_X86 1783 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1784 struct azx *chip = apcm->chip; 1785 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA) 1786 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot); 1787#endif 1788} 1789 1790static const struct hda_controller_ops pci_hda_ops = { 1791 .reg_writel = pci_azx_writel, 1792 .reg_readl = pci_azx_readl, 1793 .reg_writew = pci_azx_writew, 1794 .reg_readw = pci_azx_readw, 1795 .reg_writeb = pci_azx_writeb, 1796 .reg_readb = pci_azx_readb, 1797 .disable_msi_reset_irq = disable_msi_reset_irq, 1798 .dma_alloc_pages = dma_alloc_pages, 1799 .dma_free_pages = dma_free_pages, 1800 .substream_alloc_pages = substream_alloc_pages, 1801 .substream_free_pages = substream_free_pages, 1802 .pcm_mmap_prepare = pcm_mmap_prepare, 1803 .position_check = azx_position_check, 1804}; 1805 1806static int azx_probe(struct pci_dev *pci, 1807 const struct pci_device_id *pci_id) 1808{ 1809 static int dev; 1810 struct snd_card *card; 1811 struct hda_intel *hda; 1812 struct azx *chip; 1813 bool schedule_probe; 1814 int err; 1815 1816 if (dev >= SNDRV_CARDS) 1817 return -ENODEV; 1818 if (!enable[dev]) { 1819 dev++; 1820 return -ENOENT; 1821 } 1822 1823 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 1824 0, &card); 1825 if (err < 0) { 1826 dev_err(&pci->dev, "Error creating card!\n"); 1827 return err; 1828 } 1829 1830 err = azx_create(card, pci, dev, pci_id->driver_data, 1831 &pci_hda_ops, &chip); 1832 if (err < 0) 1833 goto out_free; 1834 card->private_data = chip; 1835 hda = container_of(chip, struct hda_intel, chip); 1836 1837 pci_set_drvdata(pci, card); 1838 1839 err = register_vga_switcheroo(chip); 1840 if (err < 0) { 1841 dev_err(card->dev, "Error registering VGA-switcheroo client\n"); 1842 goto out_free; 1843 } 1844 1845 if (check_hdmi_disabled(pci)) { 1846 dev_info(card->dev, "VGA controller is disabled\n"); 1847 dev_info(card->dev, "Delaying initialization\n"); 1848 chip->disabled = true; 1849 } 1850 1851 schedule_probe = !chip->disabled; 1852 1853#ifdef CONFIG_SND_HDA_PATCH_LOADER 1854 if (patch[dev] && *patch[dev]) { 1855 dev_info(card->dev, "Applying patch firmware '%s'\n", 1856 patch[dev]); 1857 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 1858 &pci->dev, GFP_KERNEL, card, 1859 azx_firmware_cb); 1860 if (err < 0) 1861 goto out_free; 1862 schedule_probe = false; /* continued in azx_firmware_cb() */ 1863 } 1864#endif /* CONFIG_SND_HDA_PATCH_LOADER */ 1865 1866#ifndef CONFIG_SND_HDA_I915 1867 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 1868 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n"); 1869#endif 1870 1871 if (schedule_probe) 1872 schedule_work(&hda->probe_work); 1873 1874 dev++; 1875 if (chip->disabled) 1876 complete_all(&hda->probe_wait); 1877 return 0; 1878 1879out_free: 1880 snd_card_free(card); 1881 return err; 1882} 1883 1884/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 1885static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 1886 [AZX_DRIVER_NVIDIA] = 8, 1887 [AZX_DRIVER_TERA] = 1, 1888}; 1889 1890static int azx_probe_continue(struct azx *chip) 1891{ 1892 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1893 struct pci_dev *pci = chip->pci; 1894 int dev = chip->dev_index; 1895 int err; 1896 1897 /* Request power well for Haswell HDA controller and codec */ 1898 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 1899#ifdef CONFIG_SND_HDA_I915 1900 err = hda_i915_init(hda); 1901 if (err < 0) { 1902 /* if the controller is bound only with HDMI/DP 1903 * (for HSW and BDW), we need to abort the probe; 1904 * for other chips, still continue probing as other 1905 * codecs can be on the same link. 1906 */ 1907 if (CONTROLLER_IN_GPU(pci)) 1908 goto out_free; 1909 else 1910 goto skip_i915; 1911 } 1912 err = hda_display_power(hda, true); 1913 if (err < 0) { 1914 dev_err(chip->card->dev, 1915 "Cannot turn on display power on i915\n"); 1916 goto out_free; 1917 } 1918#endif 1919 } 1920 1921#ifdef CONFIG_SND_HDA_I915 1922 skip_i915: 1923#endif 1924 err = azx_first_init(chip); 1925 if (err < 0) 1926 goto out_free; 1927 1928#ifdef CONFIG_SND_HDA_INPUT_BEEP 1929 chip->beep_mode = beep_mode[dev]; 1930#endif 1931 1932 /* create codec instances */ 1933 err = azx_bus_create(chip, model[dev]); 1934 if (err < 0) 1935 goto out_free; 1936 1937 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); 1938 if (err < 0) 1939 goto out_free; 1940 1941#ifdef CONFIG_SND_HDA_PATCH_LOADER 1942 if (chip->fw) { 1943 err = snd_hda_load_patch(chip->bus, chip->fw->size, 1944 chip->fw->data); 1945 if (err < 0) 1946 goto out_free; 1947#ifndef CONFIG_PM 1948 release_firmware(chip->fw); /* no longer needed */ 1949 chip->fw = NULL; 1950#endif 1951 } 1952#endif 1953 if ((probe_only[dev] & 1) == 0) { 1954 err = azx_codec_configure(chip); 1955 if (err < 0) 1956 goto out_free; 1957 } 1958 1959 err = snd_card_register(chip->card); 1960 if (err < 0) 1961 goto out_free; 1962 1963 chip->running = 1; 1964 azx_add_card_list(chip); 1965 snd_hda_set_power_save(chip->bus, power_save * 1000); 1966 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo) 1967 pm_runtime_put_noidle(&pci->dev); 1968 1969out_free: 1970 if (err < 0) 1971 hda->init_failed = 1; 1972 complete_all(&hda->probe_wait); 1973 return err; 1974} 1975 1976static void azx_remove(struct pci_dev *pci) 1977{ 1978 struct snd_card *card = pci_get_drvdata(pci); 1979 struct azx *chip; 1980 struct hda_intel *hda; 1981 1982 if (card) { 1983 /* cancel the pending probing work */ 1984 chip = card->private_data; 1985 hda = container_of(chip, struct hda_intel, chip); 1986 cancel_work_sync(&hda->probe_work); 1987 1988 snd_card_free(card); 1989 } 1990} 1991 1992static void azx_shutdown(struct pci_dev *pci) 1993{ 1994 struct snd_card *card = pci_get_drvdata(pci); 1995 struct azx *chip; 1996 1997 if (!card) 1998 return; 1999 chip = card->private_data; 2000 if (chip && chip->running) 2001 azx_stop_chip(chip); 2002} 2003 2004/* PCI IDs */ 2005static const struct pci_device_id azx_ids[] = { 2006 /* CPT */ 2007 { PCI_DEVICE(0x8086, 0x1c20), 2008 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2009 /* PBG */ 2010 { PCI_DEVICE(0x8086, 0x1d20), 2011 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2012 /* Panther Point */ 2013 { PCI_DEVICE(0x8086, 0x1e20), 2014 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2015 /* Lynx Point */ 2016 { PCI_DEVICE(0x8086, 0x8c20), 2017 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2018 /* 9 Series */ 2019 { PCI_DEVICE(0x8086, 0x8ca0), 2020 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2021 /* Wellsburg */ 2022 { PCI_DEVICE(0x8086, 0x8d20), 2023 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2024 { PCI_DEVICE(0x8086, 0x8d21), 2025 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2026 /* Lewisburg */ 2027 { PCI_DEVICE(0x8086, 0xa1f0), 2028 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2029 { PCI_DEVICE(0x8086, 0xa270), 2030 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2031 /* Lynx Point-LP */ 2032 { PCI_DEVICE(0x8086, 0x9c20), 2033 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2034 /* Lynx Point-LP */ 2035 { PCI_DEVICE(0x8086, 0x9c21), 2036 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2037 /* Wildcat Point-LP */ 2038 { PCI_DEVICE(0x8086, 0x9ca0), 2039 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2040 /* Sunrise Point */ 2041 { PCI_DEVICE(0x8086, 0xa170), 2042 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2043 /* Sunrise Point-LP */ 2044 { PCI_DEVICE(0x8086, 0x9d70), 2045 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2046 /* Broxton-P(Apollolake) */ 2047 { PCI_DEVICE(0x8086, 0x5a98), 2048 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON }, 2049 /* Broxton-T */ 2050 { PCI_DEVICE(0x8086, 0x1a98), 2051 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON }, 2052 /* Haswell */ 2053 { PCI_DEVICE(0x8086, 0x0a0c), 2054 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2055 { PCI_DEVICE(0x8086, 0x0c0c), 2056 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2057 { PCI_DEVICE(0x8086, 0x0d0c), 2058 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2059 /* Broadwell */ 2060 { PCI_DEVICE(0x8086, 0x160c), 2061 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL }, 2062 /* 5 Series/3400 */ 2063 { PCI_DEVICE(0x8086, 0x3b56), 2064 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2065 /* Poulsbo */ 2066 { PCI_DEVICE(0x8086, 0x811b), 2067 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2068 /* Oaktrail */ 2069 { PCI_DEVICE(0x8086, 0x080a), 2070 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2071 /* BayTrail */ 2072 { PCI_DEVICE(0x8086, 0x0f04), 2073 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL }, 2074 /* Braswell */ 2075 { PCI_DEVICE(0x8086, 0x2284), 2076 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL }, 2077 /* ICH6 */ 2078 { PCI_DEVICE(0x8086, 0x2668), 2079 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2080 /* ICH7 */ 2081 { PCI_DEVICE(0x8086, 0x27d8), 2082 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2083 /* ESB2 */ 2084 { PCI_DEVICE(0x8086, 0x269a), 2085 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2086 /* ICH8 */ 2087 { PCI_DEVICE(0x8086, 0x284b), 2088 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2089 /* ICH9 */ 2090 { PCI_DEVICE(0x8086, 0x293e), 2091 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2092 /* ICH9 */ 2093 { PCI_DEVICE(0x8086, 0x293f), 2094 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2095 /* ICH10 */ 2096 { PCI_DEVICE(0x8086, 0x3a3e), 2097 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2098 /* ICH10 */ 2099 { PCI_DEVICE(0x8086, 0x3a6e), 2100 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2101 /* Generic Intel */ 2102 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2103 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2104 .class_mask = 0xffffff, 2105 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, 2106 /* ATI SB 450/600/700/800/900 */ 2107 { PCI_DEVICE(0x1002, 0x437b), 2108 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2109 { PCI_DEVICE(0x1002, 0x4383), 2110 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2111 /* AMD Hudson */ 2112 { PCI_DEVICE(0x1022, 0x780d), 2113 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 2114 /* ATI HDMI */ 2115 { PCI_DEVICE(0x1002, 0x1308), 2116 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2117 { PCI_DEVICE(0x1002, 0x157a), 2118 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2119 { PCI_DEVICE(0x1002, 0x793b), 2120 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2121 { PCI_DEVICE(0x1002, 0x7919), 2122 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2123 { PCI_DEVICE(0x1002, 0x960f), 2124 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2125 { PCI_DEVICE(0x1002, 0x970f), 2126 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2127 { PCI_DEVICE(0x1002, 0x9840), 2128 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2129 { PCI_DEVICE(0x1002, 0xaa00), 2130 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2131 { PCI_DEVICE(0x1002, 0xaa08), 2132 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2133 { PCI_DEVICE(0x1002, 0xaa10), 2134 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2135 { PCI_DEVICE(0x1002, 0xaa18), 2136 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2137 { PCI_DEVICE(0x1002, 0xaa20), 2138 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2139 { PCI_DEVICE(0x1002, 0xaa28), 2140 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2141 { PCI_DEVICE(0x1002, 0xaa30), 2142 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2143 { PCI_DEVICE(0x1002, 0xaa38), 2144 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2145 { PCI_DEVICE(0x1002, 0xaa40), 2146 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2147 { PCI_DEVICE(0x1002, 0xaa48), 2148 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2149 { PCI_DEVICE(0x1002, 0xaa50), 2150 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2151 { PCI_DEVICE(0x1002, 0xaa58), 2152 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2153 { PCI_DEVICE(0x1002, 0xaa60), 2154 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2155 { PCI_DEVICE(0x1002, 0xaa68), 2156 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2157 { PCI_DEVICE(0x1002, 0xaa80), 2158 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2159 { PCI_DEVICE(0x1002, 0xaa88), 2160 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2161 { PCI_DEVICE(0x1002, 0xaa90), 2162 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2163 { PCI_DEVICE(0x1002, 0xaa98), 2164 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2165 { PCI_DEVICE(0x1002, 0x9902), 2166 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2167 { PCI_DEVICE(0x1002, 0xaaa0), 2168 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2169 { PCI_DEVICE(0x1002, 0xaaa8), 2170 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2171 { PCI_DEVICE(0x1002, 0xaab0), 2172 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2173 { PCI_DEVICE(0x1002, 0xaac0), 2174 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2175 { PCI_DEVICE(0x1002, 0xaac8), 2176 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2177 { PCI_DEVICE(0x1002, 0xaad8), 2178 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2179 { PCI_DEVICE(0x1002, 0xaae8), 2180 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2181 /* VIA VT8251/VT8237A */ 2182 { PCI_DEVICE(0x1106, 0x3288), 2183 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA }, 2184 /* VIA GFX VT7122/VX900 */ 2185 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 2186 /* VIA GFX VT6122/VX11 */ 2187 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 2188 /* SIS966 */ 2189 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2190 /* ULI M5461 */ 2191 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2192 /* NVIDIA MCP */ 2193 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2194 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2195 .class_mask = 0xffffff, 2196 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 2197 /* Teradici */ 2198 { PCI_DEVICE(0x6549, 0x1200), 2199 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2200 { PCI_DEVICE(0x6549, 0x2200), 2201 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2202 /* Creative X-Fi (CA0110-IBG) */ 2203 /* CTHDA chips */ 2204 { PCI_DEVICE(0x1102, 0x0010), 2205 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2206 { PCI_DEVICE(0x1102, 0x0012), 2207 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2208#if !IS_ENABLED(CONFIG_SND_CTXFI) 2209 /* the following entry conflicts with snd-ctxfi driver, 2210 * as ctxfi driver mutates from HD-audio to native mode with 2211 * a special command sequence. 2212 */ 2213 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2214 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2215 .class_mask = 0xffffff, 2216 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2217 AZX_DCAPS_NO_64BIT | 2218 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB }, 2219#else 2220 /* this entry seems still valid -- i.e. without emu20kx chip */ 2221 { PCI_DEVICE(0x1102, 0x0009), 2222 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2223 AZX_DCAPS_NO_64BIT | 2224 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB }, 2225#endif 2226 /* CM8888 */ 2227 { PCI_DEVICE(0x13f6, 0x5011), 2228 .driver_data = AZX_DRIVER_CMEDIA | 2229 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, 2230 /* Vortex86MX */ 2231 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2232 /* VMware HDAudio */ 2233 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2234 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2235 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2236 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2237 .class_mask = 0xffffff, 2238 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2239 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2240 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2241 .class_mask = 0xffffff, 2242 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2243 { 0, } 2244}; 2245MODULE_DEVICE_TABLE(pci, azx_ids); 2246 2247/* pci_driver definition */ 2248static struct pci_driver azx_driver = { 2249 .name = KBUILD_MODNAME, 2250 .id_table = azx_ids, 2251 .probe = azx_probe, 2252 .remove = azx_remove, 2253 .shutdown = azx_shutdown, 2254 .driver = { 2255 .pm = AZX_PM_OPS, 2256 }, 2257}; 2258 2259module_pci_driver(azx_driver); 2260