1/*
2 * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef _UAPI_TEGRA_DRM_H_
24#define _UAPI_TEGRA_DRM_H_
25
26#include <drm/drm.h>
27
28#define DRM_TEGRA_GEM_CREATE_TILED     (1 << 0)
29#define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
30
31struct drm_tegra_gem_create {
32	__u64 size;
33	__u32 flags;
34	__u32 handle;
35};
36
37struct drm_tegra_gem_mmap {
38	__u32 handle;
39	__u32 pad;
40	__u64 offset;
41};
42
43struct drm_tegra_syncpt_read {
44	__u32 id;
45	__u32 value;
46};
47
48struct drm_tegra_syncpt_incr {
49	__u32 id;
50	__u32 pad;
51};
52
53struct drm_tegra_syncpt_wait {
54	__u32 id;
55	__u32 thresh;
56	__u32 timeout;
57	__u32 value;
58};
59
60#define DRM_TEGRA_NO_TIMEOUT	(0xffffffff)
61
62struct drm_tegra_open_channel {
63	__u32 client;
64	__u32 pad;
65	__u64 context;
66};
67
68struct drm_tegra_close_channel {
69	__u64 context;
70};
71
72struct drm_tegra_get_syncpt {
73	__u64 context;
74	__u32 index;
75	__u32 id;
76};
77
78struct drm_tegra_get_syncpt_base {
79	__u64 context;
80	__u32 syncpt;
81	__u32 id;
82};
83
84struct drm_tegra_syncpt {
85	__u32 id;
86	__u32 incrs;
87};
88
89struct drm_tegra_cmdbuf {
90	__u32 handle;
91	__u32 offset;
92	__u32 words;
93	__u32 pad;
94};
95
96struct drm_tegra_reloc {
97	struct {
98		__u32 handle;
99		__u32 offset;
100	} cmdbuf;
101	struct {
102		__u32 handle;
103		__u32 offset;
104	} target;
105	__u32 shift;
106	__u32 pad;
107};
108
109struct drm_tegra_waitchk {
110	__u32 handle;
111	__u32 offset;
112	__u32 syncpt;
113	__u32 thresh;
114};
115
116struct drm_tegra_submit {
117	__u64 context;
118	__u32 num_syncpts;
119	__u32 num_cmdbufs;
120	__u32 num_relocs;
121	__u32 num_waitchks;
122	__u32 waitchk_mask;
123	__u32 timeout;
124	__u64 syncpts;
125	__u64 cmdbufs;
126	__u64 relocs;
127	__u64 waitchks;
128	__u32 fence;		/* Return value */
129
130	__u32 reserved[5];	/* future expansion */
131};
132
133#define DRM_TEGRA_GEM_TILING_MODE_PITCH 0
134#define DRM_TEGRA_GEM_TILING_MODE_TILED 1
135#define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2
136
137struct drm_tegra_gem_set_tiling {
138	/* input */
139	__u32 handle;
140	__u32 mode;
141	__u32 value;
142	__u32 pad;
143};
144
145struct drm_tegra_gem_get_tiling {
146	/* input */
147	__u32 handle;
148	/* output */
149	__u32 mode;
150	__u32 value;
151	__u32 pad;
152};
153
154#define DRM_TEGRA_GEM_BOTTOM_UP		(1 << 0)
155#define DRM_TEGRA_GEM_FLAGS		(DRM_TEGRA_GEM_BOTTOM_UP)
156
157struct drm_tegra_gem_set_flags {
158	/* input */
159	__u32 handle;
160	/* output */
161	__u32 flags;
162};
163
164struct drm_tegra_gem_get_flags {
165	/* input */
166	__u32 handle;
167	/* output */
168	__u32 flags;
169};
170
171#define DRM_TEGRA_GEM_CREATE		0x00
172#define DRM_TEGRA_GEM_MMAP		0x01
173#define DRM_TEGRA_SYNCPT_READ		0x02
174#define DRM_TEGRA_SYNCPT_INCR		0x03
175#define DRM_TEGRA_SYNCPT_WAIT		0x04
176#define DRM_TEGRA_OPEN_CHANNEL		0x05
177#define DRM_TEGRA_CLOSE_CHANNEL		0x06
178#define DRM_TEGRA_GET_SYNCPT		0x07
179#define DRM_TEGRA_SUBMIT		0x08
180#define DRM_TEGRA_GET_SYNCPT_BASE	0x09
181#define DRM_TEGRA_GEM_SET_TILING	0x0a
182#define DRM_TEGRA_GEM_GET_TILING	0x0b
183#define DRM_TEGRA_GEM_SET_FLAGS		0x0c
184#define DRM_TEGRA_GEM_GET_FLAGS		0x0d
185
186#define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create)
187#define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap)
188#define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read)
189#define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr)
190#define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait)
191#define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel)
192#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_open_channel)
193#define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt)
194#define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit)
195#define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base)
196#define DRM_IOCTL_TEGRA_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_TILING, struct drm_tegra_gem_set_tiling)
197#define DRM_IOCTL_TEGRA_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_TILING, struct drm_tegra_gem_get_tiling)
198#define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags)
199#define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags)
200
201#endif
202