1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program.  If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __MSM_DRM_H__
19#define __MSM_DRM_H__
20
21#include <stddef.h>
22#include <drm/drm.h>
23
24/* Please note that modifications to all structs defined here are
25 * subject to backwards-compatibility constraints:
26 *  1) Do not use pointers, use uint64_t instead for 32 bit / 64 bit
27 *     user/kernel compatibility
28 *  2) Keep fields aligned to their size
29 *  3) Because of how drm_ioctl() works, we can add new fields at
30 *     the end of an ioctl if some care is taken: drm_ioctl() will
31 *     zero out the new fields at the tail of the ioctl, so a zero
32 *     value should have a backwards compatible meaning.  And for
33 *     output params, userspace won't see the newly added output
34 *     fields.. so that has to be somehow ok.
35 */
36
37#define MSM_PIPE_NONE        0x00
38#define MSM_PIPE_2D0         0x01
39#define MSM_PIPE_2D1         0x02
40#define MSM_PIPE_3D0         0x10
41
42/* timeouts are specified in clock-monotonic absolute times (to simplify
43 * restarting interrupted ioctls).  The following struct is logically the
44 * same as 'struct timespec' but 32/64b ABI safe.
45 */
46struct drm_msm_timespec {
47	int64_t tv_sec;          /* seconds */
48	int64_t tv_nsec;         /* nanoseconds */
49};
50
51#define MSM_PARAM_GPU_ID     0x01
52#define MSM_PARAM_GMEM_SIZE  0x02
53#define MSM_PARAM_CHIP_ID    0x03
54
55struct drm_msm_param {
56	uint32_t pipe;           /* in, MSM_PIPE_x */
57	uint32_t param;          /* in, MSM_PARAM_x */
58	uint64_t value;          /* out (get_param) or in (set_param) */
59};
60
61/*
62 * GEM buffers:
63 */
64
65#define MSM_BO_SCANOUT       0x00000001     /* scanout capable */
66#define MSM_BO_GPU_READONLY  0x00000002
67#define MSM_BO_CACHE_MASK    0x000f0000
68/* cache modes */
69#define MSM_BO_CACHED        0x00010000
70#define MSM_BO_WC            0x00020000
71#define MSM_BO_UNCACHED      0x00040000
72
73#define MSM_BO_FLAGS         (MSM_BO_SCANOUT | \
74                              MSM_BO_GPU_READONLY | \
75                              MSM_BO_CACHED | \
76                              MSM_BO_WC | \
77                              MSM_BO_UNCACHED)
78
79struct drm_msm_gem_new {
80	uint64_t size;           /* in */
81	uint32_t flags;          /* in, mask of MSM_BO_x */
82	uint32_t handle;         /* out */
83};
84
85struct drm_msm_gem_info {
86	uint32_t handle;         /* in */
87	uint32_t pad;
88	uint64_t offset;         /* out, offset to pass to mmap() */
89};
90
91#define MSM_PREP_READ        0x01
92#define MSM_PREP_WRITE       0x02
93#define MSM_PREP_NOSYNC      0x04
94
95#define MSM_PREP_FLAGS       (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC)
96
97struct drm_msm_gem_cpu_prep {
98	uint32_t handle;         /* in */
99	uint32_t op;             /* in, mask of MSM_PREP_x */
100	struct drm_msm_timespec timeout;   /* in */
101};
102
103struct drm_msm_gem_cpu_fini {
104	uint32_t handle;         /* in */
105};
106
107/*
108 * Cmdstream Submission:
109 */
110
111/* The value written into the cmdstream is logically:
112 *
113 *   ((relocbuf->gpuaddr + reloc_offset) << shift) | or
114 *
115 * When we have GPU's w/ >32bit ptrs, it should be possible to deal
116 * with this by emit'ing two reloc entries with appropriate shift
117 * values.  Or a new MSM_SUBMIT_CMD_x type would also be an option.
118 *
119 * NOTE that reloc's must be sorted by order of increasing submit_offset,
120 * otherwise EINVAL.
121 */
122struct drm_msm_gem_submit_reloc {
123	uint32_t submit_offset;  /* in, offset from submit_bo */
124	uint32_t or;             /* in, value OR'd with result */
125	int32_t  shift;          /* in, amount of left shift (can be negative) */
126	uint32_t reloc_idx;      /* in, index of reloc_bo buffer */
127	uint64_t reloc_offset;   /* in, offset from start of reloc_bo */
128};
129
130/* submit-types:
131 *   BUF - this cmd buffer is executed normally.
132 *   IB_TARGET_BUF - this cmd buffer is an IB target.  Reloc's are
133 *      processed normally, but the kernel does not setup an IB to
134 *      this buffer in the first-level ringbuffer
135 *   CTX_RESTORE_BUF - only executed if there has been a GPU context
136 *      switch since the last SUBMIT ioctl
137 */
138#define MSM_SUBMIT_CMD_BUF             0x0001
139#define MSM_SUBMIT_CMD_IB_TARGET_BUF   0x0002
140#define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003
141struct drm_msm_gem_submit_cmd {
142	uint32_t type;           /* in, one of MSM_SUBMIT_CMD_x */
143	uint32_t submit_idx;     /* in, index of submit_bo cmdstream buffer */
144	uint32_t submit_offset;  /* in, offset into submit_bo */
145	uint32_t size;           /* in, cmdstream size */
146	uint32_t pad;
147	uint32_t nr_relocs;      /* in, number of submit_reloc's */
148	uint64_t __user relocs;  /* in, ptr to array of submit_reloc's */
149};
150
151/* Each buffer referenced elsewhere in the cmdstream submit (ie. the
152 * cmdstream buffer(s) themselves or reloc entries) has one (and only
153 * one) entry in the submit->bos[] table.
154 *
155 * As a optimization, the current buffer (gpu virtual address) can be
156 * passed back through the 'presumed' field.  If on a subsequent reloc,
157 * userspace passes back a 'presumed' address that is still valid,
158 * then patching the cmdstream for this entry is skipped.  This can
159 * avoid kernel needing to map/access the cmdstream bo in the common
160 * case.
161 */
162#define MSM_SUBMIT_BO_READ             0x0001
163#define MSM_SUBMIT_BO_WRITE            0x0002
164
165#define MSM_SUBMIT_BO_FLAGS            (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE)
166
167struct drm_msm_gem_submit_bo {
168	uint32_t flags;          /* in, mask of MSM_SUBMIT_BO_x */
169	uint32_t handle;         /* in, GEM handle */
170	uint64_t presumed;       /* in/out, presumed buffer address */
171};
172
173/* Each cmdstream submit consists of a table of buffers involved, and
174 * one or more cmdstream buffers.  This allows for conditional execution
175 * (context-restore), and IB buffers needed for per tile/bin draw cmds.
176 */
177struct drm_msm_gem_submit {
178	uint32_t pipe;           /* in, MSM_PIPE_x */
179	uint32_t fence;          /* out */
180	uint32_t nr_bos;         /* in, number of submit_bo's */
181	uint32_t nr_cmds;        /* in, number of submit_cmd's */
182	uint64_t __user bos;     /* in, ptr to array of submit_bo's */
183	uint64_t __user cmds;    /* in, ptr to array of submit_cmd's */
184};
185
186/* The normal way to synchronize with the GPU is just to CPU_PREP on
187 * a buffer if you need to access it from the CPU (other cmdstream
188 * submission from same or other contexts, PAGE_FLIP ioctl, etc, all
189 * handle the required synchronization under the hood).  This ioctl
190 * mainly just exists as a way to implement the gallium pipe_fence
191 * APIs without requiring a dummy bo to synchronize on.
192 */
193struct drm_msm_wait_fence {
194	uint32_t fence;          /* in */
195	uint32_t pad;
196	struct drm_msm_timespec timeout;   /* in */
197};
198
199#define DRM_MSM_GET_PARAM              0x00
200/* placeholder:
201#define DRM_MSM_SET_PARAM              0x01
202 */
203#define DRM_MSM_GEM_NEW                0x02
204#define DRM_MSM_GEM_INFO               0x03
205#define DRM_MSM_GEM_CPU_PREP           0x04
206#define DRM_MSM_GEM_CPU_FINI           0x05
207#define DRM_MSM_GEM_SUBMIT             0x06
208#define DRM_MSM_WAIT_FENCE             0x07
209#define DRM_MSM_NUM_IOCTLS             0x08
210
211#define DRM_IOCTL_MSM_GET_PARAM        DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
212#define DRM_IOCTL_MSM_GEM_NEW          DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
213#define DRM_IOCTL_MSM_GEM_INFO         DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
214#define DRM_IOCTL_MSM_GEM_CPU_PREP     DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
215#define DRM_IOCTL_MSM_GEM_CPU_FINI     DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
216#define DRM_IOCTL_MSM_GEM_SUBMIT       DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
217#define DRM_IOCTL_MSM_WAIT_FENCE       DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
218
219#endif /* __MSM_DRM_H__ */
220