1/*
2 * Core driver interface to access RICOH_RC5T583 power management chip.
3 *
4 * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
5 * Author: Laxman dewangan <ldewangan@nvidia.com>
6 *
7 * Based on code
8 *      Copyright (C) 2011 RICOH COMPANY,LTD
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms and conditions of the GNU General Public License,
12 * version 2, as published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
21 *
22 */
23
24#ifndef __LINUX_MFD_RC5T583_H
25#define __LINUX_MFD_RC5T583_H
26
27#include <linux/mutex.h>
28#include <linux/types.h>
29#include <linux/regmap.h>
30
31#define RC5T583_MAX_REGS		0xF8
32
33/* Maximum number of main interrupts */
34#define MAX_MAIN_INTERRUPT		5
35#define RC5T583_MAX_GPEDGE_REG		2
36#define RC5T583_MAX_INTERRUPT_EN_REGS	8
37#define RC5T583_MAX_INTERRUPT_MASK_REGS	9
38
39/* Interrupt enable register */
40#define RC5T583_INT_EN_SYS1	0x19
41#define RC5T583_INT_EN_SYS2	0x1D
42#define RC5T583_INT_EN_DCDC	0x41
43#define RC5T583_INT_EN_RTC	0xED
44#define RC5T583_INT_EN_ADC1	0x90
45#define RC5T583_INT_EN_ADC2	0x91
46#define RC5T583_INT_EN_ADC3	0x92
47
48/* Interrupt status registers (monitor regs in Ricoh)*/
49#define RC5T583_INTC_INTPOL	0xAD
50#define RC5T583_INTC_INTEN	0xAE
51#define RC5T583_INTC_INTMON	0xAF
52
53#define RC5T583_INT_MON_GRP	0xAF
54#define RC5T583_INT_MON_SYS1	0x1B
55#define RC5T583_INT_MON_SYS2	0x1F
56#define RC5T583_INT_MON_DCDC	0x43
57#define RC5T583_INT_MON_RTC	0xEE
58
59/* Interrupt clearing registers */
60#define RC5T583_INT_IR_SYS1	0x1A
61#define RC5T583_INT_IR_SYS2	0x1E
62#define RC5T583_INT_IR_DCDC	0x42
63#define RC5T583_INT_IR_RTC	0xEE
64#define RC5T583_INT_IR_ADCL	0x94
65#define RC5T583_INT_IR_ADCH	0x95
66#define RC5T583_INT_IR_ADCEND	0x96
67#define RC5T583_INT_IR_GPIOR	0xA9
68#define RC5T583_INT_IR_GPIOF	0xAA
69
70/* Sleep sequence registers */
71#define RC5T583_SLPSEQ1		0x21
72#define RC5T583_SLPSEQ2		0x22
73#define RC5T583_SLPSEQ3		0x23
74#define RC5T583_SLPSEQ4		0x24
75#define RC5T583_SLPSEQ5		0x25
76#define RC5T583_SLPSEQ6		0x26
77#define RC5T583_SLPSEQ7		0x27
78#define RC5T583_SLPSEQ8		0x28
79#define RC5T583_SLPSEQ9		0x29
80#define RC5T583_SLPSEQ10	0x2A
81#define RC5T583_SLPSEQ11	0x2B
82
83/* Regulator registers */
84#define RC5T583_REG_DC0CTL	0x30
85#define RC5T583_REG_DC0DAC	0x31
86#define RC5T583_REG_DC0LATCTL	0x32
87#define RC5T583_REG_SR0CTL	0x33
88
89#define RC5T583_REG_DC1CTL	0x34
90#define RC5T583_REG_DC1DAC	0x35
91#define RC5T583_REG_DC1LATCTL	0x36
92#define RC5T583_REG_SR1CTL	0x37
93
94#define RC5T583_REG_DC2CTL	0x38
95#define RC5T583_REG_DC2DAC	0x39
96#define RC5T583_REG_DC2LATCTL	0x3A
97#define RC5T583_REG_SR2CTL	0x3B
98
99#define RC5T583_REG_DC3CTL	0x3C
100#define RC5T583_REG_DC3DAC	0x3D
101#define RC5T583_REG_DC3LATCTL	0x3E
102#define RC5T583_REG_SR3CTL	0x3F
103
104
105#define RC5T583_REG_LDOEN1	0x50
106#define RC5T583_REG_LDOEN2	0x51
107#define RC5T583_REG_LDODIS1	0x52
108#define RC5T583_REG_LDODIS2	0x53
109
110#define RC5T583_REG_LDO0DAC	0x54
111#define RC5T583_REG_LDO1DAC	0x55
112#define RC5T583_REG_LDO2DAC	0x56
113#define RC5T583_REG_LDO3DAC	0x57
114#define RC5T583_REG_LDO4DAC	0x58
115#define RC5T583_REG_LDO5DAC	0x59
116#define RC5T583_REG_LDO6DAC	0x5A
117#define RC5T583_REG_LDO7DAC	0x5B
118#define RC5T583_REG_LDO8DAC	0x5C
119#define RC5T583_REG_LDO9DAC	0x5D
120
121#define RC5T583_REG_DC0DAC_DS	0x60
122#define RC5T583_REG_DC1DAC_DS	0x61
123#define RC5T583_REG_DC2DAC_DS	0x62
124#define RC5T583_REG_DC3DAC_DS	0x63
125
126#define RC5T583_REG_LDO0DAC_DS	0x64
127#define RC5T583_REG_LDO1DAC_DS	0x65
128#define RC5T583_REG_LDO2DAC_DS	0x66
129#define RC5T583_REG_LDO3DAC_DS	0x67
130#define RC5T583_REG_LDO4DAC_DS	0x68
131#define RC5T583_REG_LDO5DAC_DS	0x69
132#define RC5T583_REG_LDO6DAC_DS	0x6A
133#define RC5T583_REG_LDO7DAC_DS	0x6B
134#define RC5T583_REG_LDO8DAC_DS	0x6C
135#define RC5T583_REG_LDO9DAC_DS	0x6D
136
137/* GPIO register base address */
138#define RC5T583_GPIO_IOSEL	0xA0
139#define RC5T583_GPIO_PDEN	0xA1
140#define RC5T583_GPIO_IOOUT	0xA2
141#define RC5T583_GPIO_PGSEL	0xA3
142#define RC5T583_GPIO_GPINV	0xA4
143#define RC5T583_GPIO_GPDEB	0xA5
144#define RC5T583_GPIO_GPEDGE1	0xA6
145#define RC5T583_GPIO_GPEDGE2	0xA7
146#define RC5T583_GPIO_EN_INT	0xA8
147#define RC5T583_GPIO_MON_IOIN	0xAB
148#define RC5T583_GPIO_GPOFUNC	0xAC
149
150/* RTC registers */
151#define RC5T583_RTC_SEC		0xE0
152#define RC5T583_RTC_MIN		0xE1
153#define RC5T583_RTC_HOUR	0xE2
154#define RC5T583_RTC_WDAY	0xE3
155#define RC5T583_RTC_DAY		0xE4
156#define RC5T583_RTC_MONTH	0xE5
157#define RC5T583_RTC_YEAR	0xE6
158#define RC5T583_RTC_ADJ		0xE7
159#define RC5T583_RTC_AW_MIN	0xE8
160#define RC5T583_RTC_AW_HOUR	0xE9
161#define RC5T583_RTC_AW_WEEK	0xEA
162#define RC5T583_RTC_AD_MIN	0xEB
163#define RC5T583_RTC_AD_HOUR	0xEC
164#define RC5T583_RTC_CTL1	0xED
165#define RC5T583_RTC_CTL2	0xEE
166#define RC5T583_RTC_AY_MIN	0xF0
167#define RC5T583_RTC_AY_HOUR	0xF1
168#define RC5T583_RTC_AY_DAY	0xF2
169#define RC5T583_RTC_AY_MONTH 0xF3
170#define RC5T583_RTC_AY_YEAR	0xF4
171
172/* RICOH_RC5T583 IRQ definitions */
173enum {
174	RC5T583_IRQ_ONKEY,
175	RC5T583_IRQ_ACOK,
176	RC5T583_IRQ_LIDOPEN,
177	RC5T583_IRQ_PREOT,
178	RC5T583_IRQ_CLKSTP,
179	RC5T583_IRQ_ONKEY_OFF,
180	RC5T583_IRQ_WD,
181	RC5T583_IRQ_EN_PWRREQ1,
182	RC5T583_IRQ_EN_PWRREQ2,
183	RC5T583_IRQ_PRE_VINDET,
184
185	RC5T583_IRQ_DC0LIM,
186	RC5T583_IRQ_DC1LIM,
187	RC5T583_IRQ_DC2LIM,
188	RC5T583_IRQ_DC3LIM,
189
190	RC5T583_IRQ_CTC,
191	RC5T583_IRQ_YALE,
192	RC5T583_IRQ_DALE,
193	RC5T583_IRQ_WALE,
194
195	RC5T583_IRQ_AIN1L,
196	RC5T583_IRQ_AIN2L,
197	RC5T583_IRQ_AIN3L,
198	RC5T583_IRQ_VBATL,
199	RC5T583_IRQ_VIN3L,
200	RC5T583_IRQ_VIN8L,
201	RC5T583_IRQ_AIN1H,
202	RC5T583_IRQ_AIN2H,
203	RC5T583_IRQ_AIN3H,
204	RC5T583_IRQ_VBATH,
205	RC5T583_IRQ_VIN3H,
206	RC5T583_IRQ_VIN8H,
207	RC5T583_IRQ_ADCEND,
208
209	RC5T583_IRQ_GPIO0,
210	RC5T583_IRQ_GPIO1,
211	RC5T583_IRQ_GPIO2,
212	RC5T583_IRQ_GPIO3,
213	RC5T583_IRQ_GPIO4,
214	RC5T583_IRQ_GPIO5,
215	RC5T583_IRQ_GPIO6,
216	RC5T583_IRQ_GPIO7,
217
218	/* Should be last entry */
219	RC5T583_MAX_IRQS,
220};
221
222/* Ricoh583 gpio definitions */
223enum {
224	RC5T583_GPIO0,
225	RC5T583_GPIO1,
226	RC5T583_GPIO2,
227	RC5T583_GPIO3,
228	RC5T583_GPIO4,
229	RC5T583_GPIO5,
230	RC5T583_GPIO6,
231	RC5T583_GPIO7,
232
233	/* Should be last entry */
234	RC5T583_MAX_GPIO,
235};
236
237enum {
238	RC5T583_DS_NONE,
239	RC5T583_DS_DC0,
240	RC5T583_DS_DC1,
241	RC5T583_DS_DC2,
242	RC5T583_DS_DC3,
243	RC5T583_DS_LDO0,
244	RC5T583_DS_LDO1,
245	RC5T583_DS_LDO2,
246	RC5T583_DS_LDO3,
247	RC5T583_DS_LDO4,
248	RC5T583_DS_LDO5,
249	RC5T583_DS_LDO6,
250	RC5T583_DS_LDO7,
251	RC5T583_DS_LDO8,
252	RC5T583_DS_LDO9,
253	RC5T583_DS_PSO0,
254	RC5T583_DS_PSO1,
255	RC5T583_DS_PSO2,
256	RC5T583_DS_PSO3,
257	RC5T583_DS_PSO4,
258	RC5T583_DS_PSO5,
259	RC5T583_DS_PSO6,
260	RC5T583_DS_PSO7,
261
262	/* Should be last entry */
263	RC5T583_DS_MAX,
264};
265
266/*
267 * Ricoh pmic RC5T583 supports sleep through two external controls.
268 * The output of gpios and regulator can be enable/disable through
269 * this external signals.
270 */
271enum {
272	RC5T583_EXT_PWRREQ1_CONTROL = 0x1,
273	RC5T583_EXT_PWRREQ2_CONTROL = 0x2,
274};
275
276enum {
277	RC5T583_REGULATOR_DC0,
278	RC5T583_REGULATOR_DC1,
279	RC5T583_REGULATOR_DC2,
280	RC5T583_REGULATOR_DC3,
281	RC5T583_REGULATOR_LDO0,
282	RC5T583_REGULATOR_LDO1,
283	RC5T583_REGULATOR_LDO2,
284	RC5T583_REGULATOR_LDO3,
285	RC5T583_REGULATOR_LDO4,
286	RC5T583_REGULATOR_LDO5,
287	RC5T583_REGULATOR_LDO6,
288	RC5T583_REGULATOR_LDO7,
289	RC5T583_REGULATOR_LDO8,
290	RC5T583_REGULATOR_LDO9,
291
292	/* Should be last entry */
293	RC5T583_REGULATOR_MAX,
294};
295
296struct rc5t583 {
297	struct device	*dev;
298	struct regmap	*regmap;
299	int		chip_irq;
300	int		irq_base;
301	struct mutex	irq_lock;
302	unsigned long	group_irq_en[MAX_MAIN_INTERRUPT];
303
304	/* For main interrupt bits in INTC */
305	uint8_t		intc_inten_reg;
306
307	/* For group interrupt bits and address */
308	uint8_t		irq_en_reg[RC5T583_MAX_INTERRUPT_EN_REGS];
309
310	/* For gpio edge */
311	uint8_t		gpedge_reg[RC5T583_MAX_GPEDGE_REG];
312};
313
314/*
315 * rc5t583_platform_data: Platform data for ricoh rc5t583 pmu.
316 * The board specific data is provided through this structure.
317 * @irq_base: Irq base number on which this device registers their interrupts.
318 * @gpio_base: GPIO base from which gpio of this device will start.
319 * @enable_shutdown: Enable shutdown through the input pin "shutdown".
320 * @regulator_deepsleep_slot: The slot number on which device goes to sleep
321 *		in device sleep mode.
322 * @regulator_ext_pwr_control: External power request regulator control. The
323 *		regulator output enable/disable is controlled by the external
324 *		power request input state.
325 * @reg_init_data: Regulator init data.
326 */
327
328struct rc5t583_platform_data {
329	int		irq_base;
330	int		gpio_base;
331	bool		enable_shutdown;
332	int		regulator_deepsleep_slot[RC5T583_REGULATOR_MAX];
333	unsigned long	regulator_ext_pwr_control[RC5T583_REGULATOR_MAX];
334	struct regulator_init_data *reg_init_data[RC5T583_REGULATOR_MAX];
335};
336
337static inline int rc5t583_write(struct device *dev, uint8_t reg, uint8_t val)
338{
339	struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
340	return regmap_write(rc5t583->regmap, reg, val);
341}
342
343static inline int rc5t583_read(struct device *dev, uint8_t reg, uint8_t *val)
344{
345	struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
346	unsigned int ival;
347	int ret;
348	ret = regmap_read(rc5t583->regmap, reg, &ival);
349	if (!ret)
350		*val = (uint8_t)ival;
351	return ret;
352}
353
354static inline int rc5t583_set_bits(struct device *dev, unsigned int reg,
355			unsigned int bit_mask)
356{
357	struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
358	return regmap_update_bits(rc5t583->regmap, reg, bit_mask, bit_mask);
359}
360
361static inline int rc5t583_clear_bits(struct device *dev, unsigned int reg,
362			unsigned int bit_mask)
363{
364	struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
365	return regmap_update_bits(rc5t583->regmap, reg, bit_mask, 0);
366}
367
368static inline int rc5t583_update(struct device *dev, unsigned int reg,
369		unsigned int val, unsigned int mask)
370{
371	struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
372	return regmap_update_bits(rc5t583->regmap, reg, mask, val);
373}
374
375int rc5t583_ext_power_req_config(struct device *dev, int deepsleep_id,
376	int ext_pwr_req, int deepsleep_slot_nr);
377int rc5t583_irq_init(struct rc5t583 *rc5t583, int irq, int irq_base);
378int rc5t583_irq_exit(struct rc5t583 *rc5t583);
379
380#endif
381