1/* 2 * as3722 definitions 3 * 4 * Copyright (C) 2013 ams 5 * Copyright (c) 2013, NVIDIA Corporation. All rights reserved. 6 * 7 * Author: Florian Lobmaier <florian.lobmaier@ams.com> 8 * Author: Laxman Dewangan <ldewangan@nvidia.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 * 24 */ 25 26#ifndef __LINUX_MFD_AS3722_H__ 27#define __LINUX_MFD_AS3722_H__ 28 29#include <linux/regmap.h> 30 31/* AS3722 registers */ 32#define AS3722_SD0_VOLTAGE_REG 0x00 33#define AS3722_SD1_VOLTAGE_REG 0x01 34#define AS3722_SD2_VOLTAGE_REG 0x02 35#define AS3722_SD3_VOLTAGE_REG 0x03 36#define AS3722_SD4_VOLTAGE_REG 0x04 37#define AS3722_SD5_VOLTAGE_REG 0x05 38#define AS3722_SD6_VOLTAGE_REG 0x06 39#define AS3722_GPIO0_CONTROL_REG 0x08 40#define AS3722_GPIO1_CONTROL_REG 0x09 41#define AS3722_GPIO2_CONTROL_REG 0x0A 42#define AS3722_GPIO3_CONTROL_REG 0x0B 43#define AS3722_GPIO4_CONTROL_REG 0x0C 44#define AS3722_GPIO5_CONTROL_REG 0x0D 45#define AS3722_GPIO6_CONTROL_REG 0x0E 46#define AS3722_GPIO7_CONTROL_REG 0x0F 47#define AS3722_LDO0_VOLTAGE_REG 0x10 48#define AS3722_LDO1_VOLTAGE_REG 0x11 49#define AS3722_LDO2_VOLTAGE_REG 0x12 50#define AS3722_LDO3_VOLTAGE_REG 0x13 51#define AS3722_LDO4_VOLTAGE_REG 0x14 52#define AS3722_LDO5_VOLTAGE_REG 0x15 53#define AS3722_LDO6_VOLTAGE_REG 0x16 54#define AS3722_LDO7_VOLTAGE_REG 0x17 55#define AS3722_LDO9_VOLTAGE_REG 0x19 56#define AS3722_LDO10_VOLTAGE_REG 0x1A 57#define AS3722_LDO11_VOLTAGE_REG 0x1B 58#define AS3722_GPIO_DEB1_REG 0x1E 59#define AS3722_GPIO_DEB2_REG 0x1F 60#define AS3722_GPIO_SIGNAL_OUT_REG 0x20 61#define AS3722_GPIO_SIGNAL_IN_REG 0x21 62#define AS3722_REG_SEQU_MOD1_REG 0x22 63#define AS3722_REG_SEQU_MOD2_REG 0x23 64#define AS3722_REG_SEQU_MOD3_REG 0x24 65#define AS3722_SD_PHSW_CTRL_REG 0x27 66#define AS3722_SD_PHSW_STATUS 0x28 67#define AS3722_SD0_CONTROL_REG 0x29 68#define AS3722_SD1_CONTROL_REG 0x2A 69#define AS3722_SDmph_CONTROL_REG 0x2B 70#define AS3722_SD23_CONTROL_REG 0x2C 71#define AS3722_SD4_CONTROL_REG 0x2D 72#define AS3722_SD5_CONTROL_REG 0x2E 73#define AS3722_SD6_CONTROL_REG 0x2F 74#define AS3722_SD_DVM_REG 0x30 75#define AS3722_RESET_REASON_REG 0x31 76#define AS3722_BATTERY_VOLTAGE_MONITOR_REG 0x32 77#define AS3722_STARTUP_CONTROL_REG 0x33 78#define AS3722_RESET_TIMER_REG 0x34 79#define AS3722_REFERENCE_CONTROL_REG 0x35 80#define AS3722_RESET_CONTROL_REG 0x36 81#define AS3722_OVER_TEMP_CONTROL_REG 0x37 82#define AS3722_WATCHDOG_CONTROL_REG 0x38 83#define AS3722_REG_STANDBY_MOD1_REG 0x39 84#define AS3722_REG_STANDBY_MOD2_REG 0x3A 85#define AS3722_REG_STANDBY_MOD3_REG 0x3B 86#define AS3722_ENABLE_CTRL1_REG 0x3C 87#define AS3722_ENABLE_CTRL2_REG 0x3D 88#define AS3722_ENABLE_CTRL3_REG 0x3E 89#define AS3722_ENABLE_CTRL4_REG 0x3F 90#define AS3722_ENABLE_CTRL5_REG 0x40 91#define AS3722_PWM_CONTROL_L_REG 0x41 92#define AS3722_PWM_CONTROL_H_REG 0x42 93#define AS3722_WATCHDOG_TIMER_REG 0x46 94#define AS3722_WATCHDOG_SOFTWARE_SIGNAL_REG 0x48 95#define AS3722_IOVOLTAGE_REG 0x49 96#define AS3722_BATTERY_VOLTAGE_MONITOR2_REG 0x4A 97#define AS3722_SD_CONTROL_REG 0x4D 98#define AS3722_LDOCONTROL0_REG 0x4E 99#define AS3722_LDOCONTROL1_REG 0x4F 100#define AS3722_SD0_PROTECT_REG 0x50 101#define AS3722_SD6_PROTECT_REG 0x51 102#define AS3722_PWM_VCONTROL1_REG 0x52 103#define AS3722_PWM_VCONTROL2_REG 0x53 104#define AS3722_PWM_VCONTROL3_REG 0x54 105#define AS3722_PWM_VCONTROL4_REG 0x55 106#define AS3722_BB_CHARGER_REG 0x57 107#define AS3722_CTRL_SEQU1_REG 0x58 108#define AS3722_CTRL_SEQU2_REG 0x59 109#define AS3722_OVCURRENT_REG 0x5A 110#define AS3722_OVCURRENT_DEB_REG 0x5B 111#define AS3722_SDLV_DEB_REG 0x5C 112#define AS3722_OC_PG_CTRL_REG 0x5D 113#define AS3722_OC_PG_CTRL2_REG 0x5E 114#define AS3722_CTRL_STATUS 0x5F 115#define AS3722_RTC_CONTROL_REG 0x60 116#define AS3722_RTC_SECOND_REG 0x61 117#define AS3722_RTC_MINUTE_REG 0x62 118#define AS3722_RTC_HOUR_REG 0x63 119#define AS3722_RTC_DAY_REG 0x64 120#define AS3722_RTC_MONTH_REG 0x65 121#define AS3722_RTC_YEAR_REG 0x66 122#define AS3722_RTC_ALARM_SECOND_REG 0x67 123#define AS3722_RTC_ALARM_MINUTE_REG 0x68 124#define AS3722_RTC_ALARM_HOUR_REG 0x69 125#define AS3722_RTC_ALARM_DAY_REG 0x6A 126#define AS3722_RTC_ALARM_MONTH_REG 0x6B 127#define AS3722_RTC_ALARM_YEAR_REG 0x6C 128#define AS3722_SRAM_REG 0x6D 129#define AS3722_RTC_ACCESS_REG 0x6F 130#define AS3722_RTC_STATUS_REG 0x73 131#define AS3722_INTERRUPT_MASK1_REG 0x74 132#define AS3722_INTERRUPT_MASK2_REG 0x75 133#define AS3722_INTERRUPT_MASK3_REG 0x76 134#define AS3722_INTERRUPT_MASK4_REG 0x77 135#define AS3722_INTERRUPT_STATUS1_REG 0x78 136#define AS3722_INTERRUPT_STATUS2_REG 0x79 137#define AS3722_INTERRUPT_STATUS3_REG 0x7A 138#define AS3722_INTERRUPT_STATUS4_REG 0x7B 139#define AS3722_TEMP_STATUS_REG 0x7D 140#define AS3722_ADC0_CONTROL_REG 0x80 141#define AS3722_ADC1_CONTROL_REG 0x81 142#define AS3722_ADC0_MSB_RESULT_REG 0x82 143#define AS3722_ADC0_LSB_RESULT_REG 0x83 144#define AS3722_ADC1_MSB_RESULT_REG 0x84 145#define AS3722_ADC1_LSB_RESULT_REG 0x85 146#define AS3722_ADC1_THRESHOLD_HI_MSB_REG 0x86 147#define AS3722_ADC1_THRESHOLD_HI_LSB_REG 0x87 148#define AS3722_ADC1_THRESHOLD_LO_MSB_REG 0x88 149#define AS3722_ADC1_THRESHOLD_LO_LSB_REG 0x89 150#define AS3722_ADC_CONFIGURATION_REG 0x8A 151#define AS3722_ASIC_ID1_REG 0x90 152#define AS3722_ASIC_ID2_REG 0x91 153#define AS3722_LOCK_REG 0x9E 154#define AS3722_FUSE7_REG 0xA7 155#define AS3722_MAX_REGISTER 0xF4 156 157#define AS3722_SD0_EXT_ENABLE_MASK 0x03 158#define AS3722_SD1_EXT_ENABLE_MASK 0x0C 159#define AS3722_SD2_EXT_ENABLE_MASK 0x30 160#define AS3722_SD3_EXT_ENABLE_MASK 0xC0 161#define AS3722_SD4_EXT_ENABLE_MASK 0x03 162#define AS3722_SD5_EXT_ENABLE_MASK 0x0C 163#define AS3722_SD6_EXT_ENABLE_MASK 0x30 164#define AS3722_LDO0_EXT_ENABLE_MASK 0x03 165#define AS3722_LDO1_EXT_ENABLE_MASK 0x0C 166#define AS3722_LDO2_EXT_ENABLE_MASK 0x30 167#define AS3722_LDO3_EXT_ENABLE_MASK 0xC0 168#define AS3722_LDO4_EXT_ENABLE_MASK 0x03 169#define AS3722_LDO5_EXT_ENABLE_MASK 0x0C 170#define AS3722_LDO6_EXT_ENABLE_MASK 0x30 171#define AS3722_LDO7_EXT_ENABLE_MASK 0xC0 172#define AS3722_LDO9_EXT_ENABLE_MASK 0x0C 173#define AS3722_LDO10_EXT_ENABLE_MASK 0x30 174#define AS3722_LDO11_EXT_ENABLE_MASK 0xC0 175 176#define AS3722_OVCURRENT_SD0_ALARM_MASK 0x07 177#define AS3722_OVCURRENT_SD0_ALARM_SHIFT 0x01 178#define AS3722_OVCURRENT_SD0_TRIP_MASK 0x18 179#define AS3722_OVCURRENT_SD0_TRIP_SHIFT 0x03 180#define AS3722_OVCURRENT_SD1_TRIP_MASK 0x60 181#define AS3722_OVCURRENT_SD1_TRIP_SHIFT 0x05 182 183#define AS3722_OVCURRENT_SD6_ALARM_MASK 0x07 184#define AS3722_OVCURRENT_SD6_ALARM_SHIFT 0x01 185#define AS3722_OVCURRENT_SD6_TRIP_MASK 0x18 186#define AS3722_OVCURRENT_SD6_TRIP_SHIFT 0x03 187 188/* AS3722 register bits and bit masks */ 189#define AS3722_LDO_ILIMIT_MASK BIT(7) 190#define AS3722_LDO_ILIMIT_BIT BIT(7) 191#define AS3722_LDO0_VSEL_MASK 0x1F 192#define AS3722_LDO0_VSEL_MIN 0x01 193#define AS3722_LDO0_VSEL_MAX 0x12 194#define AS3722_LDO0_NUM_VOLT 0x12 195#define AS3722_LDO3_VSEL_MASK 0x3F 196#define AS3722_LDO3_VSEL_MIN 0x01 197#define AS3722_LDO3_VSEL_MAX 0x2D 198#define AS3722_LDO3_NUM_VOLT 0x2D 199#define AS3722_LDO_VSEL_MASK 0x7F 200#define AS3722_LDO_VSEL_MIN 0x01 201#define AS3722_LDO_VSEL_MAX 0x7F 202#define AS3722_LDO_VSEL_DNU_MIN 0x25 203#define AS3722_LDO_VSEL_DNU_MAX 0x3F 204#define AS3722_LDO_NUM_VOLT 0x80 205 206#define AS3722_LDO0_CTRL BIT(0) 207#define AS3722_LDO1_CTRL BIT(1) 208#define AS3722_LDO2_CTRL BIT(2) 209#define AS3722_LDO3_CTRL BIT(3) 210#define AS3722_LDO4_CTRL BIT(4) 211#define AS3722_LDO5_CTRL BIT(5) 212#define AS3722_LDO6_CTRL BIT(6) 213#define AS3722_LDO7_CTRL BIT(7) 214#define AS3722_LDO9_CTRL BIT(1) 215#define AS3722_LDO10_CTRL BIT(2) 216#define AS3722_LDO11_CTRL BIT(3) 217 218#define AS3722_LDO3_MODE_MASK (3 << 6) 219#define AS3722_LDO3_MODE_VAL(n) (((n) & 0x3) << 6) 220#define AS3722_LDO3_MODE_PMOS AS3722_LDO3_MODE_VAL(0) 221#define AS3722_LDO3_MODE_PMOS_TRACKING AS3722_LDO3_MODE_VAL(1) 222#define AS3722_LDO3_MODE_NMOS AS3722_LDO3_MODE_VAL(2) 223#define AS3722_LDO3_MODE_SWITCH AS3722_LDO3_MODE_VAL(3) 224 225#define AS3722_SD_VSEL_MASK 0x7F 226#define AS3722_SD0_VSEL_MIN 0x01 227#define AS3722_SD0_VSEL_MAX 0x5A 228#define AS3722_SD0_VSEL_LOW_VOL_MAX 0x6E 229#define AS3722_SD2_VSEL_MIN 0x01 230#define AS3722_SD2_VSEL_MAX 0x7F 231 232#define AS3722_SDn_CTRL(n) BIT(n) 233 234#define AS3722_SD0_MODE_FAST BIT(4) 235#define AS3722_SD1_MODE_FAST BIT(4) 236#define AS3722_SD2_MODE_FAST BIT(2) 237#define AS3722_SD3_MODE_FAST BIT(6) 238#define AS3722_SD4_MODE_FAST BIT(2) 239#define AS3722_SD5_MODE_FAST BIT(2) 240#define AS3722_SD6_MODE_FAST BIT(4) 241 242#define AS3722_POWER_OFF BIT(1) 243 244#define AS3722_INTERRUPT_MASK1_LID BIT(0) 245#define AS3722_INTERRUPT_MASK1_ACOK BIT(1) 246#define AS3722_INTERRUPT_MASK1_ENABLE1 BIT(2) 247#define AS3722_INTERRUPT_MASK1_OCURR_ALARM_SD0 BIT(3) 248#define AS3722_INTERRUPT_MASK1_ONKEY_LONG BIT(4) 249#define AS3722_INTERRUPT_MASK1_ONKEY BIT(5) 250#define AS3722_INTERRUPT_MASK1_OVTMP BIT(6) 251#define AS3722_INTERRUPT_MASK1_LOWBAT BIT(7) 252 253#define AS3722_INTERRUPT_MASK2_SD0_LV BIT(0) 254#define AS3722_INTERRUPT_MASK2_SD1_LV BIT(1) 255#define AS3722_INTERRUPT_MASK2_SD2345_LV BIT(2) 256#define AS3722_INTERRUPT_MASK2_PWM1_OV_PROT BIT(3) 257#define AS3722_INTERRUPT_MASK2_PWM2_OV_PROT BIT(4) 258#define AS3722_INTERRUPT_MASK2_ENABLE2 BIT(5) 259#define AS3722_INTERRUPT_MASK2_SD6_LV BIT(6) 260#define AS3722_INTERRUPT_MASK2_RTC_REP BIT(7) 261 262#define AS3722_INTERRUPT_MASK3_RTC_ALARM BIT(0) 263#define AS3722_INTERRUPT_MASK3_GPIO1 BIT(1) 264#define AS3722_INTERRUPT_MASK3_GPIO2 BIT(2) 265#define AS3722_INTERRUPT_MASK3_GPIO3 BIT(3) 266#define AS3722_INTERRUPT_MASK3_GPIO4 BIT(4) 267#define AS3722_INTERRUPT_MASK3_GPIO5 BIT(5) 268#define AS3722_INTERRUPT_MASK3_WATCHDOG BIT(6) 269#define AS3722_INTERRUPT_MASK3_ENABLE3 BIT(7) 270 271#define AS3722_INTERRUPT_MASK4_TEMP_SD0_SHUTDOWN BIT(0) 272#define AS3722_INTERRUPT_MASK4_TEMP_SD1_SHUTDOWN BIT(1) 273#define AS3722_INTERRUPT_MASK4_TEMP_SD6_SHUTDOWN BIT(2) 274#define AS3722_INTERRUPT_MASK4_TEMP_SD0_ALARM BIT(3) 275#define AS3722_INTERRUPT_MASK4_TEMP_SD1_ALARM BIT(4) 276#define AS3722_INTERRUPT_MASK4_TEMP_SD6_ALARM BIT(5) 277#define AS3722_INTERRUPT_MASK4_OCCUR_ALARM_SD6 BIT(6) 278#define AS3722_INTERRUPT_MASK4_ADC BIT(7) 279 280#define AS3722_ADC1_INTERVAL_TIME BIT(0) 281#define AS3722_ADC1_INT_MODE_ON BIT(1) 282#define AS3722_ADC_BUF_ON BIT(2) 283#define AS3722_ADC1_LOW_VOLTAGE_RANGE BIT(5) 284#define AS3722_ADC1_INTEVAL_SCAN BIT(6) 285#define AS3722_ADC1_INT_MASK BIT(7) 286 287#define AS3722_ADC_MSB_VAL_MASK 0x7F 288#define AS3722_ADC_LSB_VAL_MASK 0x07 289 290#define AS3722_ADC0_CONV_START BIT(7) 291#define AS3722_ADC0_CONV_NOTREADY BIT(7) 292#define AS3722_ADC0_SOURCE_SELECT_MASK 0x1F 293 294#define AS3722_ADC1_CONV_START BIT(7) 295#define AS3722_ADC1_CONV_NOTREADY BIT(7) 296#define AS3722_ADC1_SOURCE_SELECT_MASK 0x1F 297 298/* GPIO modes */ 299#define AS3722_GPIO_MODE_MASK 0x07 300#define AS3722_GPIO_MODE_INPUT 0x00 301#define AS3722_GPIO_MODE_OUTPUT_VDDH 0x01 302#define AS3722_GPIO_MODE_IO_OPEN_DRAIN 0x02 303#define AS3722_GPIO_MODE_ADC_IN 0x03 304#define AS3722_GPIO_MODE_INPUT_PULL_UP 0x04 305#define AS3722_GPIO_MODE_INPUT_PULL_DOWN 0x05 306#define AS3722_GPIO_MODE_IO_OPEN_DRAIN_PULL_UP 0x06 307#define AS3722_GPIO_MODE_OUTPUT_VDDL 0x07 308#define AS3722_GPIO_MODE_VAL(n) ((n) & AS3722_GPIO_MODE_MASK) 309 310#define AS3722_GPIO_INV BIT(7) 311#define AS3722_GPIO_IOSF_MASK 0x78 312#define AS3722_GPIO_IOSF_VAL(n) (((n) & 0xF) << 3) 313#define AS3722_GPIO_IOSF_NORMAL AS3722_GPIO_IOSF_VAL(0) 314#define AS3722_GPIO_IOSF_INTERRUPT_OUT AS3722_GPIO_IOSF_VAL(1) 315#define AS3722_GPIO_IOSF_VSUP_LOW_OUT AS3722_GPIO_IOSF_VAL(2) 316#define AS3722_GPIO_IOSF_GPIO_INTERRUPT_IN AS3722_GPIO_IOSF_VAL(3) 317#define AS3722_GPIO_IOSF_ISINK_PWM_IN AS3722_GPIO_IOSF_VAL(4) 318#define AS3722_GPIO_IOSF_VOLTAGE_STBY AS3722_GPIO_IOSF_VAL(5) 319#define AS3722_GPIO_IOSF_SD0_OUT AS3722_GPIO_IOSF_VAL(6) 320#define AS3722_GPIO_IOSF_PWR_GOOD_OUT AS3722_GPIO_IOSF_VAL(7) 321#define AS3722_GPIO_IOSF_Q32K_OUT AS3722_GPIO_IOSF_VAL(8) 322#define AS3722_GPIO_IOSF_WATCHDOG_IN AS3722_GPIO_IOSF_VAL(9) 323#define AS3722_GPIO_IOSF_SOFT_RESET_IN AS3722_GPIO_IOSF_VAL(11) 324#define AS3722_GPIO_IOSF_PWM_OUT AS3722_GPIO_IOSF_VAL(12) 325#define AS3722_GPIO_IOSF_VSUP_LOW_DEB_OUT AS3722_GPIO_IOSF_VAL(13) 326#define AS3722_GPIO_IOSF_SD6_LOW_VOLT_LOW AS3722_GPIO_IOSF_VAL(14) 327 328#define AS3722_GPIOn_SIGNAL(n) BIT(n) 329#define AS3722_GPIOn_CONTROL_REG(n) (AS3722_GPIO0_CONTROL_REG + n) 330#define AS3722_I2C_PULL_UP BIT(4) 331#define AS3722_INT_PULL_UP BIT(5) 332 333#define AS3722_RTC_REP_WAKEUP_EN BIT(0) 334#define AS3722_RTC_ALARM_WAKEUP_EN BIT(1) 335#define AS3722_RTC_ON BIT(2) 336#define AS3722_RTC_IRQMODE BIT(3) 337#define AS3722_RTC_CLK32K_OUT_EN BIT(5) 338 339#define AS3722_WATCHDOG_TIMER_MAX 0x7F 340#define AS3722_WATCHDOG_ON BIT(0) 341#define AS3722_WATCHDOG_SW_SIG BIT(0) 342 343#define AS3722_EXT_CONTROL_ENABLE1 0x1 344#define AS3722_EXT_CONTROL_ENABLE2 0x2 345#define AS3722_EXT_CONTROL_ENABLE3 0x3 346 347#define AS3722_FUSE7_SD0_LOW_VOLTAGE BIT(4) 348 349/* Interrupt IDs */ 350enum as3722_irq { 351 AS3722_IRQ_LID, 352 AS3722_IRQ_ACOK, 353 AS3722_IRQ_ENABLE1, 354 AS3722_IRQ_OCCUR_ALARM_SD0, 355 AS3722_IRQ_ONKEY_LONG_PRESS, 356 AS3722_IRQ_ONKEY, 357 AS3722_IRQ_OVTMP, 358 AS3722_IRQ_LOWBAT, 359 AS3722_IRQ_SD0_LV, 360 AS3722_IRQ_SD1_LV, 361 AS3722_IRQ_SD2_LV, 362 AS3722_IRQ_PWM1_OV_PROT, 363 AS3722_IRQ_PWM2_OV_PROT, 364 AS3722_IRQ_ENABLE2, 365 AS3722_IRQ_SD6_LV, 366 AS3722_IRQ_RTC_REP, 367 AS3722_IRQ_RTC_ALARM, 368 AS3722_IRQ_GPIO1, 369 AS3722_IRQ_GPIO2, 370 AS3722_IRQ_GPIO3, 371 AS3722_IRQ_GPIO4, 372 AS3722_IRQ_GPIO5, 373 AS3722_IRQ_WATCHDOG, 374 AS3722_IRQ_ENABLE3, 375 AS3722_IRQ_TEMP_SD0_SHUTDOWN, 376 AS3722_IRQ_TEMP_SD1_SHUTDOWN, 377 AS3722_IRQ_TEMP_SD2_SHUTDOWN, 378 AS3722_IRQ_TEMP_SD0_ALARM, 379 AS3722_IRQ_TEMP_SD1_ALARM, 380 AS3722_IRQ_TEMP_SD6_ALARM, 381 AS3722_IRQ_OCCUR_ALARM_SD6, 382 AS3722_IRQ_ADC, 383 AS3722_IRQ_MAX, 384}; 385 386struct as3722 { 387 struct device *dev; 388 struct regmap *regmap; 389 int chip_irq; 390 unsigned long irq_flags; 391 bool en_intern_int_pullup; 392 bool en_intern_i2c_pullup; 393 struct regmap_irq_chip_data *irq_data; 394}; 395 396static inline int as3722_read(struct as3722 *as3722, u32 reg, u32 *dest) 397{ 398 return regmap_read(as3722->regmap, reg, dest); 399} 400 401static inline int as3722_write(struct as3722 *as3722, u32 reg, u32 value) 402{ 403 return regmap_write(as3722->regmap, reg, value); 404} 405 406static inline int as3722_block_read(struct as3722 *as3722, u32 reg, 407 int count, u8 *buf) 408{ 409 return regmap_bulk_read(as3722->regmap, reg, buf, count); 410} 411 412static inline int as3722_block_write(struct as3722 *as3722, u32 reg, 413 int count, u8 *data) 414{ 415 return regmap_bulk_write(as3722->regmap, reg, data, count); 416} 417 418static inline int as3722_update_bits(struct as3722 *as3722, u32 reg, 419 u32 mask, u8 val) 420{ 421 return regmap_update_bits(as3722->regmap, reg, mask, val); 422} 423 424static inline int as3722_irq_get_virq(struct as3722 *as3722, int irq) 425{ 426 return regmap_irq_get_virq(as3722->irq_data, irq); 427} 428#endif /* __LINUX_MFD_AS3722_H__ */ 429