1/* 2 * Generic EDAC defs 3 * 4 * Author: Dave Jiang <djiang@mvista.com> 5 * 6 * 2006-2008 (c) MontaVista Software, Inc. This file is licensed under 7 * the terms of the GNU General Public License version 2. This program 8 * is licensed "as is" without any warranty of any kind, whether express 9 * or implied. 10 * 11 */ 12#ifndef _LINUX_EDAC_H_ 13#define _LINUX_EDAC_H_ 14 15#include <linux/atomic.h> 16#include <linux/device.h> 17#include <linux/completion.h> 18#include <linux/workqueue.h> 19#include <linux/debugfs.h> 20 21struct device; 22 23#define EDAC_OPSTATE_INVAL -1 24#define EDAC_OPSTATE_POLL 0 25#define EDAC_OPSTATE_NMI 1 26#define EDAC_OPSTATE_INT 2 27 28extern int edac_op_state; 29extern int edac_err_assert; 30extern atomic_t edac_handlers; 31extern struct bus_type edac_subsys; 32 33extern int edac_handler_set(void); 34extern void edac_atomic_assert_error(void); 35extern struct bus_type *edac_get_sysfs_subsys(void); 36extern void edac_put_sysfs_subsys(void); 37 38enum { 39 EDAC_REPORTING_ENABLED, 40 EDAC_REPORTING_DISABLED, 41 EDAC_REPORTING_FORCE 42}; 43 44extern int edac_report_status; 45#ifdef CONFIG_EDAC 46static inline int get_edac_report_status(void) 47{ 48 return edac_report_status; 49} 50 51static inline void set_edac_report_status(int new) 52{ 53 edac_report_status = new; 54} 55#else 56static inline int get_edac_report_status(void) 57{ 58 return EDAC_REPORTING_DISABLED; 59} 60 61static inline void set_edac_report_status(int new) 62{ 63} 64#endif 65 66static inline void opstate_init(void) 67{ 68 switch (edac_op_state) { 69 case EDAC_OPSTATE_POLL: 70 case EDAC_OPSTATE_NMI: 71 break; 72 default: 73 edac_op_state = EDAC_OPSTATE_POLL; 74 } 75 return; 76} 77 78/* Max length of a DIMM label*/ 79#define EDAC_MC_LABEL_LEN 31 80 81/* Maximum size of the location string */ 82#define LOCATION_SIZE 256 83 84/* Defines the maximum number of labels that can be reported */ 85#define EDAC_MAX_LABELS 8 86 87/* String used to join two or more labels */ 88#define OTHER_LABEL " or " 89 90/** 91 * enum dev_type - describe the type of memory DRAM chips used at the stick 92 * @DEV_UNKNOWN: Can't be determined, or MC doesn't support detect it 93 * @DEV_X1: 1 bit for data 94 * @DEV_X2: 2 bits for data 95 * @DEV_X4: 4 bits for data 96 * @DEV_X8: 8 bits for data 97 * @DEV_X16: 16 bits for data 98 * @DEV_X32: 32 bits for data 99 * @DEV_X64: 64 bits for data 100 * 101 * Typical values are x4 and x8. 102 */ 103enum dev_type { 104 DEV_UNKNOWN = 0, 105 DEV_X1, 106 DEV_X2, 107 DEV_X4, 108 DEV_X8, 109 DEV_X16, 110 DEV_X32, /* Do these parts exist? */ 111 DEV_X64 /* Do these parts exist? */ 112}; 113 114#define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN) 115#define DEV_FLAG_X1 BIT(DEV_X1) 116#define DEV_FLAG_X2 BIT(DEV_X2) 117#define DEV_FLAG_X4 BIT(DEV_X4) 118#define DEV_FLAG_X8 BIT(DEV_X8) 119#define DEV_FLAG_X16 BIT(DEV_X16) 120#define DEV_FLAG_X32 BIT(DEV_X32) 121#define DEV_FLAG_X64 BIT(DEV_X64) 122 123/** 124 * enum hw_event_mc_err_type - type of the detected error 125 * 126 * @HW_EVENT_ERR_CORRECTED: Corrected Error - Indicates that an ECC 127 * corrected error was detected 128 * @HW_EVENT_ERR_UNCORRECTED: Uncorrected Error - Indicates an error that 129 * can't be corrected by ECC, but it is not 130 * fatal (maybe it is on an unused memory area, 131 * or the memory controller could recover from 132 * it for example, by re-trying the operation). 133 * @HW_EVENT_ERR_FATAL: Fatal Error - Uncorrected error that could not 134 * be recovered. 135 */ 136enum hw_event_mc_err_type { 137 HW_EVENT_ERR_CORRECTED, 138 HW_EVENT_ERR_UNCORRECTED, 139 HW_EVENT_ERR_FATAL, 140 HW_EVENT_ERR_INFO, 141}; 142 143static inline char *mc_event_error_type(const unsigned int err_type) 144{ 145 switch (err_type) { 146 case HW_EVENT_ERR_CORRECTED: 147 return "Corrected"; 148 case HW_EVENT_ERR_UNCORRECTED: 149 return "Uncorrected"; 150 case HW_EVENT_ERR_FATAL: 151 return "Fatal"; 152 default: 153 case HW_EVENT_ERR_INFO: 154 return "Info"; 155 } 156} 157 158/** 159 * enum mem_type - memory types. For a more detailed reference, please see 160 * http://en.wikipedia.org/wiki/DRAM 161 * 162 * @MEM_EMPTY Empty csrow 163 * @MEM_RESERVED: Reserved csrow type 164 * @MEM_UNKNOWN: Unknown csrow type 165 * @MEM_FPM: FPM - Fast Page Mode, used on systems up to 1995. 166 * @MEM_EDO: EDO - Extended data out, used on systems up to 1998. 167 * @MEM_BEDO: BEDO - Burst Extended data out, an EDO variant. 168 * @MEM_SDR: SDR - Single data rate SDRAM 169 * http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory 170 * They use 3 pins for chip select: Pins 0 and 2 are 171 * for rank 0; pins 1 and 3 are for rank 1, if the memory 172 * is dual-rank. 173 * @MEM_RDR: Registered SDR SDRAM 174 * @MEM_DDR: Double data rate SDRAM 175 * http://en.wikipedia.org/wiki/DDR_SDRAM 176 * @MEM_RDDR: Registered Double data rate SDRAM 177 * This is a variant of the DDR memories. 178 * A registered memory has a buffer inside it, hiding 179 * part of the memory details to the memory controller. 180 * @MEM_RMBS: Rambus DRAM, used on a few Pentium III/IV controllers. 181 * @MEM_DDR2: DDR2 RAM, as described at JEDEC JESD79-2F. 182 * Those memories are labed as "PC2-" instead of "PC" to 183 * differenciate from DDR. 184 * @MEM_FB_DDR2: Fully-Buffered DDR2, as described at JEDEC Std No. 205 185 * and JESD206. 186 * Those memories are accessed per DIMM slot, and not by 187 * a chip select signal. 188 * @MEM_RDDR2: Registered DDR2 RAM 189 * This is a variant of the DDR2 memories. 190 * @MEM_XDR: Rambus XDR 191 * It is an evolution of the original RAMBUS memories, 192 * created to compete with DDR2. Weren't used on any 193 * x86 arch, but cell_edac PPC memory controller uses it. 194 * @MEM_DDR3: DDR3 RAM 195 * @MEM_RDDR3: Registered DDR3 RAM 196 * This is a variant of the DDR3 memories. 197 * @MEM_LRDDR3 Load-Reduced DDR3 memory. 198 * @MEM_DDR4: Unbuffered DDR4 RAM 199 * @MEM_RDDR4: Registered DDR4 RAM 200 * This is a variant of the DDR4 memories. 201 */ 202enum mem_type { 203 MEM_EMPTY = 0, 204 MEM_RESERVED, 205 MEM_UNKNOWN, 206 MEM_FPM, 207 MEM_EDO, 208 MEM_BEDO, 209 MEM_SDR, 210 MEM_RDR, 211 MEM_DDR, 212 MEM_RDDR, 213 MEM_RMBS, 214 MEM_DDR2, 215 MEM_FB_DDR2, 216 MEM_RDDR2, 217 MEM_XDR, 218 MEM_DDR3, 219 MEM_RDDR3, 220 MEM_LRDDR3, 221 MEM_DDR4, 222 MEM_RDDR4, 223}; 224 225#define MEM_FLAG_EMPTY BIT(MEM_EMPTY) 226#define MEM_FLAG_RESERVED BIT(MEM_RESERVED) 227#define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN) 228#define MEM_FLAG_FPM BIT(MEM_FPM) 229#define MEM_FLAG_EDO BIT(MEM_EDO) 230#define MEM_FLAG_BEDO BIT(MEM_BEDO) 231#define MEM_FLAG_SDR BIT(MEM_SDR) 232#define MEM_FLAG_RDR BIT(MEM_RDR) 233#define MEM_FLAG_DDR BIT(MEM_DDR) 234#define MEM_FLAG_RDDR BIT(MEM_RDDR) 235#define MEM_FLAG_RMBS BIT(MEM_RMBS) 236#define MEM_FLAG_DDR2 BIT(MEM_DDR2) 237#define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2) 238#define MEM_FLAG_RDDR2 BIT(MEM_RDDR2) 239#define MEM_FLAG_XDR BIT(MEM_XDR) 240#define MEM_FLAG_DDR3 BIT(MEM_DDR3) 241#define MEM_FLAG_RDDR3 BIT(MEM_RDDR3) 242 243/** 244 * enum edac-type - Error Detection and Correction capabilities and mode 245 * @EDAC_UNKNOWN: Unknown if ECC is available 246 * @EDAC_NONE: Doesn't support ECC 247 * @EDAC_RESERVED: Reserved ECC type 248 * @EDAC_PARITY: Detects parity errors 249 * @EDAC_EC: Error Checking - no correction 250 * @EDAC_SECDED: Single bit error correction, Double detection 251 * @EDAC_S2ECD2ED: Chipkill x2 devices - do these exist? 252 * @EDAC_S4ECD4ED: Chipkill x4 devices 253 * @EDAC_S8ECD8ED: Chipkill x8 devices 254 * @EDAC_S16ECD16ED: Chipkill x16 devices 255 */ 256enum edac_type { 257 EDAC_UNKNOWN = 0, 258 EDAC_NONE, 259 EDAC_RESERVED, 260 EDAC_PARITY, 261 EDAC_EC, 262 EDAC_SECDED, 263 EDAC_S2ECD2ED, 264 EDAC_S4ECD4ED, 265 EDAC_S8ECD8ED, 266 EDAC_S16ECD16ED, 267}; 268 269#define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN) 270#define EDAC_FLAG_NONE BIT(EDAC_NONE) 271#define EDAC_FLAG_PARITY BIT(EDAC_PARITY) 272#define EDAC_FLAG_EC BIT(EDAC_EC) 273#define EDAC_FLAG_SECDED BIT(EDAC_SECDED) 274#define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED) 275#define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED) 276#define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED) 277#define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED) 278 279/** 280 * enum scrub_type - scrubbing capabilities 281 * @SCRUB_UNKNOWN Unknown if scrubber is available 282 * @SCRUB_NONE: No scrubber 283 * @SCRUB_SW_PROG: SW progressive (sequential) scrubbing 284 * @SCRUB_SW_SRC: Software scrub only errors 285 * @SCRUB_SW_PROG_SRC: Progressive software scrub from an error 286 * @SCRUB_SW_TUNABLE: Software scrub frequency is tunable 287 * @SCRUB_HW_PROG: HW progressive (sequential) scrubbing 288 * @SCRUB_HW_SRC: Hardware scrub only errors 289 * @SCRUB_HW_PROG_SRC: Progressive hardware scrub from an error 290 * SCRUB_HW_TUNABLE: Hardware scrub frequency is tunable 291 */ 292enum scrub_type { 293 SCRUB_UNKNOWN = 0, 294 SCRUB_NONE, 295 SCRUB_SW_PROG, 296 SCRUB_SW_SRC, 297 SCRUB_SW_PROG_SRC, 298 SCRUB_SW_TUNABLE, 299 SCRUB_HW_PROG, 300 SCRUB_HW_SRC, 301 SCRUB_HW_PROG_SRC, 302 SCRUB_HW_TUNABLE 303}; 304 305#define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG) 306#define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC) 307#define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC) 308#define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE) 309#define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG) 310#define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC) 311#define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC) 312#define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE) 313 314/* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */ 315 316/* EDAC internal operation states */ 317#define OP_ALLOC 0x100 318#define OP_RUNNING_POLL 0x201 319#define OP_RUNNING_INTERRUPT 0x202 320#define OP_RUNNING_POLL_INTR 0x203 321#define OP_OFFLINE 0x300 322 323/* 324 * Concepts used at the EDAC subsystem 325 * 326 * There are several things to be aware of that aren't at all obvious: 327 * 328 * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc.. 329 * 330 * These are some of the many terms that are thrown about that don't always 331 * mean what people think they mean (Inconceivable!). In the interest of 332 * creating a common ground for discussion, terms and their definitions 333 * will be established. 334 * 335 * Memory devices: The individual DRAM chips on a memory stick. These 336 * devices commonly output 4 and 8 bits each (x4, x8). 337 * Grouping several of these in parallel provides the 338 * number of bits that the memory controller expects: 339 * typically 72 bits, in order to provide 64 bits + 340 * 8 bits of ECC data. 341 * 342 * Memory Stick: A printed circuit board that aggregates multiple 343 * memory devices in parallel. In general, this is the 344 * Field Replaceable Unit (FRU) which gets replaced, in 345 * the case of excessive errors. Most often it is also 346 * called DIMM (Dual Inline Memory Module). 347 * 348 * Memory Socket: A physical connector on the motherboard that accepts 349 * a single memory stick. Also called as "slot" on several 350 * datasheets. 351 * 352 * Channel: A memory controller channel, responsible to communicate 353 * with a group of DIMMs. Each channel has its own 354 * independent control (command) and data bus, and can 355 * be used independently or grouped with other channels. 356 * 357 * Branch: It is typically the highest hierarchy on a 358 * Fully-Buffered DIMM memory controller. 359 * Typically, it contains two channels. 360 * Two channels at the same branch can be used in single 361 * mode or in lockstep mode. 362 * When lockstep is enabled, the cacheline is doubled, 363 * but it generally brings some performance penalty. 364 * Also, it is generally not possible to point to just one 365 * memory stick when an error occurs, as the error 366 * correction code is calculated using two DIMMs instead 367 * of one. Due to that, it is capable of correcting more 368 * errors than on single mode. 369 * 370 * Single-channel: The data accessed by the memory controller is contained 371 * into one dimm only. E. g. if the data is 64 bits-wide, 372 * the data flows to the CPU using one 64 bits parallel 373 * access. 374 * Typically used with SDR, DDR, DDR2 and DDR3 memories. 375 * FB-DIMM and RAMBUS use a different concept for channel, 376 * so this concept doesn't apply there. 377 * 378 * Double-channel: The data size accessed by the memory controller is 379 * interlaced into two dimms, accessed at the same time. 380 * E. g. if the DIMM is 64 bits-wide (72 bits with ECC), 381 * the data flows to the CPU using a 128 bits parallel 382 * access. 383 * 384 * Chip-select row: This is the name of the DRAM signal used to select the 385 * DRAM ranks to be accessed. Common chip-select rows for 386 * single channel are 64 bits, for dual channel 128 bits. 387 * It may not be visible by the memory controller, as some 388 * DIMM types have a memory buffer that can hide direct 389 * access to it from the Memory Controller. 390 * 391 * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memory. 392 * Motherboards commonly drive two chip-select pins to 393 * a memory stick. A single-ranked stick, will occupy 394 * only one of those rows. The other will be unused. 395 * 396 * Double-Ranked stick: A double-ranked stick has two chip-select rows which 397 * access different sets of memory devices. The two 398 * rows cannot be accessed concurrently. 399 * 400 * Double-sided stick: DEPRECATED TERM, see Double-Ranked stick. 401 * A double-sided stick has two chip-select rows which 402 * access different sets of memory devices. The two 403 * rows cannot be accessed concurrently. "Double-sided" 404 * is irrespective of the memory devices being mounted 405 * on both sides of the memory stick. 406 * 407 * Socket set: All of the memory sticks that are required for 408 * a single memory access or all of the memory sticks 409 * spanned by a chip-select row. A single socket set 410 * has two chip-select rows and if double-sided sticks 411 * are used these will occupy those chip-select rows. 412 * 413 * Bank: This term is avoided because it is unclear when 414 * needing to distinguish between chip-select rows and 415 * socket sets. 416 * 417 * Controller pages: 418 * 419 * Physical pages: 420 * 421 * Virtual pages: 422 * 423 * 424 * STRUCTURE ORGANIZATION AND CHOICES 425 * 426 * 427 * 428 * PS - I enjoyed writing all that about as much as you enjoyed reading it. 429 */ 430 431/** 432 * enum edac_mc_layer - memory controller hierarchy layer 433 * 434 * @EDAC_MC_LAYER_BRANCH: memory layer is named "branch" 435 * @EDAC_MC_LAYER_CHANNEL: memory layer is named "channel" 436 * @EDAC_MC_LAYER_SLOT: memory layer is named "slot" 437 * @EDAC_MC_LAYER_CHIP_SELECT: memory layer is named "chip select" 438 * @EDAC_MC_LAYER_ALL_MEM: memory layout is unknown. All memory is mapped 439 * as a single memory area. This is used when 440 * retrieving errors from a firmware driven driver. 441 * 442 * This enum is used by the drivers to tell edac_mc_sysfs what name should 443 * be used when describing a memory stick location. 444 */ 445enum edac_mc_layer_type { 446 EDAC_MC_LAYER_BRANCH, 447 EDAC_MC_LAYER_CHANNEL, 448 EDAC_MC_LAYER_SLOT, 449 EDAC_MC_LAYER_CHIP_SELECT, 450 EDAC_MC_LAYER_ALL_MEM, 451}; 452 453/** 454 * struct edac_mc_layer - describes the memory controller hierarchy 455 * @layer: layer type 456 * @size: number of components per layer. For example, 457 * if the channel layer has two channels, size = 2 458 * @is_virt_csrow: This layer is part of the "csrow" when old API 459 * compatibility mode is enabled. Otherwise, it is 460 * a channel 461 */ 462struct edac_mc_layer { 463 enum edac_mc_layer_type type; 464 unsigned size; 465 bool is_virt_csrow; 466}; 467 468/* 469 * Maximum number of layers used by the memory controller to uniquely 470 * identify a single memory stick. 471 * NOTE: Changing this constant requires not only to change the constant 472 * below, but also to change the existing code at the core, as there are 473 * some code there that are optimized for 3 layers. 474 */ 475#define EDAC_MAX_LAYERS 3 476 477/** 478 * EDAC_DIMM_OFF - Macro responsible to get a pointer offset inside a pointer array 479 * for the element given by [layer0,layer1,layer2] position 480 * 481 * @layers: a struct edac_mc_layer array, describing how many elements 482 * were allocated for each layer 483 * @n_layers: Number of layers at the @layers array 484 * @layer0: layer0 position 485 * @layer1: layer1 position. Unused if n_layers < 2 486 * @layer2: layer2 position. Unused if n_layers < 3 487 * 488 * For 1 layer, this macro returns &var[layer0] - &var 489 * For 2 layers, this macro is similar to allocate a bi-dimensional array 490 * and to return "&var[layer0][layer1] - &var" 491 * For 3 layers, this macro is similar to allocate a tri-dimensional array 492 * and to return "&var[layer0][layer1][layer2] - &var" 493 * 494 * A loop could be used here to make it more generic, but, as we only have 495 * 3 layers, this is a little faster. 496 * By design, layers can never be 0 or more than 3. If that ever happens, 497 * a NULL is returned, causing an OOPS during the memory allocation routine, 498 * with would point to the developer that he's doing something wrong. 499 */ 500#define EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2) ({ \ 501 int __i; \ 502 if ((nlayers) == 1) \ 503 __i = layer0; \ 504 else if ((nlayers) == 2) \ 505 __i = (layer1) + ((layers[1]).size * (layer0)); \ 506 else if ((nlayers) == 3) \ 507 __i = (layer2) + ((layers[2]).size * ((layer1) + \ 508 ((layers[1]).size * (layer0)))); \ 509 else \ 510 __i = -EINVAL; \ 511 __i; \ 512}) 513 514/** 515 * EDAC_DIMM_PTR - Macro responsible to get a pointer inside a pointer array 516 * for the element given by [layer0,layer1,layer2] position 517 * 518 * @layers: a struct edac_mc_layer array, describing how many elements 519 * were allocated for each layer 520 * @var: name of the var where we want to get the pointer 521 * (like mci->dimms) 522 * @n_layers: Number of layers at the @layers array 523 * @layer0: layer0 position 524 * @layer1: layer1 position. Unused if n_layers < 2 525 * @layer2: layer2 position. Unused if n_layers < 3 526 * 527 * For 1 layer, this macro returns &var[layer0] 528 * For 2 layers, this macro is similar to allocate a bi-dimensional array 529 * and to return "&var[layer0][layer1]" 530 * For 3 layers, this macro is similar to allocate a tri-dimensional array 531 * and to return "&var[layer0][layer1][layer2]" 532 */ 533#define EDAC_DIMM_PTR(layers, var, nlayers, layer0, layer1, layer2) ({ \ 534 typeof(*var) __p; \ 535 int ___i = EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2); \ 536 if (___i < 0) \ 537 __p = NULL; \ 538 else \ 539 __p = (var)[___i]; \ 540 __p; \ 541}) 542 543struct dimm_info { 544 struct device dev; 545 546 char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */ 547 548 /* Memory location data */ 549 unsigned location[EDAC_MAX_LAYERS]; 550 551 struct mem_ctl_info *mci; /* the parent */ 552 553 u32 grain; /* granularity of reported error in bytes */ 554 enum dev_type dtype; /* memory device type */ 555 enum mem_type mtype; /* memory dimm type */ 556 enum edac_type edac_mode; /* EDAC mode for this dimm */ 557 558 u32 nr_pages; /* number of pages on this dimm */ 559 560 unsigned csrow, cschannel; /* Points to the old API data */ 561}; 562 563/** 564 * struct rank_info - contains the information for one DIMM rank 565 * 566 * @chan_idx: channel number where the rank is (typically, 0 or 1) 567 * @ce_count: number of correctable errors for this rank 568 * @csrow: A pointer to the chip select row structure (the parent 569 * structure). The location of the rank is given by 570 * the (csrow->csrow_idx, chan_idx) vector. 571 * @dimm: A pointer to the DIMM structure, where the DIMM label 572 * information is stored. 573 * 574 * FIXME: Currently, the EDAC core model will assume one DIMM per rank. 575 * This is a bad assumption, but it makes this patch easier. Later 576 * patches in this series will fix this issue. 577 */ 578struct rank_info { 579 int chan_idx; 580 struct csrow_info *csrow; 581 struct dimm_info *dimm; 582 583 u32 ce_count; /* Correctable Errors for this csrow */ 584}; 585 586struct csrow_info { 587 struct device dev; 588 589 /* Used only by edac_mc_find_csrow_by_page() */ 590 unsigned long first_page; /* first page number in csrow */ 591 unsigned long last_page; /* last page number in csrow */ 592 unsigned long page_mask; /* used for interleaving - 593 * 0UL for non intlv */ 594 595 int csrow_idx; /* the chip-select row */ 596 597 u32 ue_count; /* Uncorrectable Errors for this csrow */ 598 u32 ce_count; /* Correctable Errors for this csrow */ 599 600 struct mem_ctl_info *mci; /* the parent */ 601 602 /* channel information for this csrow */ 603 u32 nr_channels; 604 struct rank_info **channels; 605}; 606 607/* 608 * struct errcount_attribute - used to store the several error counts 609 */ 610struct errcount_attribute_data { 611 int n_layers; 612 int pos[EDAC_MAX_LAYERS]; 613 int layer0, layer1, layer2; 614}; 615 616/** 617 * edac_raw_error_desc - Raw error report structure 618 * @grain: minimum granularity for an error report, in bytes 619 * @error_count: number of errors of the same type 620 * @top_layer: top layer of the error (layer[0]) 621 * @mid_layer: middle layer of the error (layer[1]) 622 * @low_layer: low layer of the error (layer[2]) 623 * @page_frame_number: page where the error happened 624 * @offset_in_page: page offset 625 * @syndrome: syndrome of the error (or 0 if unknown or if 626 * the syndrome is not applicable) 627 * @msg: error message 628 * @location: location of the error 629 * @label: label of the affected DIMM(s) 630 * @other_detail: other driver-specific detail about the error 631 * @enable_per_layer_report: if false, the error affects all layers 632 * (typically, a memory controller error) 633 */ 634struct edac_raw_error_desc { 635 /* 636 * NOTE: everything before grain won't be cleaned by 637 * edac_raw_error_desc_clean() 638 */ 639 char location[LOCATION_SIZE]; 640 char label[(EDAC_MC_LABEL_LEN + 1 + sizeof(OTHER_LABEL)) * EDAC_MAX_LABELS]; 641 long grain; 642 643 /* the vars below and grain will be cleaned on every new error report */ 644 u16 error_count; 645 int top_layer; 646 int mid_layer; 647 int low_layer; 648 unsigned long page_frame_number; 649 unsigned long offset_in_page; 650 unsigned long syndrome; 651 const char *msg; 652 const char *other_detail; 653 bool enable_per_layer_report; 654}; 655 656/* MEMORY controller information structure 657 */ 658struct mem_ctl_info { 659 struct device dev; 660 struct bus_type *bus; 661 662 struct list_head link; /* for global list of mem_ctl_info structs */ 663 664 struct module *owner; /* Module owner of this control struct */ 665 666 unsigned long mtype_cap; /* memory types supported by mc */ 667 unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */ 668 unsigned long edac_cap; /* configuration capabilities - this is 669 * closely related to edac_ctl_cap. The 670 * difference is that the controller may be 671 * capable of s4ecd4ed which would be listed 672 * in edac_ctl_cap, but if channels aren't 673 * capable of s4ecd4ed then the edac_cap would 674 * not have that capability. 675 */ 676 unsigned long scrub_cap; /* chipset scrub capabilities */ 677 enum scrub_type scrub_mode; /* current scrub mode */ 678 679 /* Translates sdram memory scrub rate given in bytes/sec to the 680 internal representation and configures whatever else needs 681 to be configured. 682 */ 683 int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 bw); 684 685 /* Get the current sdram memory scrub rate from the internal 686 representation and converts it to the closest matching 687 bandwidth in bytes/sec. 688 */ 689 int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci); 690 691 692 /* pointer to edac checking routine */ 693 void (*edac_check) (struct mem_ctl_info * mci); 694 695 /* 696 * Remaps memory pages: controller pages to physical pages. 697 * For most MC's, this will be NULL. 698 */ 699 /* FIXME - why not send the phys page to begin with? */ 700 unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci, 701 unsigned long page); 702 int mc_idx; 703 struct csrow_info **csrows; 704 unsigned nr_csrows, num_cschannel; 705 706 /* 707 * Memory Controller hierarchy 708 * 709 * There are basically two types of memory controller: the ones that 710 * sees memory sticks ("dimms"), and the ones that sees memory ranks. 711 * All old memory controllers enumerate memories per rank, but most 712 * of the recent drivers enumerate memories per DIMM, instead. 713 * When the memory controller is per rank, csbased is true. 714 */ 715 unsigned n_layers; 716 struct edac_mc_layer *layers; 717 bool csbased; 718 719 /* 720 * DIMM info. Will eventually remove the entire csrows_info some day 721 */ 722 unsigned tot_dimms; 723 struct dimm_info **dimms; 724 725 /* 726 * FIXME - what about controllers on other busses? - IDs must be 727 * unique. dev pointer should be sufficiently unique, but 728 * BUS:SLOT.FUNC numbers may not be unique. 729 */ 730 struct device *pdev; 731 const char *mod_name; 732 const char *mod_ver; 733 const char *ctl_name; 734 const char *dev_name; 735 void *pvt_info; 736 unsigned long start_time; /* mci load start time (in jiffies) */ 737 738 /* 739 * drivers shouldn't access those fields directly, as the core 740 * already handles that. 741 */ 742 u32 ce_noinfo_count, ue_noinfo_count; 743 u32 ue_mc, ce_mc; 744 u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS]; 745 746 struct completion complete; 747 748 /* Additional top controller level attributes, but specified 749 * by the low level driver. 750 * 751 * Set by the low level driver to provide attributes at the 752 * controller level. 753 * An array of structures, NULL terminated 754 * 755 * If attributes are desired, then set to array of attributes 756 * If no attributes are desired, leave NULL 757 */ 758 const struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes; 759 760 /* work struct for this MC */ 761 struct delayed_work work; 762 763 /* 764 * Used to report an error - by being at the global struct 765 * makes the memory allocated by the EDAC core 766 */ 767 struct edac_raw_error_desc error_desc; 768 769 /* the internal state of this controller instance */ 770 int op_state; 771 772#ifdef CONFIG_EDAC_DEBUG 773 struct dentry *debugfs; 774 u8 fake_inject_layer[EDAC_MAX_LAYERS]; 775 u32 fake_inject_ue; 776 u16 fake_inject_count; 777#endif 778}; 779 780/* 781 * Maximum number of memory controllers in the coherent fabric. 782 */ 783#define EDAC_MAX_MCS 16 784 785#endif 786