1#ifndef __INCLUDE_ATMEL_SSC_H 2#define __INCLUDE_ATMEL_SSC_H 3 4#include <linux/platform_device.h> 5#include <linux/list.h> 6#include <linux/io.h> 7 8struct atmel_ssc_platform_data { 9 int use_dma; 10 int has_fslen_ext; 11}; 12 13struct ssc_device { 14 struct list_head list; 15 dma_addr_t phybase; 16 void __iomem *regs; 17 struct platform_device *pdev; 18 struct atmel_ssc_platform_data *pdata; 19 struct clk *clk; 20 int user; 21 int irq; 22 bool clk_from_rk_pin; 23}; 24 25struct ssc_device * __must_check ssc_request(unsigned int ssc_num); 26void ssc_free(struct ssc_device *ssc); 27 28/* SSC register offsets */ 29 30/* SSC Control Register */ 31#define SSC_CR 0x00000000 32#define SSC_CR_RXDIS_SIZE 1 33#define SSC_CR_RXDIS_OFFSET 1 34#define SSC_CR_RXEN_SIZE 1 35#define SSC_CR_RXEN_OFFSET 0 36#define SSC_CR_SWRST_SIZE 1 37#define SSC_CR_SWRST_OFFSET 15 38#define SSC_CR_TXDIS_SIZE 1 39#define SSC_CR_TXDIS_OFFSET 9 40#define SSC_CR_TXEN_SIZE 1 41#define SSC_CR_TXEN_OFFSET 8 42 43/* SSC Clock Mode Register */ 44#define SSC_CMR 0x00000004 45#define SSC_CMR_DIV_SIZE 12 46#define SSC_CMR_DIV_OFFSET 0 47 48/* SSC Receive Clock Mode Register */ 49#define SSC_RCMR 0x00000010 50#define SSC_RCMR_CKG_SIZE 2 51#define SSC_RCMR_CKG_OFFSET 6 52#define SSC_RCMR_CKI_SIZE 1 53#define SSC_RCMR_CKI_OFFSET 5 54#define SSC_RCMR_CKO_SIZE 3 55#define SSC_RCMR_CKO_OFFSET 2 56#define SSC_RCMR_CKS_SIZE 2 57#define SSC_RCMR_CKS_OFFSET 0 58#define SSC_RCMR_PERIOD_SIZE 8 59#define SSC_RCMR_PERIOD_OFFSET 24 60#define SSC_RCMR_START_SIZE 4 61#define SSC_RCMR_START_OFFSET 8 62#define SSC_RCMR_STOP_SIZE 1 63#define SSC_RCMR_STOP_OFFSET 12 64#define SSC_RCMR_STTDLY_SIZE 8 65#define SSC_RCMR_STTDLY_OFFSET 16 66 67/* SSC Receive Frame Mode Register */ 68#define SSC_RFMR 0x00000014 69#define SSC_RFMR_DATLEN_SIZE 5 70#define SSC_RFMR_DATLEN_OFFSET 0 71#define SSC_RFMR_DATNB_SIZE 4 72#define SSC_RFMR_DATNB_OFFSET 8 73#define SSC_RFMR_FSEDGE_SIZE 1 74#define SSC_RFMR_FSEDGE_OFFSET 24 75/* 76 * The FSLEN_EXT exist on at91sam9rl, at91sam9g10, 77 * at91sam9g20, and at91sam9g45 and newer SoCs 78 */ 79#define SSC_RFMR_FSLEN_EXT_SIZE 4 80#define SSC_RFMR_FSLEN_EXT_OFFSET 28 81#define SSC_RFMR_FSLEN_SIZE 4 82#define SSC_RFMR_FSLEN_OFFSET 16 83#define SSC_RFMR_FSOS_SIZE 4 84#define SSC_RFMR_FSOS_OFFSET 20 85#define SSC_RFMR_LOOP_SIZE 1 86#define SSC_RFMR_LOOP_OFFSET 5 87#define SSC_RFMR_MSBF_SIZE 1 88#define SSC_RFMR_MSBF_OFFSET 7 89 90/* SSC Transmit Clock Mode Register */ 91#define SSC_TCMR 0x00000018 92#define SSC_TCMR_CKG_SIZE 2 93#define SSC_TCMR_CKG_OFFSET 6 94#define SSC_TCMR_CKI_SIZE 1 95#define SSC_TCMR_CKI_OFFSET 5 96#define SSC_TCMR_CKO_SIZE 3 97#define SSC_TCMR_CKO_OFFSET 2 98#define SSC_TCMR_CKS_SIZE 2 99#define SSC_TCMR_CKS_OFFSET 0 100#define SSC_TCMR_PERIOD_SIZE 8 101#define SSC_TCMR_PERIOD_OFFSET 24 102#define SSC_TCMR_START_SIZE 4 103#define SSC_TCMR_START_OFFSET 8 104#define SSC_TCMR_STTDLY_SIZE 8 105#define SSC_TCMR_STTDLY_OFFSET 16 106 107/* SSC Transmit Frame Mode Register */ 108#define SSC_TFMR 0x0000001c 109#define SSC_TFMR_DATDEF_SIZE 1 110#define SSC_TFMR_DATDEF_OFFSET 5 111#define SSC_TFMR_DATLEN_SIZE 5 112#define SSC_TFMR_DATLEN_OFFSET 0 113#define SSC_TFMR_DATNB_SIZE 4 114#define SSC_TFMR_DATNB_OFFSET 8 115#define SSC_TFMR_FSDEN_SIZE 1 116#define SSC_TFMR_FSDEN_OFFSET 23 117#define SSC_TFMR_FSEDGE_SIZE 1 118#define SSC_TFMR_FSEDGE_OFFSET 24 119/* 120 * The FSLEN_EXT exist on at91sam9rl, at91sam9g10, 121 * at91sam9g20, and at91sam9g45 and newer SoCs 122 */ 123#define SSC_TFMR_FSLEN_EXT_SIZE 4 124#define SSC_TFMR_FSLEN_EXT_OFFSET 28 125#define SSC_TFMR_FSLEN_SIZE 4 126#define SSC_TFMR_FSLEN_OFFSET 16 127#define SSC_TFMR_FSOS_SIZE 3 128#define SSC_TFMR_FSOS_OFFSET 20 129#define SSC_TFMR_MSBF_SIZE 1 130#define SSC_TFMR_MSBF_OFFSET 7 131 132/* SSC Receive Hold Register */ 133#define SSC_RHR 0x00000020 134#define SSC_RHR_RDAT_SIZE 32 135#define SSC_RHR_RDAT_OFFSET 0 136 137/* SSC Transmit Hold Register */ 138#define SSC_THR 0x00000024 139#define SSC_THR_TDAT_SIZE 32 140#define SSC_THR_TDAT_OFFSET 0 141 142/* SSC Receive Sync. Holding Register */ 143#define SSC_RSHR 0x00000030 144#define SSC_RSHR_RSDAT_SIZE 16 145#define SSC_RSHR_RSDAT_OFFSET 0 146 147/* SSC Transmit Sync. Holding Register */ 148#define SSC_TSHR 0x00000034 149#define SSC_TSHR_TSDAT_SIZE 16 150#define SSC_TSHR_RSDAT_OFFSET 0 151 152/* SSC Receive Compare 0 Register */ 153#define SSC_RC0R 0x00000038 154#define SSC_RC0R_CP0_SIZE 16 155#define SSC_RC0R_CP0_OFFSET 0 156 157/* SSC Receive Compare 1 Register */ 158#define SSC_RC1R 0x0000003c 159#define SSC_RC1R_CP1_SIZE 16 160#define SSC_RC1R_CP1_OFFSET 0 161 162/* SSC Status Register */ 163#define SSC_SR 0x00000040 164#define SSC_SR_CP0_SIZE 1 165#define SSC_SR_CP0_OFFSET 8 166#define SSC_SR_CP1_SIZE 1 167#define SSC_SR_CP1_OFFSET 9 168#define SSC_SR_ENDRX_SIZE 1 169#define SSC_SR_ENDRX_OFFSET 6 170#define SSC_SR_ENDTX_SIZE 1 171#define SSC_SR_ENDTX_OFFSET 2 172#define SSC_SR_OVRUN_SIZE 1 173#define SSC_SR_OVRUN_OFFSET 5 174#define SSC_SR_RXBUFF_SIZE 1 175#define SSC_SR_RXBUFF_OFFSET 7 176#define SSC_SR_RXEN_SIZE 1 177#define SSC_SR_RXEN_OFFSET 17 178#define SSC_SR_RXRDY_SIZE 1 179#define SSC_SR_RXRDY_OFFSET 4 180#define SSC_SR_RXSYN_SIZE 1 181#define SSC_SR_RXSYN_OFFSET 11 182#define SSC_SR_TXBUFE_SIZE 1 183#define SSC_SR_TXBUFE_OFFSET 3 184#define SSC_SR_TXEMPTY_SIZE 1 185#define SSC_SR_TXEMPTY_OFFSET 1 186#define SSC_SR_TXEN_SIZE 1 187#define SSC_SR_TXEN_OFFSET 16 188#define SSC_SR_TXRDY_SIZE 1 189#define SSC_SR_TXRDY_OFFSET 0 190#define SSC_SR_TXSYN_SIZE 1 191#define SSC_SR_TXSYN_OFFSET 10 192 193/* SSC Interrupt Enable Register */ 194#define SSC_IER 0x00000044 195#define SSC_IER_CP0_SIZE 1 196#define SSC_IER_CP0_OFFSET 8 197#define SSC_IER_CP1_SIZE 1 198#define SSC_IER_CP1_OFFSET 9 199#define SSC_IER_ENDRX_SIZE 1 200#define SSC_IER_ENDRX_OFFSET 6 201#define SSC_IER_ENDTX_SIZE 1 202#define SSC_IER_ENDTX_OFFSET 2 203#define SSC_IER_OVRUN_SIZE 1 204#define SSC_IER_OVRUN_OFFSET 5 205#define SSC_IER_RXBUFF_SIZE 1 206#define SSC_IER_RXBUFF_OFFSET 7 207#define SSC_IER_RXRDY_SIZE 1 208#define SSC_IER_RXRDY_OFFSET 4 209#define SSC_IER_RXSYN_SIZE 1 210#define SSC_IER_RXSYN_OFFSET 11 211#define SSC_IER_TXBUFE_SIZE 1 212#define SSC_IER_TXBUFE_OFFSET 3 213#define SSC_IER_TXEMPTY_SIZE 1 214#define SSC_IER_TXEMPTY_OFFSET 1 215#define SSC_IER_TXRDY_SIZE 1 216#define SSC_IER_TXRDY_OFFSET 0 217#define SSC_IER_TXSYN_SIZE 1 218#define SSC_IER_TXSYN_OFFSET 10 219 220/* SSC Interrupt Disable Register */ 221#define SSC_IDR 0x00000048 222#define SSC_IDR_CP0_SIZE 1 223#define SSC_IDR_CP0_OFFSET 8 224#define SSC_IDR_CP1_SIZE 1 225#define SSC_IDR_CP1_OFFSET 9 226#define SSC_IDR_ENDRX_SIZE 1 227#define SSC_IDR_ENDRX_OFFSET 6 228#define SSC_IDR_ENDTX_SIZE 1 229#define SSC_IDR_ENDTX_OFFSET 2 230#define SSC_IDR_OVRUN_SIZE 1 231#define SSC_IDR_OVRUN_OFFSET 5 232#define SSC_IDR_RXBUFF_SIZE 1 233#define SSC_IDR_RXBUFF_OFFSET 7 234#define SSC_IDR_RXRDY_SIZE 1 235#define SSC_IDR_RXRDY_OFFSET 4 236#define SSC_IDR_RXSYN_SIZE 1 237#define SSC_IDR_RXSYN_OFFSET 11 238#define SSC_IDR_TXBUFE_SIZE 1 239#define SSC_IDR_TXBUFE_OFFSET 3 240#define SSC_IDR_TXEMPTY_SIZE 1 241#define SSC_IDR_TXEMPTY_OFFSET 1 242#define SSC_IDR_TXRDY_SIZE 1 243#define SSC_IDR_TXRDY_OFFSET 0 244#define SSC_IDR_TXSYN_SIZE 1 245#define SSC_IDR_TXSYN_OFFSET 10 246 247/* SSC Interrupt Mask Register */ 248#define SSC_IMR 0x0000004c 249#define SSC_IMR_CP0_SIZE 1 250#define SSC_IMR_CP0_OFFSET 8 251#define SSC_IMR_CP1_SIZE 1 252#define SSC_IMR_CP1_OFFSET 9 253#define SSC_IMR_ENDRX_SIZE 1 254#define SSC_IMR_ENDRX_OFFSET 6 255#define SSC_IMR_ENDTX_SIZE 1 256#define SSC_IMR_ENDTX_OFFSET 2 257#define SSC_IMR_OVRUN_SIZE 1 258#define SSC_IMR_OVRUN_OFFSET 5 259#define SSC_IMR_RXBUFF_SIZE 1 260#define SSC_IMR_RXBUFF_OFFSET 7 261#define SSC_IMR_RXRDY_SIZE 1 262#define SSC_IMR_RXRDY_OFFSET 4 263#define SSC_IMR_RXSYN_SIZE 1 264#define SSC_IMR_RXSYN_OFFSET 11 265#define SSC_IMR_TXBUFE_SIZE 1 266#define SSC_IMR_TXBUFE_OFFSET 3 267#define SSC_IMR_TXEMPTY_SIZE 1 268#define SSC_IMR_TXEMPTY_OFFSET 1 269#define SSC_IMR_TXRDY_SIZE 1 270#define SSC_IMR_TXRDY_OFFSET 0 271#define SSC_IMR_TXSYN_SIZE 1 272#define SSC_IMR_TXSYN_OFFSET 10 273 274/* SSC PDC Receive Pointer Register */ 275#define SSC_PDC_RPR 0x00000100 276 277/* SSC PDC Receive Counter Register */ 278#define SSC_PDC_RCR 0x00000104 279 280/* SSC PDC Transmit Pointer Register */ 281#define SSC_PDC_TPR 0x00000108 282 283/* SSC PDC Receive Next Pointer Register */ 284#define SSC_PDC_RNPR 0x00000110 285 286/* SSC PDC Receive Next Counter Register */ 287#define SSC_PDC_RNCR 0x00000114 288 289/* SSC PDC Transmit Counter Register */ 290#define SSC_PDC_TCR 0x0000010c 291 292/* SSC PDC Transmit Next Pointer Register */ 293#define SSC_PDC_TNPR 0x00000118 294 295/* SSC PDC Transmit Next Counter Register */ 296#define SSC_PDC_TNCR 0x0000011c 297 298/* SSC PDC Transfer Control Register */ 299#define SSC_PDC_PTCR 0x00000120 300#define SSC_PDC_PTCR_RXTDIS_SIZE 1 301#define SSC_PDC_PTCR_RXTDIS_OFFSET 1 302#define SSC_PDC_PTCR_RXTEN_SIZE 1 303#define SSC_PDC_PTCR_RXTEN_OFFSET 0 304#define SSC_PDC_PTCR_TXTDIS_SIZE 1 305#define SSC_PDC_PTCR_TXTDIS_OFFSET 9 306#define SSC_PDC_PTCR_TXTEN_SIZE 1 307#define SSC_PDC_PTCR_TXTEN_OFFSET 8 308 309/* SSC PDC Transfer Status Register */ 310#define SSC_PDC_PTSR 0x00000124 311#define SSC_PDC_PTSR_RXTEN_SIZE 1 312#define SSC_PDC_PTSR_RXTEN_OFFSET 0 313#define SSC_PDC_PTSR_TXTEN_SIZE 1 314#define SSC_PDC_PTSR_TXTEN_OFFSET 8 315 316/* Bit manipulation macros */ 317#define SSC_BIT(name) \ 318 (1 << SSC_##name##_OFFSET) 319#define SSC_BF(name, value) \ 320 (((value) & ((1 << SSC_##name##_SIZE) - 1)) \ 321 << SSC_##name##_OFFSET) 322#define SSC_BFEXT(name, value) \ 323 (((value) >> SSC_##name##_OFFSET) \ 324 & ((1 << SSC_##name##_SIZE) - 1)) 325#define SSC_BFINS(name, value, old) \ 326 (((old) & ~(((1 << SSC_##name##_SIZE) - 1) \ 327 << SSC_##name##_OFFSET)) | SSC_BF(name, value)) 328 329/* Register access macros */ 330#define ssc_readl(base, reg) __raw_readl(base + SSC_##reg) 331#define ssc_writel(base, reg, value) __raw_writel((value), base + SSC_##reg) 332 333#endif /* __INCLUDE_ATMEL_SSC_H */ 334