1/* 2 * This header provides constants for binding nvidia,tegra124-car or 3 * nvidia,tegra132-car. 4 * 5 * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB 6 * registers. These IDs often match those in the CAR's RST_DEVICES registers, 7 * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In 8 * this case, those clocks are assigned IDs above 185 in order to highlight 9 * this issue. Implementations that interpret these clock IDs as bit values 10 * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to 11 * explicitly handle these special cases. 12 * 13 * The balance of the clocks controlled by the CAR are assigned IDs of 185 and 14 * above. 15 */ 16 17#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H 18#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H 19 20/* 0 */ 21/* 1 */ 22/* 2 */ 23#define TEGRA124_CLK_ISPB 3 24#define TEGRA124_CLK_RTC 4 25#define TEGRA124_CLK_TIMER 5 26#define TEGRA124_CLK_UARTA 6 27/* 7 (register bit affects uartb and vfir) */ 28/* 8 */ 29#define TEGRA124_CLK_SDMMC2 9 30/* 10 (register bit affects spdif_in and spdif_out) */ 31#define TEGRA124_CLK_I2S1 11 32#define TEGRA124_CLK_I2C1 12 33/* 13 */ 34#define TEGRA124_CLK_SDMMC1 14 35#define TEGRA124_CLK_SDMMC4 15 36/* 16 */ 37#define TEGRA124_CLK_PWM 17 38#define TEGRA124_CLK_I2S2 18 39/* 20 (register bit affects vi and vi_sensor) */ 40/* 21 */ 41#define TEGRA124_CLK_USBD 22 42#define TEGRA124_CLK_ISP 23 43/* 26 */ 44/* 25 */ 45#define TEGRA124_CLK_DISP2 26 46#define TEGRA124_CLK_DISP1 27 47#define TEGRA124_CLK_HOST1X 28 48#define TEGRA124_CLK_VCP 29 49#define TEGRA124_CLK_I2S0 30 50/* 31 */ 51 52#define TEGRA124_CLK_MC 32 53/* 33 */ 54#define TEGRA124_CLK_APBDMA 34 55/* 35 */ 56#define TEGRA124_CLK_KBC 36 57/* 37 */ 58/* 38 */ 59/* 39 (register bit affects fuse and fuse_burn) */ 60#define TEGRA124_CLK_KFUSE 40 61#define TEGRA124_CLK_SBC1 41 62#define TEGRA124_CLK_NOR 42 63/* 43 */ 64#define TEGRA124_CLK_SBC2 44 65/* 45 */ 66#define TEGRA124_CLK_SBC3 46 67#define TEGRA124_CLK_I2C5 47 68#define TEGRA124_CLK_DSIA 48 69/* 49 */ 70#define TEGRA124_CLK_MIPI 50 71#define TEGRA124_CLK_HDMI 51 72#define TEGRA124_CLK_CSI 52 73/* 53 */ 74#define TEGRA124_CLK_I2C2 54 75#define TEGRA124_CLK_UARTC 55 76#define TEGRA124_CLK_MIPI_CAL 56 77#define TEGRA124_CLK_EMC 57 78#define TEGRA124_CLK_USB2 58 79#define TEGRA124_CLK_USB3 59 80/* 60 */ 81#define TEGRA124_CLK_VDE 61 82#define TEGRA124_CLK_BSEA 62 83#define TEGRA124_CLK_BSEV 63 84 85/* 64 */ 86#define TEGRA124_CLK_UARTD 65 87/* 66 */ 88#define TEGRA124_CLK_I2C3 67 89#define TEGRA124_CLK_SBC4 68 90#define TEGRA124_CLK_SDMMC3 69 91#define TEGRA124_CLK_PCIE 70 92#define TEGRA124_CLK_OWR 71 93#define TEGRA124_CLK_AFI 72 94#define TEGRA124_CLK_CSITE 73 95/* 74 */ 96/* 75 */ 97#define TEGRA124_CLK_LA 76 98#define TEGRA124_CLK_TRACE 77 99#define TEGRA124_CLK_SOC_THERM 78 100#define TEGRA124_CLK_DTV 79 101/* 80 */ 102#define TEGRA124_CLK_I2CSLOW 81 103#define TEGRA124_CLK_DSIB 82 104#define TEGRA124_CLK_TSEC 83 105/* 84 */ 106/* 85 */ 107/* 86 */ 108/* 87 */ 109/* 88 */ 110#define TEGRA124_CLK_XUSB_HOST 89 111/* 90 */ 112#define TEGRA124_CLK_MSENC 91 113#define TEGRA124_CLK_CSUS 92 114/* 93 */ 115/* 94 */ 116/* 95 (bit affects xusb_dev and xusb_dev_src) */ 117 118/* 96 */ 119/* 97 */ 120/* 98 */ 121#define TEGRA124_CLK_MSELECT 99 122#define TEGRA124_CLK_TSENSOR 100 123#define TEGRA124_CLK_I2S3 101 124#define TEGRA124_CLK_I2S4 102 125#define TEGRA124_CLK_I2C4 103 126#define TEGRA124_CLK_SBC5 104 127#define TEGRA124_CLK_SBC6 105 128#define TEGRA124_CLK_D_AUDIO 106 129#define TEGRA124_CLK_APBIF 107 130#define TEGRA124_CLK_DAM0 108 131#define TEGRA124_CLK_DAM1 109 132#define TEGRA124_CLK_DAM2 110 133#define TEGRA124_CLK_HDA2CODEC_2X 111 134/* 112 */ 135#define TEGRA124_CLK_AUDIO0_2X 113 136#define TEGRA124_CLK_AUDIO1_2X 114 137#define TEGRA124_CLK_AUDIO2_2X 115 138#define TEGRA124_CLK_AUDIO3_2X 116 139#define TEGRA124_CLK_AUDIO4_2X 117 140#define TEGRA124_CLK_SPDIF_2X 118 141#define TEGRA124_CLK_ACTMON 119 142#define TEGRA124_CLK_EXTERN1 120 143#define TEGRA124_CLK_EXTERN2 121 144#define TEGRA124_CLK_EXTERN3 122 145#define TEGRA124_CLK_SATA_OOB 123 146#define TEGRA124_CLK_SATA 124 147#define TEGRA124_CLK_HDA 125 148/* 126 */ 149#define TEGRA124_CLK_SE 127 150 151#define TEGRA124_CLK_HDA2HDMI 128 152#define TEGRA124_CLK_SATA_COLD 129 153/* 130 */ 154/* 131 */ 155/* 132 */ 156/* 133 */ 157/* 134 */ 158/* 135 */ 159/* 136 */ 160/* 137 */ 161/* 138 */ 162/* 139 */ 163/* 140 */ 164/* 141 */ 165/* 142 */ 166/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */ 167/* xusb_host_src and xusb_ss_src) */ 168#define TEGRA124_CLK_CILAB 144 169#define TEGRA124_CLK_CILCD 145 170#define TEGRA124_CLK_CILE 146 171#define TEGRA124_CLK_DSIALP 147 172#define TEGRA124_CLK_DSIBLP 148 173#define TEGRA124_CLK_ENTROPY 149 174#define TEGRA124_CLK_DDS 150 175/* 151 */ 176#define TEGRA124_CLK_DP2 152 177#define TEGRA124_CLK_AMX 153 178#define TEGRA124_CLK_ADX 154 179/* 155 (bit affects dfll_ref and dfll_soc) */ 180#define TEGRA124_CLK_XUSB_SS 156 181/* 157 */ 182/* 158 */ 183/* 159 */ 184 185/* 160 */ 186/* 161 */ 187/* 162 */ 188/* 163 */ 189/* 164 */ 190/* 165 */ 191#define TEGRA124_CLK_I2C6 166 192/* 167 */ 193/* 168 */ 194/* 169 */ 195/* 170 */ 196#define TEGRA124_CLK_VIM2_CLK 171 197/* 172 */ 198/* 173 */ 199/* 174 */ 200/* 175 */ 201#define TEGRA124_CLK_HDMI_AUDIO 176 202#define TEGRA124_CLK_CLK72MHZ 177 203#define TEGRA124_CLK_VIC03 178 204/* 179 */ 205#define TEGRA124_CLK_ADX1 180 206#define TEGRA124_CLK_DPAUX 181 207#define TEGRA124_CLK_SOR0 182 208/* 183 */ 209#define TEGRA124_CLK_GPU 184 210#define TEGRA124_CLK_AMX1 185 211/* 186 */ 212/* 187 */ 213/* 188 */ 214/* 189 */ 215/* 190 */ 216/* 191 */ 217#define TEGRA124_CLK_UARTB 192 218#define TEGRA124_CLK_VFIR 193 219#define TEGRA124_CLK_SPDIF_IN 194 220#define TEGRA124_CLK_SPDIF_OUT 195 221#define TEGRA124_CLK_VI 196 222#define TEGRA124_CLK_VI_SENSOR 197 223#define TEGRA124_CLK_FUSE 198 224#define TEGRA124_CLK_FUSE_BURN 199 225#define TEGRA124_CLK_CLK_32K 200 226#define TEGRA124_CLK_CLK_M 201 227#define TEGRA124_CLK_CLK_M_DIV2 202 228#define TEGRA124_CLK_CLK_M_DIV4 203 229#define TEGRA124_CLK_PLL_REF 204 230#define TEGRA124_CLK_PLL_C 205 231#define TEGRA124_CLK_PLL_C_OUT1 206 232#define TEGRA124_CLK_PLL_C2 207 233#define TEGRA124_CLK_PLL_C3 208 234#define TEGRA124_CLK_PLL_M 209 235#define TEGRA124_CLK_PLL_M_OUT1 210 236#define TEGRA124_CLK_PLL_P 211 237#define TEGRA124_CLK_PLL_P_OUT1 212 238#define TEGRA124_CLK_PLL_P_OUT2 213 239#define TEGRA124_CLK_PLL_P_OUT3 214 240#define TEGRA124_CLK_PLL_P_OUT4 215 241#define TEGRA124_CLK_PLL_A 216 242#define TEGRA124_CLK_PLL_A_OUT0 217 243#define TEGRA124_CLK_PLL_D 218 244#define TEGRA124_CLK_PLL_D_OUT0 219 245#define TEGRA124_CLK_PLL_D2 220 246#define TEGRA124_CLK_PLL_D2_OUT0 221 247#define TEGRA124_CLK_PLL_U 222 248#define TEGRA124_CLK_PLL_U_480M 223 249 250#define TEGRA124_CLK_PLL_U_60M 224 251#define TEGRA124_CLK_PLL_U_48M 225 252#define TEGRA124_CLK_PLL_U_12M 226 253/* 227 */ 254/* 228 */ 255#define TEGRA124_CLK_PLL_RE_VCO 229 256#define TEGRA124_CLK_PLL_RE_OUT 230 257#define TEGRA124_CLK_PLL_E 231 258#define TEGRA124_CLK_SPDIF_IN_SYNC 232 259#define TEGRA124_CLK_I2S0_SYNC 233 260#define TEGRA124_CLK_I2S1_SYNC 234 261#define TEGRA124_CLK_I2S2_SYNC 235 262#define TEGRA124_CLK_I2S3_SYNC 236 263#define TEGRA124_CLK_I2S4_SYNC 237 264#define TEGRA124_CLK_VIMCLK_SYNC 238 265#define TEGRA124_CLK_AUDIO0 239 266#define TEGRA124_CLK_AUDIO1 240 267#define TEGRA124_CLK_AUDIO2 241 268#define TEGRA124_CLK_AUDIO3 242 269#define TEGRA124_CLK_AUDIO4 243 270#define TEGRA124_CLK_SPDIF 244 271#define TEGRA124_CLK_CLK_OUT_1 245 272#define TEGRA124_CLK_CLK_OUT_2 246 273#define TEGRA124_CLK_CLK_OUT_3 247 274#define TEGRA124_CLK_BLINK 248 275/* 249 */ 276/* 250 */ 277/* 251 */ 278#define TEGRA124_CLK_XUSB_HOST_SRC 252 279#define TEGRA124_CLK_XUSB_FALCON_SRC 253 280#define TEGRA124_CLK_XUSB_FS_SRC 254 281#define TEGRA124_CLK_XUSB_SS_SRC 255 282 283#define TEGRA124_CLK_XUSB_DEV_SRC 256 284#define TEGRA124_CLK_XUSB_DEV 257 285#define TEGRA124_CLK_XUSB_HS_SRC 258 286#define TEGRA124_CLK_SCLK 259 287#define TEGRA124_CLK_HCLK 260 288#define TEGRA124_CLK_PCLK 261 289/* 262 */ 290/* 263 */ 291#define TEGRA124_CLK_DFLL_REF 264 292#define TEGRA124_CLK_DFLL_SOC 265 293#define TEGRA124_CLK_VI_SENSOR2 266 294#define TEGRA124_CLK_PLL_P_OUT5 267 295#define TEGRA124_CLK_CML0 268 296#define TEGRA124_CLK_CML1 269 297#define TEGRA124_CLK_PLL_C4 270 298#define TEGRA124_CLK_PLL_DP 271 299#define TEGRA124_CLK_PLL_E_MUX 272 300#define TEGRA124_CLK_PLL_D_DSI_OUT 273 301/* 274 */ 302/* 275 */ 303/* 276 */ 304/* 277 */ 305/* 278 */ 306/* 279 */ 307/* 280 */ 308/* 281 */ 309/* 282 */ 310/* 283 */ 311/* 284 */ 312/* 285 */ 313/* 286 */ 314/* 287 */ 315 316/* 288 */ 317/* 289 */ 318/* 290 */ 319/* 291 */ 320/* 292 */ 321/* 293 */ 322/* 294 */ 323/* 295 */ 324/* 296 */ 325/* 297 */ 326/* 298 */ 327/* 299 */ 328#define TEGRA124_CLK_AUDIO0_MUX 300 329#define TEGRA124_CLK_AUDIO1_MUX 301 330#define TEGRA124_CLK_AUDIO2_MUX 302 331#define TEGRA124_CLK_AUDIO3_MUX 303 332#define TEGRA124_CLK_AUDIO4_MUX 304 333#define TEGRA124_CLK_SPDIF_MUX 305 334#define TEGRA124_CLK_CLK_OUT_1_MUX 306 335#define TEGRA124_CLK_CLK_OUT_2_MUX 307 336#define TEGRA124_CLK_CLK_OUT_3_MUX 308 337/* 309 */ 338/* 310 */ 339#define TEGRA124_CLK_SOR0_LVDS 311 340#define TEGRA124_CLK_XUSB_SS_DIV2 312 341 342#define TEGRA124_CLK_PLL_M_UD 313 343#define TEGRA124_CLK_PLL_C_UD 314 344 345#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H */ 346