1/*
2 * HDMI driver definition for TI OMAP4 Processor.
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program.  If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#ifndef _HDMI_H
20#define _HDMI_H
21
22#include <linux/delay.h>
23#include <linux/io.h>
24#include <linux/platform_device.h>
25#include <linux/hdmi.h>
26#include <video/omapdss.h>
27
28#include "dss.h"
29
30/* HDMI Wrapper */
31
32#define HDMI_WP_REVISION			0x0
33#define HDMI_WP_SYSCONFIG			0x10
34#define HDMI_WP_IRQSTATUS_RAW			0x24
35#define HDMI_WP_IRQSTATUS			0x28
36#define HDMI_WP_IRQENABLE_SET			0x2C
37#define HDMI_WP_IRQENABLE_CLR			0x30
38#define HDMI_WP_IRQWAKEEN			0x34
39#define HDMI_WP_PWR_CTRL			0x40
40#define HDMI_WP_DEBOUNCE			0x44
41#define HDMI_WP_VIDEO_CFG			0x50
42#define HDMI_WP_VIDEO_SIZE			0x60
43#define HDMI_WP_VIDEO_TIMING_H			0x68
44#define HDMI_WP_VIDEO_TIMING_V			0x6C
45#define HDMI_WP_CLK				0x70
46#define HDMI_WP_AUDIO_CFG			0x80
47#define HDMI_WP_AUDIO_CFG2			0x84
48#define HDMI_WP_AUDIO_CTRL			0x88
49#define HDMI_WP_AUDIO_DATA			0x8C
50
51/* HDMI WP IRQ flags */
52#define HDMI_IRQ_CORE				(1 << 0)
53#define HDMI_IRQ_OCP_TIMEOUT			(1 << 4)
54#define HDMI_IRQ_AUDIO_FIFO_UNDERFLOW		(1 << 8)
55#define HDMI_IRQ_AUDIO_FIFO_OVERFLOW		(1 << 9)
56#define HDMI_IRQ_AUDIO_FIFO_SAMPLE_REQ		(1 << 10)
57#define HDMI_IRQ_VIDEO_VSYNC			(1 << 16)
58#define HDMI_IRQ_VIDEO_FRAME_DONE		(1 << 17)
59#define HDMI_IRQ_PHY_LINE5V_ASSERT		(1 << 24)
60#define HDMI_IRQ_LINK_CONNECT			(1 << 25)
61#define HDMI_IRQ_LINK_DISCONNECT		(1 << 26)
62#define HDMI_IRQ_PLL_LOCK			(1 << 29)
63#define HDMI_IRQ_PLL_UNLOCK			(1 << 30)
64#define HDMI_IRQ_PLL_RECAL			(1 << 31)
65
66/* HDMI PLL */
67
68#define PLLCTRL_PLL_CONTROL			0x0
69#define PLLCTRL_PLL_STATUS			0x4
70#define PLLCTRL_PLL_GO				0x8
71#define PLLCTRL_CFG1				0xC
72#define PLLCTRL_CFG2				0x10
73#define PLLCTRL_CFG3				0x14
74#define PLLCTRL_SSC_CFG1			0x18
75#define PLLCTRL_SSC_CFG2			0x1C
76#define PLLCTRL_CFG4				0x20
77
78/* HDMI PHY */
79
80#define HDMI_TXPHY_TX_CTRL			0x0
81#define HDMI_TXPHY_DIGITAL_CTRL			0x4
82#define HDMI_TXPHY_POWER_CTRL			0x8
83#define HDMI_TXPHY_PAD_CFG_CTRL			0xC
84#define HDMI_TXPHY_BIST_CONTROL			0x1C
85
86enum hdmi_pll_pwr {
87	HDMI_PLLPWRCMD_ALLOFF = 0,
88	HDMI_PLLPWRCMD_PLLONLY = 1,
89	HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2,
90	HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3
91};
92
93enum hdmi_phy_pwr {
94	HDMI_PHYPWRCMD_OFF = 0,
95	HDMI_PHYPWRCMD_LDOON = 1,
96	HDMI_PHYPWRCMD_TXON = 2
97};
98
99enum hdmi_core_hdmi_dvi {
100	HDMI_DVI = 0,
101	HDMI_HDMI = 1
102};
103
104enum hdmi_packing_mode {
105	HDMI_PACK_10b_RGB_YUV444 = 0,
106	HDMI_PACK_24b_RGB_YUV444_YUV422 = 1,
107	HDMI_PACK_20b_YUV422 = 2,
108	HDMI_PACK_ALREADYPACKED = 7
109};
110
111enum hdmi_stereo_channels {
112	HDMI_AUDIO_STEREO_NOCHANNELS = 0,
113	HDMI_AUDIO_STEREO_ONECHANNEL = 1,
114	HDMI_AUDIO_STEREO_TWOCHANNELS = 2,
115	HDMI_AUDIO_STEREO_THREECHANNELS = 3,
116	HDMI_AUDIO_STEREO_FOURCHANNELS = 4
117};
118
119enum hdmi_audio_type {
120	HDMI_AUDIO_TYPE_LPCM = 0,
121	HDMI_AUDIO_TYPE_IEC = 1
122};
123
124enum hdmi_audio_justify {
125	HDMI_AUDIO_JUSTIFY_LEFT = 0,
126	HDMI_AUDIO_JUSTIFY_RIGHT = 1
127};
128
129enum hdmi_audio_sample_order {
130	HDMI_AUDIO_SAMPLE_RIGHT_FIRST = 0,
131	HDMI_AUDIO_SAMPLE_LEFT_FIRST = 1
132};
133
134enum hdmi_audio_samples_perword {
135	HDMI_AUDIO_ONEWORD_ONESAMPLE = 0,
136	HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1
137};
138
139enum hdmi_audio_sample_size_omap {
140	HDMI_AUDIO_SAMPLE_16BITS = 0,
141	HDMI_AUDIO_SAMPLE_24BITS = 1
142};
143
144enum hdmi_audio_transf_mode {
145	HDMI_AUDIO_TRANSF_DMA = 0,
146	HDMI_AUDIO_TRANSF_IRQ = 1
147};
148
149enum hdmi_audio_blk_strt_end_sig {
150	HDMI_AUDIO_BLOCK_SIG_STARTEND_ON = 0,
151	HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1
152};
153
154enum hdmi_core_audio_layout {
155	HDMI_AUDIO_LAYOUT_2CH = 0,
156	HDMI_AUDIO_LAYOUT_8CH = 1,
157	HDMI_AUDIO_LAYOUT_6CH = 2
158};
159
160enum hdmi_core_cts_mode {
161	HDMI_AUDIO_CTS_MODE_HW = 0,
162	HDMI_AUDIO_CTS_MODE_SW = 1
163};
164
165enum hdmi_audio_mclk_mode {
166	HDMI_AUDIO_MCLK_128FS = 0,
167	HDMI_AUDIO_MCLK_256FS = 1,
168	HDMI_AUDIO_MCLK_384FS = 2,
169	HDMI_AUDIO_MCLK_512FS = 3,
170	HDMI_AUDIO_MCLK_768FS = 4,
171	HDMI_AUDIO_MCLK_1024FS = 5,
172	HDMI_AUDIO_MCLK_1152FS = 6,
173	HDMI_AUDIO_MCLK_192FS = 7
174};
175
176struct hdmi_video_format {
177	enum hdmi_packing_mode	packing_mode;
178	u32			y_res;	/* Line per panel */
179	u32			x_res;	/* pixel per line */
180};
181
182struct hdmi_config {
183	struct omap_video_timings timings;
184	struct hdmi_avi_infoframe infoframe;
185	enum hdmi_core_hdmi_dvi hdmi_dvi_mode;
186};
187
188struct hdmi_audio_format {
189	enum hdmi_stereo_channels		stereo_channels;
190	u8					active_chnnls_msk;
191	enum hdmi_audio_type			type;
192	enum hdmi_audio_justify			justification;
193	enum hdmi_audio_sample_order		sample_order;
194	enum hdmi_audio_samples_perword		samples_per_word;
195	enum hdmi_audio_sample_size_omap	sample_size;
196	enum hdmi_audio_blk_strt_end_sig	en_sig_blk_strt_end;
197};
198
199struct hdmi_audio_dma {
200	u8				transfer_size;
201	u8				block_size;
202	enum hdmi_audio_transf_mode	mode;
203	u16				fifo_threshold;
204};
205
206struct hdmi_core_audio_i2s_config {
207	u8 in_length_bits;
208	u8 justification;
209	u8 sck_edge_mode;
210	u8 vbit;
211	u8 direction;
212	u8 shift;
213	u8 active_sds;
214};
215
216struct hdmi_core_audio_config {
217	struct hdmi_core_audio_i2s_config	i2s_cfg;
218	struct snd_aes_iec958			*iec60958_cfg;
219	bool					fs_override;
220	u32					n;
221	u32					cts;
222	u32					aud_par_busclk;
223	enum hdmi_core_audio_layout		layout;
224	enum hdmi_core_cts_mode			cts_mode;
225	bool					use_mclk;
226	enum hdmi_audio_mclk_mode		mclk_mode;
227	bool					en_acr_pkt;
228	bool					en_dsd_audio;
229	bool					en_parallel_aud_input;
230	bool					en_spdif;
231};
232
233struct hdmi_wp_data {
234	void __iomem *base;
235	phys_addr_t phys_base;
236};
237
238struct hdmi_pll_data {
239	struct dss_pll pll;
240
241	void __iomem *base;
242
243	struct hdmi_wp_data *wp;
244};
245
246struct hdmi_phy_data {
247	void __iomem *base;
248
249	u8 lane_function[4];
250	u8 lane_polarity[4];
251};
252
253struct hdmi_core_data {
254	void __iomem *base;
255};
256
257static inline void hdmi_write_reg(void __iomem *base_addr, const u32 idx,
258		u32 val)
259{
260	__raw_writel(val, base_addr + idx);
261}
262
263static inline u32 hdmi_read_reg(void __iomem *base_addr, const u32 idx)
264{
265	return __raw_readl(base_addr + idx);
266}
267
268#define REG_FLD_MOD(base, idx, val, start, end) \
269	hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
270							val, start, end))
271#define REG_GET(base, idx, start, end) \
272	FLD_GET(hdmi_read_reg(base, idx), start, end)
273
274static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
275		const u32 idx, int b2, int b1, u32 val)
276{
277	u32 t = 0, v;
278	while (val != (v = REG_GET(base_addr, idx, b2, b1))) {
279		if (t++ > 10000)
280			return v;
281		udelay(1);
282	}
283	return v;
284}
285
286/* HDMI wrapper funcs */
287int hdmi_wp_video_start(struct hdmi_wp_data *wp);
288void hdmi_wp_video_stop(struct hdmi_wp_data *wp);
289void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s);
290u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp);
291void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus);
292void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask);
293void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask);
294int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val);
295int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val);
296void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,
297		struct hdmi_video_format *video_fmt);
298void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
299		struct omap_video_timings *timings);
300void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
301		struct omap_video_timings *timings);
302void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
303		struct omap_video_timings *timings, struct hdmi_config *param);
304int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp);
305phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp);
306
307/* HDMI PLL funcs */
308void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s);
309void hdmi_pll_compute(struct hdmi_pll_data *pll,
310	unsigned long target_tmds, struct dss_pll_clock_info *pi);
311int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll,
312	struct hdmi_wp_data *wp);
313void hdmi_pll_uninit(struct hdmi_pll_data *hpll);
314
315/* HDMI PHY funcs */
316int hdmi_phy_configure(struct hdmi_phy_data *phy, unsigned long hfbitclk,
317	unsigned long lfbitclk);
318void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s);
319int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy);
320int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes);
321
322/* HDMI common funcs */
323int hdmi_parse_lanes_of(struct platform_device *pdev, struct device_node *ep,
324	struct hdmi_phy_data *phy);
325
326/* Audio funcs */
327int hdmi_compute_acr(u32 pclk, u32 sample_freq, u32 *n, u32 *cts);
328int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable);
329int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable);
330void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,
331		struct hdmi_audio_format *aud_fmt);
332void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,
333		struct hdmi_audio_dma *aud_dma);
334static inline bool hdmi_mode_has_audio(struct hdmi_config *cfg)
335{
336	return cfg->hdmi_dvi_mode == HDMI_HDMI ? true : false;
337}
338
339/* HDMI DRV data */
340struct omap_hdmi {
341	struct mutex lock;
342	struct platform_device *pdev;
343
344	struct hdmi_wp_data	wp;
345	struct hdmi_pll_data	pll;
346	struct hdmi_phy_data	phy;
347	struct hdmi_core_data	core;
348
349	struct hdmi_config cfg;
350
351	struct regulator *vdda_reg;
352
353	bool core_enabled;
354	bool display_enabled;
355
356	struct omap_dss_device output;
357
358	struct platform_device *audio_pdev;
359	void (*audio_abort_cb)(struct device *dev);
360	int wp_idlemode;
361};
362
363#endif
364