1/* 2 * Renesas USB driver 3 * 4 * Copyright (C) 2011 Renesas Solutions Corp. 5 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 * 12 * You should have received a copy of the GNU General Public License 13 * along with this program; if not, write to the Free Software 14 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 15 * 16 */ 17#ifndef RENESAS_USB_DRIVER_H 18#define RENESAS_USB_DRIVER_H 19 20#include <linux/extcon.h> 21#include <linux/platform_device.h> 22#include <linux/usb/renesas_usbhs.h> 23 24struct usbhs_priv; 25 26#include "mod.h" 27#include "pipe.h" 28 29/* 30 * 31 * register define 32 * 33 */ 34#define SYSCFG 0x0000 35#define BUSWAIT 0x0002 36#define DVSTCTR 0x0008 37#define TESTMODE 0x000C 38#define CFIFO 0x0014 39#define CFIFOSEL 0x0020 40#define CFIFOCTR 0x0022 41#define D0FIFO 0x0100 42#define D0FIFOSEL 0x0028 43#define D0FIFOCTR 0x002A 44#define D1FIFO 0x0120 45#define D1FIFOSEL 0x002C 46#define D1FIFOCTR 0x002E 47#define INTENB0 0x0030 48#define INTENB1 0x0032 49#define BRDYENB 0x0036 50#define NRDYENB 0x0038 51#define BEMPENB 0x003A 52#define INTSTS0 0x0040 53#define INTSTS1 0x0042 54#define BRDYSTS 0x0046 55#define NRDYSTS 0x0048 56#define BEMPSTS 0x004A 57#define FRMNUM 0x004C 58#define USBREQ 0x0054 /* USB request type register */ 59#define USBVAL 0x0056 /* USB request value register */ 60#define USBINDX 0x0058 /* USB request index register */ 61#define USBLENG 0x005A /* USB request length register */ 62#define DCPCFG 0x005C 63#define DCPMAXP 0x005E 64#define DCPCTR 0x0060 65#define PIPESEL 0x0064 66#define PIPECFG 0x0068 67#define PIPEBUF 0x006A 68#define PIPEMAXP 0x006C 69#define PIPEPERI 0x006E 70#define PIPEnCTR 0x0070 71#define PIPE1TRE 0x0090 72#define PIPE1TRN 0x0092 73#define PIPE2TRE 0x0094 74#define PIPE2TRN 0x0096 75#define PIPE3TRE 0x0098 76#define PIPE3TRN 0x009A 77#define PIPE4TRE 0x009C 78#define PIPE4TRN 0x009E 79#define PIPE5TRE 0x00A0 80#define PIPE5TRN 0x00A2 81#define PIPEBTRE 0x00A4 82#define PIPEBTRN 0x00A6 83#define PIPECTRE 0x00A8 84#define PIPECTRN 0x00AA 85#define PIPEDTRE 0x00AC 86#define PIPEDTRN 0x00AE 87#define PIPEETRE 0x00B0 88#define PIPEETRN 0x00B2 89#define PIPEFTRE 0x00B4 90#define PIPEFTRN 0x00B6 91#define PIPE9TRE 0x00B8 92#define PIPE9TRN 0x00BA 93#define PIPEATRE 0x00BC 94#define PIPEATRN 0x00BE 95#define DEVADD0 0x00D0 /* Device address n configuration */ 96#define DEVADD1 0x00D2 97#define DEVADD2 0x00D4 98#define DEVADD3 0x00D6 99#define DEVADD4 0x00D8 100#define DEVADD5 0x00DA 101#define DEVADD6 0x00DC 102#define DEVADD7 0x00DE 103#define DEVADD8 0x00E0 104#define DEVADD9 0x00E2 105#define DEVADDA 0x00E4 106#define D2FIFOSEL 0x00F0 /* for R-Car Gen2 */ 107#define D2FIFOCTR 0x00F2 /* for R-Car Gen2 */ 108#define D3FIFOSEL 0x00F4 /* for R-Car Gen2 */ 109#define D3FIFOCTR 0x00F6 /* for R-Car Gen2 */ 110 111/* SYSCFG */ 112#define SCKE (1 << 10) /* USB Module Clock Enable */ 113#define HSE (1 << 7) /* High-Speed Operation Enable */ 114#define DCFM (1 << 6) /* Controller Function Select */ 115#define DRPD (1 << 5) /* D+ Line/D- Line Resistance Control */ 116#define DPRPU (1 << 4) /* D+ Line Resistance Control */ 117#define USBE (1 << 0) /* USB Module Operation Enable */ 118 119/* DVSTCTR */ 120#define EXTLP (1 << 10) /* Controls the EXTLP pin output state */ 121#define PWEN (1 << 9) /* Controls the PWEN pin output state */ 122#define USBRST (1 << 6) /* Bus Reset Output */ 123#define UACT (1 << 4) /* USB Bus Enable */ 124#define RHST (0x7) /* Reset Handshake */ 125#define RHST_LOW_SPEED 1 /* Low-speed connection */ 126#define RHST_FULL_SPEED 2 /* Full-speed connection */ 127#define RHST_HIGH_SPEED 3 /* High-speed connection */ 128 129/* CFIFOSEL */ 130#define DREQE (1 << 12) /* DMA Transfer Request Enable */ 131#define MBW_32 (0x2 << 10) /* CFIFO Port Access Bit Width */ 132 133/* CFIFOCTR */ 134#define BVAL (1 << 15) /* Buffer Memory Enable Flag */ 135#define BCLR (1 << 14) /* CPU buffer clear */ 136#define FRDY (1 << 13) /* FIFO Port Ready */ 137#define DTLN_MASK (0x0FFF) /* Receive Data Length */ 138 139/* INTENB0 */ 140#define VBSE (1 << 15) /* Enable IRQ VBUS_0 and VBUSIN_0 */ 141#define RSME (1 << 14) /* Enable IRQ Resume */ 142#define SOFE (1 << 13) /* Enable IRQ Frame Number Update */ 143#define DVSE (1 << 12) /* Enable IRQ Device State Transition */ 144#define CTRE (1 << 11) /* Enable IRQ Control Stage Transition */ 145#define BEMPE (1 << 10) /* Enable IRQ Buffer Empty */ 146#define NRDYE (1 << 9) /* Enable IRQ Buffer Not Ready Response */ 147#define BRDYE (1 << 8) /* Enable IRQ Buffer Ready */ 148 149/* INTENB1 */ 150#define BCHGE (1 << 14) /* USB Bus Change Interrupt Enable */ 151#define DTCHE (1 << 12) /* Disconnection Detect Interrupt Enable */ 152#define ATTCHE (1 << 11) /* Connection Detect Interrupt Enable */ 153#define EOFERRE (1 << 6) /* EOF Error Detect Interrupt Enable */ 154#define SIGNE (1 << 5) /* Setup Transaction Error Interrupt Enable */ 155#define SACKE (1 << 4) /* Setup Transaction ACK Interrupt Enable */ 156 157/* INTSTS0 */ 158#define VBINT (1 << 15) /* VBUS0_0 and VBUS1_0 Interrupt Status */ 159#define DVST (1 << 12) /* Device State Transition Interrupt Status */ 160#define CTRT (1 << 11) /* Control Stage Interrupt Status */ 161#define BEMP (1 << 10) /* Buffer Empty Interrupt Status */ 162#define BRDY (1 << 8) /* Buffer Ready Interrupt Status */ 163#define VBSTS (1 << 7) /* VBUS_0 and VBUSIN_0 Input Status */ 164#define VALID (1 << 3) /* USB Request Receive */ 165 166#define DVSQ_MASK (0x3 << 4) /* Device State */ 167#define POWER_STATE (0 << 4) 168#define DEFAULT_STATE (1 << 4) 169#define ADDRESS_STATE (2 << 4) 170#define CONFIGURATION_STATE (3 << 4) 171 172#define CTSQ_MASK (0x7) /* Control Transfer Stage */ 173#define IDLE_SETUP_STAGE 0 /* Idle stage or setup stage */ 174#define READ_DATA_STAGE 1 /* Control read data stage */ 175#define READ_STATUS_STAGE 2 /* Control read status stage */ 176#define WRITE_DATA_STAGE 3 /* Control write data stage */ 177#define WRITE_STATUS_STAGE 4 /* Control write status stage */ 178#define NODATA_STATUS_STAGE 5 /* Control write NoData status stage */ 179#define SEQUENCE_ERROR 6 /* Control transfer sequence error */ 180 181/* INTSTS1 */ 182#define OVRCR (1 << 15) /* OVRCR Interrupt Status */ 183#define BCHG (1 << 14) /* USB Bus Change Interrupt Status */ 184#define DTCH (1 << 12) /* USB Disconnection Detect Interrupt Status */ 185#define ATTCH (1 << 11) /* ATTCH Interrupt Status */ 186#define EOFERR (1 << 6) /* EOF Error Detect Interrupt Status */ 187#define SIGN (1 << 5) /* Setup Transaction Error Interrupt Status */ 188#define SACK (1 << 4) /* Setup Transaction ACK Response Interrupt Status */ 189 190/* PIPECFG */ 191/* DCPCFG */ 192#define TYPE_NONE (0 << 14) /* Transfer Type */ 193#define TYPE_BULK (1 << 14) 194#define TYPE_INT (2 << 14) 195#define TYPE_ISO (3 << 14) 196#define BFRE (1 << 10) /* BRDY Interrupt Operation Spec. */ 197#define DBLB (1 << 9) /* Double Buffer Mode */ 198#define SHTNAK (1 << 7) /* Pipe Disable in Transfer End */ 199#define DIR_OUT (1 << 4) /* Transfer Direction */ 200 201/* PIPEMAXP */ 202/* DCPMAXP */ 203#define DEVSEL_MASK (0xF << 12) /* Device Select */ 204#define DCP_MAXP_MASK (0x7F) 205#define PIPE_MAXP_MASK (0x7FF) 206 207/* PIPEBUF */ 208#define BUFSIZE_SHIFT 10 209#define BUFSIZE_MASK (0x1F << BUFSIZE_SHIFT) 210#define BUFNMB_MASK (0xFF) 211 212/* PIPEnCTR */ 213/* DCPCTR */ 214#define BSTS (1 << 15) /* Buffer Status */ 215#define SUREQ (1 << 14) /* Sending SETUP Token */ 216#define CSSTS (1 << 12) /* CSSTS Status */ 217#define ACLRM (1 << 9) /* Buffer Auto-Clear Mode */ 218#define SQCLR (1 << 8) /* Toggle Bit Clear */ 219#define SQSET (1 << 7) /* Toggle Bit Set */ 220#define SQMON (1 << 6) /* Toggle Bit Check */ 221#define PBUSY (1 << 5) /* Pipe Busy */ 222#define PID_MASK (0x3) /* Response PID */ 223#define PID_NAK 0 224#define PID_BUF 1 225#define PID_STALL10 2 226#define PID_STALL11 3 227 228#define CCPL (1 << 2) /* Control Transfer End Enable */ 229 230/* PIPEnTRE */ 231#define TRENB (1 << 9) /* Transaction Counter Enable */ 232#define TRCLR (1 << 8) /* Transaction Counter Clear */ 233 234/* FRMNUM */ 235#define FRNM_MASK (0x7FF) 236 237/* DEVADDn */ 238#define UPPHUB(x) (((x) & 0xF) << 11) /* HUB Register */ 239#define HUBPORT(x) (((x) & 0x7) << 8) /* HUB Port for Target Device */ 240#define USBSPD(x) (((x) & 0x3) << 6) /* Device Transfer Rate */ 241#define USBSPD_SPEED_LOW 0x1 242#define USBSPD_SPEED_FULL 0x2 243#define USBSPD_SPEED_HIGH 0x3 244 245/* 246 * struct 247 */ 248struct usbhs_priv { 249 250 void __iomem *base; 251 unsigned int irq; 252 unsigned long irqflags; 253 254 struct renesas_usbhs_platform_callback pfunc; 255 struct renesas_usbhs_driver_param dparam; 256 257 struct delayed_work notify_hotplug_work; 258 struct platform_device *pdev; 259 260 struct extcon_dev *edev; 261 262 spinlock_t lock; 263 264 u32 flags; 265 266 /* 267 * module control 268 */ 269 struct usbhs_mod_info mod_info; 270 271 /* 272 * pipe control 273 */ 274 struct usbhs_pipe_info pipe_info; 275 276 /* 277 * fifo control 278 */ 279 struct usbhs_fifo_info fifo_info; 280 281 struct usb_phy *usb_phy; 282 struct phy *phy; 283}; 284 285/* 286 * common 287 */ 288u16 usbhs_read(struct usbhs_priv *priv, u32 reg); 289void usbhs_write(struct usbhs_priv *priv, u32 reg, u16 data); 290void usbhs_bset(struct usbhs_priv *priv, u32 reg, u16 mask, u16 data); 291 292#define usbhs_lock(p, f) spin_lock_irqsave(usbhs_priv_to_lock(p), f) 293#define usbhs_unlock(p, f) spin_unlock_irqrestore(usbhs_priv_to_lock(p), f) 294 295/* 296 * sysconfig 297 */ 298void usbhs_sys_host_ctrl(struct usbhs_priv *priv, int enable); 299void usbhs_sys_function_ctrl(struct usbhs_priv *priv, int enable); 300void usbhs_sys_function_pullup(struct usbhs_priv *priv, int enable); 301void usbhs_sys_set_test_mode(struct usbhs_priv *priv, u16 mode); 302 303/* 304 * usb request 305 */ 306void usbhs_usbreq_get_val(struct usbhs_priv *priv, struct usb_ctrlrequest *req); 307void usbhs_usbreq_set_val(struct usbhs_priv *priv, struct usb_ctrlrequest *req); 308 309/* 310 * bus 311 */ 312void usbhs_bus_send_sof_enable(struct usbhs_priv *priv); 313void usbhs_bus_send_reset(struct usbhs_priv *priv); 314int usbhs_bus_get_speed(struct usbhs_priv *priv); 315int usbhs_vbus_ctrl(struct usbhs_priv *priv, int enable); 316 317/* 318 * frame 319 */ 320int usbhs_frame_get_num(struct usbhs_priv *priv); 321 322/* 323 * device config 324 */ 325int usbhs_set_device_config(struct usbhs_priv *priv, int devnum, u16 upphub, 326 u16 hubport, u16 speed); 327 328/* 329 * interrupt functions 330 */ 331void usbhs_xxxsts_clear(struct usbhs_priv *priv, u16 sts_reg, u16 bit); 332 333/* 334 * data 335 */ 336struct usbhs_priv *usbhs_pdev_to_priv(struct platform_device *pdev); 337#define usbhs_get_dparam(priv, param) (priv->dparam.param) 338#define usbhs_priv_to_pdev(priv) (priv->pdev) 339#define usbhs_priv_to_dev(priv) (&priv->pdev->dev) 340#define usbhs_priv_to_lock(priv) (&priv->lock) 341 342#endif /* RENESAS_USB_DRIVER_H */ 343