1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Author: Robert Love <rlove@google.com>
4 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef __DRIVERS_SERIAL_MSM_SERIAL_H
17#define __DRIVERS_SERIAL_MSM_SERIAL_H
18
19#define UART_MR1			0x0000
20
21#define UART_MR1_AUTO_RFR_LEVEL0	0x3F
22#define UART_MR1_AUTO_RFR_LEVEL1	0x3FF00
23#define UART_MR1_RX_RDY_CTL    		(1 << 7)
24#define UART_MR1_CTS_CTL       		(1 << 6)
25
26#define UART_MR2			0x0004
27#define UART_MR2_ERROR_MODE		(1 << 6)
28#define UART_MR2_BITS_PER_CHAR		0x30
29#define UART_MR2_BITS_PER_CHAR_5	(0x0 << 4)
30#define UART_MR2_BITS_PER_CHAR_6	(0x1 << 4)
31#define UART_MR2_BITS_PER_CHAR_7	(0x2 << 4)
32#define UART_MR2_BITS_PER_CHAR_8	(0x3 << 4)
33#define UART_MR2_STOP_BIT_LEN_ONE	(0x1 << 2)
34#define UART_MR2_STOP_BIT_LEN_TWO	(0x3 << 2)
35#define UART_MR2_PARITY_MODE_NONE	0x0
36#define UART_MR2_PARITY_MODE_ODD	0x1
37#define UART_MR2_PARITY_MODE_EVEN	0x2
38#define UART_MR2_PARITY_MODE_SPACE	0x3
39#define UART_MR2_PARITY_MODE		0x3
40
41#define UART_CSR			0x0008
42
43#define UART_TF		0x000C
44#define UARTDM_TF	0x0070
45
46#define UART_CR				0x0010
47#define UART_CR_CMD_NULL		(0 << 4)
48#define UART_CR_CMD_RESET_RX		(1 << 4)
49#define UART_CR_CMD_RESET_TX		(2 << 4)
50#define UART_CR_CMD_RESET_ERR		(3 << 4)
51#define UART_CR_CMD_RESET_BREAK_INT	(4 << 4)
52#define UART_CR_CMD_START_BREAK		(5 << 4)
53#define UART_CR_CMD_STOP_BREAK		(6 << 4)
54#define UART_CR_CMD_RESET_CTS		(7 << 4)
55#define UART_CR_CMD_RESET_STALE_INT	(8 << 4)
56#define UART_CR_CMD_PACKET_MODE		(9 << 4)
57#define UART_CR_CMD_MODE_RESET		(12 << 4)
58#define UART_CR_CMD_SET_RFR		(13 << 4)
59#define UART_CR_CMD_RESET_RFR		(14 << 4)
60#define UART_CR_CMD_PROTECTION_EN	(16 << 4)
61#define UART_CR_CMD_STALE_EVENT_ENABLE	(80 << 4)
62#define UART_CR_CMD_FORCE_STALE		(4 << 8)
63#define UART_CR_CMD_RESET_TX_READY	(3 << 8)
64#define UART_CR_TX_DISABLE		(1 << 3)
65#define UART_CR_TX_ENABLE		(1 << 2)
66#define UART_CR_RX_DISABLE		(1 << 1)
67#define UART_CR_RX_ENABLE		(1 << 0)
68#define UART_CR_CMD_RESET_RXBREAK_START	((1 << 11) | (2 << 4))
69
70#define UART_IMR		0x0014
71#define UART_IMR_TXLEV		(1 << 0)
72#define UART_IMR_RXSTALE	(1 << 3)
73#define UART_IMR_RXLEV		(1 << 4)
74#define UART_IMR_DELTA_CTS	(1 << 5)
75#define UART_IMR_CURRENT_CTS	(1 << 6)
76#define UART_IMR_RXBREAK_START	(1 << 10)
77
78#define UART_IPR_RXSTALE_LAST		0x20
79#define UART_IPR_STALE_LSB		0x1F
80#define UART_IPR_STALE_TIMEOUT_MSB	0x3FF80
81
82#define UART_IPR	0x0018
83#define UART_TFWR	0x001C
84#define UART_RFWR	0x0020
85#define UART_HCR	0x0024
86
87#define UART_MREG		0x0028
88#define UART_NREG		0x002C
89#define UART_DREG		0x0030
90#define UART_MNDREG		0x0034
91#define UART_IRDA		0x0038
92#define UART_MISR_MODE		0x0040
93#define UART_MISR_RESET		0x0044
94#define UART_MISR_EXPORT	0x0048
95#define UART_MISR_VAL		0x004C
96#define UART_TEST_CTRL		0x0050
97
98#define UART_SR			0x0008
99#define UART_SR_HUNT_CHAR	(1 << 7)
100#define UART_SR_RX_BREAK	(1 << 6)
101#define UART_SR_PAR_FRAME_ERR	(1 << 5)
102#define UART_SR_OVERRUN		(1 << 4)
103#define UART_SR_TX_EMPTY	(1 << 3)
104#define UART_SR_TX_READY	(1 << 2)
105#define UART_SR_RX_FULL		(1 << 1)
106#define UART_SR_RX_READY	(1 << 0)
107
108#define UART_RF			0x000C
109#define UARTDM_RF		0x0070
110#define UART_MISR		0x0010
111#define UART_ISR		0x0014
112#define UART_ISR_TX_READY	(1 << 7)
113
114#define UARTDM_RXFS		0x50
115#define UARTDM_RXFS_BUF_SHIFT	0x7
116#define UARTDM_RXFS_BUF_MASK	0x7
117
118#define UARTDM_DMEN		0x3C
119#define UARTDM_DMEN_RX_SC_ENABLE BIT(5)
120#define UARTDM_DMEN_TX_SC_ENABLE BIT(4)
121
122#define UARTDM_DMRX		0x34
123#define UARTDM_NCF_TX		0x40
124#define UARTDM_RX_TOTAL_SNAP	0x38
125
126#define UART_TO_MSM(uart_port)	((struct msm_port *) uart_port)
127
128static inline
129void msm_write(struct uart_port *port, unsigned int val, unsigned int off)
130{
131	writel_relaxed(val, port->membase + off);
132}
133
134static inline
135unsigned int msm_read(struct uart_port *port, unsigned int off)
136{
137	return readl_relaxed(port->membase + off);
138}
139
140/*
141 * Setup the MND registers to use the TCXO clock.
142 */
143static inline void msm_serial_set_mnd_regs_tcxo(struct uart_port *port)
144{
145	msm_write(port, 0x06, UART_MREG);
146	msm_write(port, 0xF1, UART_NREG);
147	msm_write(port, 0x0F, UART_DREG);
148	msm_write(port, 0x1A, UART_MNDREG);
149	port->uartclk = 1843200;
150}
151
152/*
153 * Setup the MND registers to use the TCXO clock divided by 4.
154 */
155static inline void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port)
156{
157	msm_write(port, 0x18, UART_MREG);
158	msm_write(port, 0xF6, UART_NREG);
159	msm_write(port, 0x0F, UART_DREG);
160	msm_write(port, 0x0A, UART_MNDREG);
161	port->uartclk = 1843200;
162}
163
164static inline
165void msm_serial_set_mnd_regs_from_uartclk(struct uart_port *port)
166{
167	if (port->uartclk == 19200000)
168		msm_serial_set_mnd_regs_tcxo(port);
169	else if (port->uartclk == 4800000)
170		msm_serial_set_mnd_regs_tcxoby4(port);
171}
172
173#define msm_serial_set_mnd_regs msm_serial_set_mnd_regs_from_uartclk
174
175#endif	/* __DRIVERS_SERIAL_MSM_SERIAL_H */
176