1/* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7#include "qla_def.h" 8 9#include <linux/moduleparam.h> 10#include <linux/vmalloc.h> 11#include <linux/delay.h> 12#include <linux/kthread.h> 13#include <linux/mutex.h> 14#include <linux/kobject.h> 15#include <linux/slab.h> 16#include <scsi/scsi_tcq.h> 17#include <scsi/scsicam.h> 18#include <scsi/scsi_transport.h> 19#include <scsi/scsi_transport_fc.h> 20 21#include "qla_target.h" 22 23/* 24 * Driver version 25 */ 26char qla2x00_version_str[40]; 27 28static int apidev_major; 29 30/* 31 * SRB allocation cache 32 */ 33static struct kmem_cache *srb_cachep; 34 35/* 36 * CT6 CTX allocation cache 37 */ 38static struct kmem_cache *ctx_cachep; 39/* 40 * error level for logging 41 */ 42int ql_errlev = ql_log_all; 43 44static int ql2xenableclass2; 45module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 46MODULE_PARM_DESC(ql2xenableclass2, 47 "Specify if Class 2 operations are supported from the very " 48 "beginning. Default is 0 - class 2 not supported."); 49 50 51int ql2xlogintimeout = 20; 52module_param(ql2xlogintimeout, int, S_IRUGO); 53MODULE_PARM_DESC(ql2xlogintimeout, 54 "Login timeout value in seconds."); 55 56int qlport_down_retry; 57module_param(qlport_down_retry, int, S_IRUGO); 58MODULE_PARM_DESC(qlport_down_retry, 59 "Maximum number of command retries to a port that returns " 60 "a PORT-DOWN status."); 61 62int ql2xplogiabsentdevice; 63module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 64MODULE_PARM_DESC(ql2xplogiabsentdevice, 65 "Option to enable PLOGI to devices that are not present after " 66 "a Fabric scan. This is needed for several broken switches. " 67 "Default is 0 - no PLOGI. 1 - perfom PLOGI."); 68 69int ql2xloginretrycount = 0; 70module_param(ql2xloginretrycount, int, S_IRUGO); 71MODULE_PARM_DESC(ql2xloginretrycount, 72 "Specify an alternate value for the NVRAM login retry count."); 73 74int ql2xallocfwdump = 1; 75module_param(ql2xallocfwdump, int, S_IRUGO); 76MODULE_PARM_DESC(ql2xallocfwdump, 77 "Option to enable allocation of memory for a firmware dump " 78 "during HBA initialization. Memory allocation requirements " 79 "vary by ISP type. Default is 1 - allocate memory."); 80 81int ql2xextended_error_logging; 82module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 83MODULE_PARM_DESC(ql2xextended_error_logging, 84 "Option to enable extended error logging,\n" 85 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 86 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 87 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 88 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 89 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 90 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 91 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 92 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 93 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 94 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 95 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 96 "\t\t0x1e400000 - Preferred value for capturing essential " 97 "debug information (equivalent to old " 98 "ql2xextended_error_logging=1).\n" 99 "\t\tDo LOGICAL OR of the value to enable more than one level"); 100 101int ql2xshiftctondsd = 6; 102module_param(ql2xshiftctondsd, int, S_IRUGO); 103MODULE_PARM_DESC(ql2xshiftctondsd, 104 "Set to control shifting of command type processing " 105 "based on total number of SG elements."); 106 107int ql2xfdmienable=1; 108module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 109MODULE_PARM_DESC(ql2xfdmienable, 110 "Enables FDMI registrations. " 111 "0 - no FDMI. Default is 1 - perform FDMI."); 112 113#define MAX_Q_DEPTH 32 114static int ql2xmaxqdepth = MAX_Q_DEPTH; 115module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 116MODULE_PARM_DESC(ql2xmaxqdepth, 117 "Maximum queue depth to set for each LUN. " 118 "Default is 32."); 119 120int ql2xenabledif = 2; 121module_param(ql2xenabledif, int, S_IRUGO); 122MODULE_PARM_DESC(ql2xenabledif, 123 " Enable T10-CRC-DIF:\n" 124 " Default is 2.\n" 125 " 0 -- No DIF Support\n" 126 " 1 -- Enable DIF for all types\n" 127 " 2 -- Enable DIF for all types, except Type 0.\n"); 128 129int ql2xenablehba_err_chk = 2; 130module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 131MODULE_PARM_DESC(ql2xenablehba_err_chk, 132 " Enable T10-CRC-DIF Error isolation by HBA:\n" 133 " Default is 2.\n" 134 " 0 -- Error isolation disabled\n" 135 " 1 -- Error isolation enabled only for DIX Type 0\n" 136 " 2 -- Error isolation enabled for all Types\n"); 137 138int ql2xiidmaenable=1; 139module_param(ql2xiidmaenable, int, S_IRUGO); 140MODULE_PARM_DESC(ql2xiidmaenable, 141 "Enables iIDMA settings " 142 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 143 144int ql2xmaxqueues = 1; 145module_param(ql2xmaxqueues, int, S_IRUGO); 146MODULE_PARM_DESC(ql2xmaxqueues, 147 "Enables MQ settings " 148 "Default is 1 for single queue. Set it to number " 149 "of queues in MQ mode."); 150 151int ql2xmultique_tag; 152module_param(ql2xmultique_tag, int, S_IRUGO); 153MODULE_PARM_DESC(ql2xmultique_tag, 154 "Enables CPU affinity settings for the driver " 155 "Default is 0 for no affinity of request and response IO. " 156 "Set it to 1 to turn on the cpu affinity."); 157 158int ql2xfwloadbin; 159module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 160MODULE_PARM_DESC(ql2xfwloadbin, 161 "Option to specify location from which to load ISP firmware:.\n" 162 " 2 -- load firmware via the request_firmware() (hotplug).\n" 163 " interface.\n" 164 " 1 -- load firmware from flash.\n" 165 " 0 -- use default semantics.\n"); 166 167int ql2xetsenable; 168module_param(ql2xetsenable, int, S_IRUGO); 169MODULE_PARM_DESC(ql2xetsenable, 170 "Enables firmware ETS burst." 171 "Default is 0 - skip ETS enablement."); 172 173int ql2xdbwr = 1; 174module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 175MODULE_PARM_DESC(ql2xdbwr, 176 "Option to specify scheme for request queue posting.\n" 177 " 0 -- Regular doorbell.\n" 178 " 1 -- CAMRAM doorbell (faster).\n"); 179 180int ql2xtargetreset = 1; 181module_param(ql2xtargetreset, int, S_IRUGO); 182MODULE_PARM_DESC(ql2xtargetreset, 183 "Enable target reset." 184 "Default is 1 - use hw defaults."); 185 186int ql2xgffidenable; 187module_param(ql2xgffidenable, int, S_IRUGO); 188MODULE_PARM_DESC(ql2xgffidenable, 189 "Enables GFF_ID checks of port type. " 190 "Default is 0 - Do not use GFF_ID information."); 191 192int ql2xasynctmfenable; 193module_param(ql2xasynctmfenable, int, S_IRUGO); 194MODULE_PARM_DESC(ql2xasynctmfenable, 195 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 196 "Default is 0 - Issue TM IOCBs via mailbox mechanism."); 197 198int ql2xdontresethba; 199module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 200MODULE_PARM_DESC(ql2xdontresethba, 201 "Option to specify reset behaviour.\n" 202 " 0 (Default) -- Reset on failure.\n" 203 " 1 -- Do not reset on failure.\n"); 204 205uint64_t ql2xmaxlun = MAX_LUNS; 206module_param(ql2xmaxlun, ullong, S_IRUGO); 207MODULE_PARM_DESC(ql2xmaxlun, 208 "Defines the maximum LU number to register with the SCSI " 209 "midlayer. Default is 65535."); 210 211int ql2xmdcapmask = 0x1F; 212module_param(ql2xmdcapmask, int, S_IRUGO); 213MODULE_PARM_DESC(ql2xmdcapmask, 214 "Set the Minidump driver capture mask level. " 215 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 216 217int ql2xmdenable = 1; 218module_param(ql2xmdenable, int, S_IRUGO); 219MODULE_PARM_DESC(ql2xmdenable, 220 "Enable/disable MiniDump. " 221 "0 - MiniDump disabled. " 222 "1 (Default) - MiniDump enabled."); 223 224/* 225 * SCSI host template entry points 226 */ 227static int qla2xxx_slave_configure(struct scsi_device * device); 228static int qla2xxx_slave_alloc(struct scsi_device *); 229static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time); 230static void qla2xxx_scan_start(struct Scsi_Host *); 231static void qla2xxx_slave_destroy(struct scsi_device *); 232static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd); 233static int qla2xxx_eh_abort(struct scsi_cmnd *); 234static int qla2xxx_eh_device_reset(struct scsi_cmnd *); 235static int qla2xxx_eh_target_reset(struct scsi_cmnd *); 236static int qla2xxx_eh_bus_reset(struct scsi_cmnd *); 237static int qla2xxx_eh_host_reset(struct scsi_cmnd *); 238 239static void qla2x00_clear_drv_active(struct qla_hw_data *); 240static void qla2x00_free_device(scsi_qla_host_t *); 241static void qla83xx_disable_laser(scsi_qla_host_t *vha); 242 243struct scsi_host_template qla2xxx_driver_template = { 244 .module = THIS_MODULE, 245 .name = QLA2XXX_DRIVER_NAME, 246 .queuecommand = qla2xxx_queuecommand, 247 248 .eh_abort_handler = qla2xxx_eh_abort, 249 .eh_device_reset_handler = qla2xxx_eh_device_reset, 250 .eh_target_reset_handler = qla2xxx_eh_target_reset, 251 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 252 .eh_host_reset_handler = qla2xxx_eh_host_reset, 253 254 .slave_configure = qla2xxx_slave_configure, 255 256 .slave_alloc = qla2xxx_slave_alloc, 257 .slave_destroy = qla2xxx_slave_destroy, 258 .scan_finished = qla2xxx_scan_finished, 259 .scan_start = qla2xxx_scan_start, 260 .change_queue_depth = scsi_change_queue_depth, 261 .this_id = -1, 262 .cmd_per_lun = 3, 263 .use_clustering = ENABLE_CLUSTERING, 264 .sg_tablesize = SG_ALL, 265 266 .max_sectors = 0xFFFF, 267 .shost_attrs = qla2x00_host_attrs, 268 269 .supported_mode = MODE_INITIATOR, 270 .use_blk_tags = 1, 271 .track_queue_depth = 1, 272}; 273 274static struct scsi_transport_template *qla2xxx_transport_template = NULL; 275struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 276 277/* TODO Convert to inlines 278 * 279 * Timer routines 280 */ 281 282__inline__ void 283qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval) 284{ 285 init_timer(&vha->timer); 286 vha->timer.expires = jiffies + interval * HZ; 287 vha->timer.data = (unsigned long)vha; 288 vha->timer.function = (void (*)(unsigned long))func; 289 add_timer(&vha->timer); 290 vha->timer_active = 1; 291} 292 293static inline void 294qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 295{ 296 /* Currently used for 82XX only. */ 297 if (vha->device_flags & DFLG_DEV_FAILED) { 298 ql_dbg(ql_dbg_timer, vha, 0x600d, 299 "Device in a failed state, returning.\n"); 300 return; 301 } 302 303 mod_timer(&vha->timer, jiffies + interval * HZ); 304} 305 306static __inline__ void 307qla2x00_stop_timer(scsi_qla_host_t *vha) 308{ 309 del_timer_sync(&vha->timer); 310 vha->timer_active = 0; 311} 312 313static int qla2x00_do_dpc(void *data); 314 315static void qla2x00_rst_aen(scsi_qla_host_t *); 316 317static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 318 struct req_que **, struct rsp_que **); 319static void qla2x00_free_fw_dump(struct qla_hw_data *); 320static void qla2x00_mem_free(struct qla_hw_data *); 321 322/* -------------------------------------------------------------------------- */ 323static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 324 struct rsp_que *rsp) 325{ 326 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 327 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues, 328 GFP_KERNEL); 329 if (!ha->req_q_map) { 330 ql_log(ql_log_fatal, vha, 0x003b, 331 "Unable to allocate memory for request queue ptrs.\n"); 332 goto fail_req_map; 333 } 334 335 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues, 336 GFP_KERNEL); 337 if (!ha->rsp_q_map) { 338 ql_log(ql_log_fatal, vha, 0x003c, 339 "Unable to allocate memory for response queue ptrs.\n"); 340 goto fail_rsp_map; 341 } 342 /* 343 * Make sure we record at least the request and response queue zero in 344 * case we need to free them if part of the probe fails. 345 */ 346 ha->rsp_q_map[0] = rsp; 347 ha->req_q_map[0] = req; 348 set_bit(0, ha->rsp_qid_map); 349 set_bit(0, ha->req_qid_map); 350 return 1; 351 352fail_rsp_map: 353 kfree(ha->req_q_map); 354 ha->req_q_map = NULL; 355fail_req_map: 356 return -ENOMEM; 357} 358 359static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 360{ 361 if (IS_QLAFX00(ha)) { 362 if (req && req->ring_fx00) 363 dma_free_coherent(&ha->pdev->dev, 364 (req->length_fx00 + 1) * sizeof(request_t), 365 req->ring_fx00, req->dma_fx00); 366 } else if (req && req->ring) 367 dma_free_coherent(&ha->pdev->dev, 368 (req->length + 1) * sizeof(request_t), 369 req->ring, req->dma); 370 371 if (req) 372 kfree(req->outstanding_cmds); 373 374 kfree(req); 375 req = NULL; 376} 377 378static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 379{ 380 if (IS_QLAFX00(ha)) { 381 if (rsp && rsp->ring) 382 dma_free_coherent(&ha->pdev->dev, 383 (rsp->length_fx00 + 1) * sizeof(request_t), 384 rsp->ring_fx00, rsp->dma_fx00); 385 } else if (rsp && rsp->ring) { 386 dma_free_coherent(&ha->pdev->dev, 387 (rsp->length + 1) * sizeof(response_t), 388 rsp->ring, rsp->dma); 389 } 390 kfree(rsp); 391 rsp = NULL; 392} 393 394static void qla2x00_free_queues(struct qla_hw_data *ha) 395{ 396 struct req_que *req; 397 struct rsp_que *rsp; 398 int cnt; 399 400 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 401 if (!test_bit(cnt, ha->req_qid_map)) 402 continue; 403 404 req = ha->req_q_map[cnt]; 405 qla2x00_free_req_que(ha, req); 406 } 407 kfree(ha->req_q_map); 408 ha->req_q_map = NULL; 409 410 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 411 if (!test_bit(cnt, ha->rsp_qid_map)) 412 continue; 413 414 rsp = ha->rsp_q_map[cnt]; 415 qla2x00_free_rsp_que(ha, rsp); 416 } 417 kfree(ha->rsp_q_map); 418 ha->rsp_q_map = NULL; 419} 420 421static int qla25xx_setup_mode(struct scsi_qla_host *vha) 422{ 423 uint16_t options = 0; 424 int ques, req, ret; 425 struct qla_hw_data *ha = vha->hw; 426 427 if (!(ha->fw_attributes & BIT_6)) { 428 ql_log(ql_log_warn, vha, 0x00d8, 429 "Firmware is not multi-queue capable.\n"); 430 goto fail; 431 } 432 if (ql2xmultique_tag) { 433 /* create a request queue for IO */ 434 options |= BIT_7; 435 req = qla25xx_create_req_que(ha, options, 0, 0, -1, 436 QLA_DEFAULT_QUE_QOS); 437 if (!req) { 438 ql_log(ql_log_warn, vha, 0x00e0, 439 "Failed to create request queue.\n"); 440 goto fail; 441 } 442 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1); 443 vha->req = ha->req_q_map[req]; 444 options |= BIT_1; 445 for (ques = 1; ques < ha->max_rsp_queues; ques++) { 446 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req); 447 if (!ret) { 448 ql_log(ql_log_warn, vha, 0x00e8, 449 "Failed to create response queue.\n"); 450 goto fail2; 451 } 452 } 453 ha->flags.cpu_affinity_enabled = 1; 454 ql_dbg(ql_dbg_multiq, vha, 0xc007, 455 "CPU affinity mode enabled, " 456 "no. of response queues:%d no. of request queues:%d.\n", 457 ha->max_rsp_queues, ha->max_req_queues); 458 ql_dbg(ql_dbg_init, vha, 0x00e9, 459 "CPU affinity mode enabled, " 460 "no. of response queues:%d no. of request queues:%d.\n", 461 ha->max_rsp_queues, ha->max_req_queues); 462 } 463 return 0; 464fail2: 465 qla25xx_delete_queues(vha); 466 destroy_workqueue(ha->wq); 467 ha->wq = NULL; 468 vha->req = ha->req_q_map[0]; 469fail: 470 ha->mqenable = 0; 471 kfree(ha->req_q_map); 472 kfree(ha->rsp_q_map); 473 ha->max_req_queues = ha->max_rsp_queues = 1; 474 return 1; 475} 476 477static char * 478qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str) 479{ 480 struct qla_hw_data *ha = vha->hw; 481 static char *pci_bus_modes[] = { 482 "33", "66", "100", "133", 483 }; 484 uint16_t pci_bus; 485 486 strcpy(str, "PCI"); 487 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 488 if (pci_bus) { 489 strcat(str, "-X ("); 490 strcat(str, pci_bus_modes[pci_bus]); 491 } else { 492 pci_bus = (ha->pci_attr & BIT_8) >> 8; 493 strcat(str, " ("); 494 strcat(str, pci_bus_modes[pci_bus]); 495 } 496 strcat(str, " MHz)"); 497 498 return (str); 499} 500 501static char * 502qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str) 503{ 504 static char *pci_bus_modes[] = { "33", "66", "100", "133", }; 505 struct qla_hw_data *ha = vha->hw; 506 uint32_t pci_bus; 507 508 if (pci_is_pcie(ha->pdev)) { 509 char lwstr[6]; 510 uint32_t lstat, lspeed, lwidth; 511 512 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 513 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 514 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 515 516 strcpy(str, "PCIe ("); 517 switch (lspeed) { 518 case 1: 519 strcat(str, "2.5GT/s "); 520 break; 521 case 2: 522 strcat(str, "5.0GT/s "); 523 break; 524 case 3: 525 strcat(str, "8.0GT/s "); 526 break; 527 default: 528 strcat(str, "<unknown> "); 529 break; 530 } 531 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth); 532 strcat(str, lwstr); 533 534 return str; 535 } 536 537 strcpy(str, "PCI"); 538 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 539 if (pci_bus == 0 || pci_bus == 8) { 540 strcat(str, " ("); 541 strcat(str, pci_bus_modes[pci_bus >> 3]); 542 } else { 543 strcat(str, "-X "); 544 if (pci_bus & BIT_2) 545 strcat(str, "Mode 2"); 546 else 547 strcat(str, "Mode 1"); 548 strcat(str, " ("); 549 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]); 550 } 551 strcat(str, " MHz)"); 552 553 return str; 554} 555 556static char * 557qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 558{ 559 char un_str[10]; 560 struct qla_hw_data *ha = vha->hw; 561 562 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 563 ha->fw_minor_version, ha->fw_subminor_version); 564 565 if (ha->fw_attributes & BIT_9) { 566 strcat(str, "FLX"); 567 return (str); 568 } 569 570 switch (ha->fw_attributes & 0xFF) { 571 case 0x7: 572 strcat(str, "EF"); 573 break; 574 case 0x17: 575 strcat(str, "TP"); 576 break; 577 case 0x37: 578 strcat(str, "IP"); 579 break; 580 case 0x77: 581 strcat(str, "VI"); 582 break; 583 default: 584 sprintf(un_str, "(%x)", ha->fw_attributes); 585 strcat(str, un_str); 586 break; 587 } 588 if (ha->fw_attributes & 0x100) 589 strcat(str, "X"); 590 591 return (str); 592} 593 594static char * 595qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 596{ 597 struct qla_hw_data *ha = vha->hw; 598 599 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 600 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 601 return str; 602} 603 604void 605qla2x00_sp_free_dma(void *vha, void *ptr) 606{ 607 srb_t *sp = (srb_t *)ptr; 608 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 609 struct qla_hw_data *ha = sp->fcport->vha->hw; 610 void *ctx = GET_CMD_CTX_SP(sp); 611 612 if (sp->flags & SRB_DMA_VALID) { 613 scsi_dma_unmap(cmd); 614 sp->flags &= ~SRB_DMA_VALID; 615 } 616 617 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 618 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 619 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 620 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 621 } 622 623 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 624 /* List assured to be having elements */ 625 qla2x00_clean_dsd_pool(ha, sp, NULL); 626 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 627 } 628 629 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 630 dma_pool_free(ha->dl_dma_pool, ctx, 631 ((struct crc_context *)ctx)->crc_ctx_dma); 632 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 633 } 634 635 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 636 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx; 637 638 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 639 ctx1->fcp_cmnd_dma); 640 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 641 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 642 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 643 mempool_free(ctx1, ha->ctx_mempool); 644 ctx1 = NULL; 645 } 646 647 CMD_SP(cmd) = NULL; 648 qla2x00_rel_sp(sp->fcport->vha, sp); 649} 650 651static void 652qla2x00_sp_compl(void *data, void *ptr, int res) 653{ 654 struct qla_hw_data *ha = (struct qla_hw_data *)data; 655 srb_t *sp = (srb_t *)ptr; 656 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 657 658 cmd->result = res; 659 660 if (atomic_read(&sp->ref_count) == 0) { 661 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015, 662 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 663 sp, GET_CMD_SP(sp)); 664 if (ql2xextended_error_logging & ql_dbg_io) 665 BUG(); 666 return; 667 } 668 if (!atomic_dec_and_test(&sp->ref_count)) 669 return; 670 671 qla2x00_sp_free_dma(ha, sp); 672 cmd->scsi_done(cmd); 673} 674 675/* If we are SP1 here, we need to still take and release the host_lock as SP1 676 * does not have the changes necessary to avoid taking host->host_lock. 677 */ 678static int 679qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 680{ 681 scsi_qla_host_t *vha = shost_priv(host); 682 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 683 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 684 struct qla_hw_data *ha = vha->hw; 685 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 686 srb_t *sp; 687 int rval; 688 689 if (ha->flags.eeh_busy) { 690 if (ha->flags.pci_channel_io_perm_failure) { 691 ql_dbg(ql_dbg_aer, vha, 0x9010, 692 "PCI Channel IO permanent failure, exiting " 693 "cmd=%p.\n", cmd); 694 cmd->result = DID_NO_CONNECT << 16; 695 } else { 696 ql_dbg(ql_dbg_aer, vha, 0x9011, 697 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 698 cmd->result = DID_REQUEUE << 16; 699 } 700 goto qc24_fail_command; 701 } 702 703 rval = fc_remote_port_chkready(rport); 704 if (rval) { 705 cmd->result = rval; 706 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 707 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 708 cmd, rval); 709 goto qc24_fail_command; 710 } 711 712 if (!vha->flags.difdix_supported && 713 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 714 ql_dbg(ql_dbg_io, vha, 0x3004, 715 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 716 cmd); 717 cmd->result = DID_NO_CONNECT << 16; 718 goto qc24_fail_command; 719 } 720 721 if (!fcport) { 722 cmd->result = DID_NO_CONNECT << 16; 723 goto qc24_fail_command; 724 } 725 726 if (atomic_read(&fcport->state) != FCS_ONLINE) { 727 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 728 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 729 ql_dbg(ql_dbg_io, vha, 0x3005, 730 "Returning DNC, fcport_state=%d loop_state=%d.\n", 731 atomic_read(&fcport->state), 732 atomic_read(&base_vha->loop_state)); 733 cmd->result = DID_NO_CONNECT << 16; 734 goto qc24_fail_command; 735 } 736 goto qc24_target_busy; 737 } 738 739 /* 740 * Return target busy if we've received a non-zero retry_delay_timer 741 * in a FCP_RSP. 742 */ 743 if (fcport->retry_delay_timestamp == 0) { 744 /* retry delay not set */ 745 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 746 fcport->retry_delay_timestamp = 0; 747 else 748 goto qc24_target_busy; 749 750 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC); 751 if (!sp) 752 goto qc24_host_busy; 753 754 sp->u.scmd.cmd = cmd; 755 sp->type = SRB_SCSI_CMD; 756 atomic_set(&sp->ref_count, 1); 757 CMD_SP(cmd) = (void *)sp; 758 sp->free = qla2x00_sp_free_dma; 759 sp->done = qla2x00_sp_compl; 760 761 rval = ha->isp_ops->start_scsi(sp); 762 if (rval != QLA_SUCCESS) { 763 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 764 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 765 goto qc24_host_busy_free_sp; 766 } 767 768 return 0; 769 770qc24_host_busy_free_sp: 771 qla2x00_sp_free_dma(ha, sp); 772 773qc24_host_busy: 774 return SCSI_MLQUEUE_HOST_BUSY; 775 776qc24_target_busy: 777 return SCSI_MLQUEUE_TARGET_BUSY; 778 779qc24_fail_command: 780 cmd->scsi_done(cmd); 781 782 return 0; 783} 784 785/* 786 * qla2x00_eh_wait_on_command 787 * Waits for the command to be returned by the Firmware for some 788 * max time. 789 * 790 * Input: 791 * cmd = Scsi Command to wait on. 792 * 793 * Return: 794 * Not Found : 0 795 * Found : 1 796 */ 797static int 798qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 799{ 800#define ABORT_POLLING_PERIOD 1000 801#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 802 unsigned long wait_iter = ABORT_WAIT_ITER; 803 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 804 struct qla_hw_data *ha = vha->hw; 805 int ret = QLA_SUCCESS; 806 807 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 808 ql_dbg(ql_dbg_taskm, vha, 0x8005, 809 "Return:eh_wait.\n"); 810 return ret; 811 } 812 813 while (CMD_SP(cmd) && wait_iter--) { 814 msleep(ABORT_POLLING_PERIOD); 815 } 816 if (CMD_SP(cmd)) 817 ret = QLA_FUNCTION_FAILED; 818 819 return ret; 820} 821 822/* 823 * qla2x00_wait_for_hba_online 824 * Wait till the HBA is online after going through 825 * <= MAX_RETRIES_OF_ISP_ABORT or 826 * finally HBA is disabled ie marked offline 827 * 828 * Input: 829 * ha - pointer to host adapter structure 830 * 831 * Note: 832 * Does context switching-Release SPIN_LOCK 833 * (if any) before calling this routine. 834 * 835 * Return: 836 * Success (Adapter is online) : 0 837 * Failed (Adapter is offline/disabled) : 1 838 */ 839int 840qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 841{ 842 int return_status; 843 unsigned long wait_online; 844 struct qla_hw_data *ha = vha->hw; 845 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 846 847 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 848 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 849 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 850 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 851 ha->dpc_active) && time_before(jiffies, wait_online)) { 852 853 msleep(1000); 854 } 855 if (base_vha->flags.online) 856 return_status = QLA_SUCCESS; 857 else 858 return_status = QLA_FUNCTION_FAILED; 859 860 return (return_status); 861} 862 863/* 864 * qla2x00_wait_for_hba_ready 865 * Wait till the HBA is ready before doing driver unload 866 * 867 * Input: 868 * ha - pointer to host adapter structure 869 * 870 * Note: 871 * Does context switching-Release SPIN_LOCK 872 * (if any) before calling this routine. 873 * 874 */ 875static void 876qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 877{ 878 struct qla_hw_data *ha = vha->hw; 879 880 while (((qla2x00_reset_active(vha)) || ha->dpc_active || 881 ha->flags.mbox_busy) || 882 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 883 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) 884 msleep(1000); 885} 886 887int 888qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 889{ 890 int return_status; 891 unsigned long wait_reset; 892 struct qla_hw_data *ha = vha->hw; 893 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 894 895 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 896 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 897 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 898 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 899 ha->dpc_active) && time_before(jiffies, wait_reset)) { 900 901 msleep(1000); 902 903 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 904 ha->flags.chip_reset_done) 905 break; 906 } 907 if (ha->flags.chip_reset_done) 908 return_status = QLA_SUCCESS; 909 else 910 return_status = QLA_FUNCTION_FAILED; 911 912 return return_status; 913} 914 915static void 916sp_get(struct srb *sp) 917{ 918 atomic_inc(&sp->ref_count); 919} 920 921/************************************************************************** 922* qla2xxx_eh_abort 923* 924* Description: 925* The abort function will abort the specified command. 926* 927* Input: 928* cmd = Linux SCSI command packet to be aborted. 929* 930* Returns: 931* Either SUCCESS or FAILED. 932* 933* Note: 934* Only return FAILED if command not returned by firmware. 935**************************************************************************/ 936static int 937qla2xxx_eh_abort(struct scsi_cmnd *cmd) 938{ 939 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 940 srb_t *sp; 941 int ret; 942 unsigned int id; 943 uint64_t lun; 944 unsigned long flags; 945 int rval, wait = 0; 946 struct qla_hw_data *ha = vha->hw; 947 948 if (!CMD_SP(cmd)) 949 return SUCCESS; 950 951 ret = fc_block_scsi_eh(cmd); 952 if (ret != 0) 953 return ret; 954 ret = SUCCESS; 955 956 id = cmd->device->id; 957 lun = cmd->device->lun; 958 959 spin_lock_irqsave(&ha->hardware_lock, flags); 960 sp = (srb_t *) CMD_SP(cmd); 961 if (!sp) { 962 spin_unlock_irqrestore(&ha->hardware_lock, flags); 963 return SUCCESS; 964 } 965 966 ql_dbg(ql_dbg_taskm, vha, 0x8002, 967 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p\n", 968 vha->host_no, id, lun, sp, cmd); 969 970 /* Get a reference to the sp and drop the lock.*/ 971 sp_get(sp); 972 973 spin_unlock_irqrestore(&ha->hardware_lock, flags); 974 rval = ha->isp_ops->abort_command(sp); 975 if (rval) { 976 if (rval == QLA_FUNCTION_PARAMETER_ERROR) { 977 /* 978 * Decrement the ref_count since we can't find the 979 * command 980 */ 981 atomic_dec(&sp->ref_count); 982 ret = SUCCESS; 983 } else 984 ret = FAILED; 985 986 ql_dbg(ql_dbg_taskm, vha, 0x8003, 987 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval); 988 } else { 989 ql_dbg(ql_dbg_taskm, vha, 0x8004, 990 "Abort command mbx success cmd=%p.\n", cmd); 991 wait = 1; 992 } 993 994 spin_lock_irqsave(&ha->hardware_lock, flags); 995 /* 996 * Clear the slot in the oustanding_cmds array if we can't find the 997 * command to reclaim the resources. 998 */ 999 if (rval == QLA_FUNCTION_PARAMETER_ERROR) 1000 vha->req->outstanding_cmds[sp->handle] = NULL; 1001 sp->done(ha, sp, 0); 1002 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1003 1004 /* Did the command return during mailbox execution? */ 1005 if (ret == FAILED && !CMD_SP(cmd)) 1006 ret = SUCCESS; 1007 1008 /* Wait for the command to be returned. */ 1009 if (wait) { 1010 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) { 1011 ql_log(ql_log_warn, vha, 0x8006, 1012 "Abort handler timed out cmd=%p.\n", cmd); 1013 ret = FAILED; 1014 } 1015 } 1016 1017 ql_log(ql_log_info, vha, 0x801c, 1018 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n", 1019 vha->host_no, id, lun, wait, ret); 1020 1021 return ret; 1022} 1023 1024int 1025qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1026 uint64_t l, enum nexus_wait_type type) 1027{ 1028 int cnt, match, status; 1029 unsigned long flags; 1030 struct qla_hw_data *ha = vha->hw; 1031 struct req_que *req; 1032 srb_t *sp; 1033 struct scsi_cmnd *cmd; 1034 1035 status = QLA_SUCCESS; 1036 1037 spin_lock_irqsave(&ha->hardware_lock, flags); 1038 req = vha->req; 1039 for (cnt = 1; status == QLA_SUCCESS && 1040 cnt < req->num_outstanding_cmds; cnt++) { 1041 sp = req->outstanding_cmds[cnt]; 1042 if (!sp) 1043 continue; 1044 if (sp->type != SRB_SCSI_CMD) 1045 continue; 1046 if (vha->vp_idx != sp->fcport->vha->vp_idx) 1047 continue; 1048 match = 0; 1049 cmd = GET_CMD_SP(sp); 1050 switch (type) { 1051 case WAIT_HOST: 1052 match = 1; 1053 break; 1054 case WAIT_TARGET: 1055 match = cmd->device->id == t; 1056 break; 1057 case WAIT_LUN: 1058 match = (cmd->device->id == t && 1059 cmd->device->lun == l); 1060 break; 1061 } 1062 if (!match) 1063 continue; 1064 1065 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1066 status = qla2x00_eh_wait_on_command(cmd); 1067 spin_lock_irqsave(&ha->hardware_lock, flags); 1068 } 1069 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1070 1071 return status; 1072} 1073 1074static char *reset_errors[] = { 1075 "HBA not online", 1076 "HBA not ready", 1077 "Task management failed", 1078 "Waiting for command completions", 1079}; 1080 1081static int 1082__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, 1083 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int)) 1084{ 1085 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1086 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1087 int err; 1088 1089 if (!fcport) { 1090 return FAILED; 1091 } 1092 1093 err = fc_block_scsi_eh(cmd); 1094 if (err != 0) 1095 return err; 1096 1097 ql_log(ql_log_info, vha, 0x8009, 1098 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no, 1099 cmd->device->id, cmd->device->lun, cmd); 1100 1101 err = 0; 1102 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1103 ql_log(ql_log_warn, vha, 0x800a, 1104 "Wait for hba online failed for cmd=%p.\n", cmd); 1105 goto eh_reset_failed; 1106 } 1107 err = 2; 1108 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1) 1109 != QLA_SUCCESS) { 1110 ql_log(ql_log_warn, vha, 0x800c, 1111 "do_reset failed for cmd=%p.\n", cmd); 1112 goto eh_reset_failed; 1113 } 1114 err = 3; 1115 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, 1116 cmd->device->lun, type) != QLA_SUCCESS) { 1117 ql_log(ql_log_warn, vha, 0x800d, 1118 "wait for pending cmds failed for cmd=%p.\n", cmd); 1119 goto eh_reset_failed; 1120 } 1121 1122 ql_log(ql_log_info, vha, 0x800e, 1123 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name, 1124 vha->host_no, cmd->device->id, cmd->device->lun, cmd); 1125 1126 return SUCCESS; 1127 1128eh_reset_failed: 1129 ql_log(ql_log_info, vha, 0x800f, 1130 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name, 1131 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1132 cmd); 1133 return FAILED; 1134} 1135 1136static int 1137qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1138{ 1139 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1140 struct qla_hw_data *ha = vha->hw; 1141 1142 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, 1143 ha->isp_ops->lun_reset); 1144} 1145 1146static int 1147qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1148{ 1149 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1150 struct qla_hw_data *ha = vha->hw; 1151 1152 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, 1153 ha->isp_ops->target_reset); 1154} 1155 1156/************************************************************************** 1157* qla2xxx_eh_bus_reset 1158* 1159* Description: 1160* The bus reset function will reset the bus and abort any executing 1161* commands. 1162* 1163* Input: 1164* cmd = Linux SCSI command packet of the command that cause the 1165* bus reset. 1166* 1167* Returns: 1168* SUCCESS/FAILURE (defined as macro in scsi.h). 1169* 1170**************************************************************************/ 1171static int 1172qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1173{ 1174 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1175 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1176 int ret = FAILED; 1177 unsigned int id; 1178 uint64_t lun; 1179 1180 id = cmd->device->id; 1181 lun = cmd->device->lun; 1182 1183 if (!fcport) { 1184 return ret; 1185 } 1186 1187 ret = fc_block_scsi_eh(cmd); 1188 if (ret != 0) 1189 return ret; 1190 ret = FAILED; 1191 1192 ql_log(ql_log_info, vha, 0x8012, 1193 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1194 1195 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1196 ql_log(ql_log_fatal, vha, 0x8013, 1197 "Wait for hba online failed board disabled.\n"); 1198 goto eh_bus_reset_done; 1199 } 1200 1201 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1202 ret = SUCCESS; 1203 1204 if (ret == FAILED) 1205 goto eh_bus_reset_done; 1206 1207 /* Flush outstanding commands. */ 1208 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1209 QLA_SUCCESS) { 1210 ql_log(ql_log_warn, vha, 0x8014, 1211 "Wait for pending commands failed.\n"); 1212 ret = FAILED; 1213 } 1214 1215eh_bus_reset_done: 1216 ql_log(ql_log_warn, vha, 0x802b, 1217 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1218 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1219 1220 return ret; 1221} 1222 1223/************************************************************************** 1224* qla2xxx_eh_host_reset 1225* 1226* Description: 1227* The reset function will reset the Adapter. 1228* 1229* Input: 1230* cmd = Linux SCSI command packet of the command that cause the 1231* adapter reset. 1232* 1233* Returns: 1234* Either SUCCESS or FAILED. 1235* 1236* Note: 1237**************************************************************************/ 1238static int 1239qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1240{ 1241 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1242 struct qla_hw_data *ha = vha->hw; 1243 int ret = FAILED; 1244 unsigned int id; 1245 uint64_t lun; 1246 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1247 1248 id = cmd->device->id; 1249 lun = cmd->device->lun; 1250 1251 ql_log(ql_log_info, vha, 0x8018, 1252 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1253 1254 /* 1255 * No point in issuing another reset if one is active. Also do not 1256 * attempt a reset if we are updating flash. 1257 */ 1258 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1259 goto eh_host_reset_lock; 1260 1261 if (vha != base_vha) { 1262 if (qla2x00_vp_abort_isp(vha)) 1263 goto eh_host_reset_lock; 1264 } else { 1265 if (IS_P3P_TYPE(vha->hw)) { 1266 if (!qla82xx_fcoe_ctx_reset(vha)) { 1267 /* Ctx reset success */ 1268 ret = SUCCESS; 1269 goto eh_host_reset_lock; 1270 } 1271 /* fall thru if ctx reset failed */ 1272 } 1273 if (ha->wq) 1274 flush_workqueue(ha->wq); 1275 1276 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1277 if (ha->isp_ops->abort_isp(base_vha)) { 1278 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1279 /* failed. schedule dpc to try */ 1280 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1281 1282 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1283 ql_log(ql_log_warn, vha, 0x802a, 1284 "wait for hba online failed.\n"); 1285 goto eh_host_reset_lock; 1286 } 1287 } 1288 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1289 } 1290 1291 /* Waiting for command to be returned to OS.*/ 1292 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1293 QLA_SUCCESS) 1294 ret = SUCCESS; 1295 1296eh_host_reset_lock: 1297 ql_log(ql_log_info, vha, 0x8017, 1298 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1299 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1300 1301 return ret; 1302} 1303 1304/* 1305* qla2x00_loop_reset 1306* Issue loop reset. 1307* 1308* Input: 1309* ha = adapter block pointer. 1310* 1311* Returns: 1312* 0 = success 1313*/ 1314int 1315qla2x00_loop_reset(scsi_qla_host_t *vha) 1316{ 1317 int ret; 1318 struct fc_port *fcport; 1319 struct qla_hw_data *ha = vha->hw; 1320 1321 if (IS_QLAFX00(ha)) { 1322 return qlafx00_loop_reset(vha); 1323 } 1324 1325 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { 1326 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1327 if (fcport->port_type != FCT_TARGET) 1328 continue; 1329 1330 ret = ha->isp_ops->target_reset(fcport, 0, 0); 1331 if (ret != QLA_SUCCESS) { 1332 ql_dbg(ql_dbg_taskm, vha, 0x802c, 1333 "Bus Reset failed: Reset=%d " 1334 "d_id=%x.\n", ret, fcport->d_id.b24); 1335 } 1336 } 1337 } 1338 1339 1340 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1341 atomic_set(&vha->loop_state, LOOP_DOWN); 1342 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1343 qla2x00_mark_all_devices_lost(vha, 0); 1344 ret = qla2x00_full_login_lip(vha); 1345 if (ret != QLA_SUCCESS) { 1346 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1347 "full_login_lip=%d.\n", ret); 1348 } 1349 } 1350 1351 if (ha->flags.enable_lip_reset) { 1352 ret = qla2x00_lip_reset(vha); 1353 if (ret != QLA_SUCCESS) 1354 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1355 "lip_reset failed (%d).\n", ret); 1356 } 1357 1358 /* Issue marker command only when we are going to start the I/O */ 1359 vha->marker_needed = 1; 1360 1361 return QLA_SUCCESS; 1362} 1363 1364void 1365qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1366{ 1367 int que, cnt; 1368 unsigned long flags; 1369 srb_t *sp; 1370 struct qla_hw_data *ha = vha->hw; 1371 struct req_que *req; 1372 1373 qlt_host_reset_handler(ha); 1374 1375 spin_lock_irqsave(&ha->hardware_lock, flags); 1376 for (que = 0; que < ha->max_req_queues; que++) { 1377 req = ha->req_q_map[que]; 1378 if (!req) 1379 continue; 1380 if (!req->outstanding_cmds) 1381 continue; 1382 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1383 sp = req->outstanding_cmds[cnt]; 1384 if (sp) { 1385 req->outstanding_cmds[cnt] = NULL; 1386 sp->done(vha, sp, res); 1387 } 1388 } 1389 } 1390 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1391} 1392 1393static int 1394qla2xxx_slave_alloc(struct scsi_device *sdev) 1395{ 1396 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1397 1398 if (!rport || fc_remote_port_chkready(rport)) 1399 return -ENXIO; 1400 1401 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1402 1403 return 0; 1404} 1405 1406static int 1407qla2xxx_slave_configure(struct scsi_device *sdev) 1408{ 1409 scsi_qla_host_t *vha = shost_priv(sdev->host); 1410 struct req_que *req = vha->req; 1411 1412 if (IS_T10_PI_CAPABLE(vha->hw)) 1413 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1414 1415 scsi_change_queue_depth(sdev, req->max_q_depth); 1416 return 0; 1417} 1418 1419static void 1420qla2xxx_slave_destroy(struct scsi_device *sdev) 1421{ 1422 sdev->hostdata = NULL; 1423} 1424 1425/** 1426 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1427 * @ha: HA context 1428 * 1429 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1430 * supported addressing method. 1431 */ 1432static void 1433qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1434{ 1435 /* Assume a 32bit DMA mask. */ 1436 ha->flags.enable_64bit_addressing = 0; 1437 1438 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1439 /* Any upper-dword bits set? */ 1440 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1441 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { 1442 /* Ok, a 64bit DMA mask is applicable. */ 1443 ha->flags.enable_64bit_addressing = 1; 1444 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1445 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1446 return; 1447 } 1448 } 1449 1450 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1451 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); 1452} 1453 1454static void 1455qla2x00_enable_intrs(struct qla_hw_data *ha) 1456{ 1457 unsigned long flags = 0; 1458 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1459 1460 spin_lock_irqsave(&ha->hardware_lock, flags); 1461 ha->interrupts_on = 1; 1462 /* enable risc and host interrupts */ 1463 WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1464 RD_REG_WORD(®->ictrl); 1465 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1466 1467} 1468 1469static void 1470qla2x00_disable_intrs(struct qla_hw_data *ha) 1471{ 1472 unsigned long flags = 0; 1473 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1474 1475 spin_lock_irqsave(&ha->hardware_lock, flags); 1476 ha->interrupts_on = 0; 1477 /* disable risc and host interrupts */ 1478 WRT_REG_WORD(®->ictrl, 0); 1479 RD_REG_WORD(®->ictrl); 1480 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1481} 1482 1483static void 1484qla24xx_enable_intrs(struct qla_hw_data *ha) 1485{ 1486 unsigned long flags = 0; 1487 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1488 1489 spin_lock_irqsave(&ha->hardware_lock, flags); 1490 ha->interrupts_on = 1; 1491 WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); 1492 RD_REG_DWORD(®->ictrl); 1493 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1494} 1495 1496static void 1497qla24xx_disable_intrs(struct qla_hw_data *ha) 1498{ 1499 unsigned long flags = 0; 1500 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1501 1502 if (IS_NOPOLLING_TYPE(ha)) 1503 return; 1504 spin_lock_irqsave(&ha->hardware_lock, flags); 1505 ha->interrupts_on = 0; 1506 WRT_REG_DWORD(®->ictrl, 0); 1507 RD_REG_DWORD(®->ictrl); 1508 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1509} 1510 1511static int 1512qla2x00_iospace_config(struct qla_hw_data *ha) 1513{ 1514 resource_size_t pio; 1515 uint16_t msix; 1516 int cpus; 1517 1518 if (pci_request_selected_regions(ha->pdev, ha->bars, 1519 QLA2XXX_DRIVER_NAME)) { 1520 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 1521 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1522 pci_name(ha->pdev)); 1523 goto iospace_error_exit; 1524 } 1525 if (!(ha->bars & 1)) 1526 goto skip_pio; 1527 1528 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 1529 pio = pci_resource_start(ha->pdev, 0); 1530 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 1531 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1532 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 1533 "Invalid pci I/O region size (%s).\n", 1534 pci_name(ha->pdev)); 1535 pio = 0; 1536 } 1537 } else { 1538 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 1539 "Region #0 no a PIO resource (%s).\n", 1540 pci_name(ha->pdev)); 1541 pio = 0; 1542 } 1543 ha->pio_address = pio; 1544 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 1545 "PIO address=%llu.\n", 1546 (unsigned long long)ha->pio_address); 1547 1548skip_pio: 1549 /* Use MMIO operations for all accesses. */ 1550 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 1551 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 1552 "Region #1 not an MMIO resource (%s), aborting.\n", 1553 pci_name(ha->pdev)); 1554 goto iospace_error_exit; 1555 } 1556 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 1557 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 1558 "Invalid PCI mem region size (%s), aborting.\n", 1559 pci_name(ha->pdev)); 1560 goto iospace_error_exit; 1561 } 1562 1563 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 1564 if (!ha->iobase) { 1565 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 1566 "Cannot remap MMIO (%s), aborting.\n", 1567 pci_name(ha->pdev)); 1568 goto iospace_error_exit; 1569 } 1570 1571 /* Determine queue resources */ 1572 ha->max_req_queues = ha->max_rsp_queues = 1; 1573 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) || 1574 (ql2xmaxqueues > 1 && ql2xmultique_tag) || 1575 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 1576 goto mqiobase_exit; 1577 1578 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 1579 pci_resource_len(ha->pdev, 3)); 1580 if (ha->mqiobase) { 1581 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 1582 "MQIO Base=%p.\n", ha->mqiobase); 1583 /* Read MSIX vector size of the board */ 1584 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 1585 ha->msix_count = msix; 1586 /* Max queues are bounded by available msix vectors */ 1587 /* queue 0 uses two msix vectors */ 1588 if (ql2xmultique_tag) { 1589 cpus = num_online_cpus(); 1590 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ? 1591 (cpus + 1) : (ha->msix_count - 1); 1592 ha->max_req_queues = 2; 1593 } else if (ql2xmaxqueues > 1) { 1594 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ? 1595 QLA_MQ_SIZE : ql2xmaxqueues; 1596 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008, 1597 "QoS mode set, max no of request queues:%d.\n", 1598 ha->max_req_queues); 1599 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019, 1600 "QoS mode set, max no of request queues:%d.\n", 1601 ha->max_req_queues); 1602 } 1603 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 1604 "MSI-X vector count: %d.\n", msix); 1605 } else 1606 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 1607 "BAR 3 not enabled.\n"); 1608 1609mqiobase_exit: 1610 ha->msix_count = ha->max_rsp_queues + 1; 1611 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 1612 "MSIX Count:%d.\n", ha->msix_count); 1613 return (0); 1614 1615iospace_error_exit: 1616 return (-ENOMEM); 1617} 1618 1619 1620static int 1621qla83xx_iospace_config(struct qla_hw_data *ha) 1622{ 1623 uint16_t msix; 1624 int cpus; 1625 1626 if (pci_request_selected_regions(ha->pdev, ha->bars, 1627 QLA2XXX_DRIVER_NAME)) { 1628 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 1629 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1630 pci_name(ha->pdev)); 1631 1632 goto iospace_error_exit; 1633 } 1634 1635 /* Use MMIO operations for all accesses. */ 1636 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 1637 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 1638 "Invalid pci I/O region size (%s).\n", 1639 pci_name(ha->pdev)); 1640 goto iospace_error_exit; 1641 } 1642 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1643 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 1644 "Invalid PCI mem region size (%s), aborting\n", 1645 pci_name(ha->pdev)); 1646 goto iospace_error_exit; 1647 } 1648 1649 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 1650 if (!ha->iobase) { 1651 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 1652 "Cannot remap MMIO (%s), aborting.\n", 1653 pci_name(ha->pdev)); 1654 goto iospace_error_exit; 1655 } 1656 1657 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 1658 /* 83XX 26XX always use MQ type access for queues 1659 * - mbar 2, a.k.a region 4 */ 1660 ha->max_req_queues = ha->max_rsp_queues = 1; 1661 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 1662 pci_resource_len(ha->pdev, 4)); 1663 1664 if (!ha->mqiobase) { 1665 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 1666 "BAR2/region4 not enabled\n"); 1667 goto mqiobase_exit; 1668 } 1669 1670 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 1671 pci_resource_len(ha->pdev, 2)); 1672 if (ha->msixbase) { 1673 /* Read MSIX vector size of the board */ 1674 pci_read_config_word(ha->pdev, 1675 QLA_83XX_PCI_MSIX_CONTROL, &msix); 1676 ha->msix_count = msix; 1677 /* Max queues are bounded by available msix vectors */ 1678 /* queue 0 uses two msix vectors */ 1679 if (ql2xmultique_tag) { 1680 cpus = num_online_cpus(); 1681 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ? 1682 (cpus + 1) : (ha->msix_count - 1); 1683 ha->max_req_queues = 2; 1684 } else if (ql2xmaxqueues > 1) { 1685 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ? 1686 QLA_MQ_SIZE : ql2xmaxqueues; 1687 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c, 1688 "QoS mode set, max no of request queues:%d.\n", 1689 ha->max_req_queues); 1690 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 1691 "QoS mode set, max no of request queues:%d.\n", 1692 ha->max_req_queues); 1693 } 1694 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 1695 "MSI-X vector count: %d.\n", msix); 1696 } else 1697 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 1698 "BAR 1 not enabled.\n"); 1699 1700mqiobase_exit: 1701 ha->msix_count = ha->max_rsp_queues + 1; 1702 1703 qlt_83xx_iospace_config(ha); 1704 1705 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 1706 "MSIX Count:%d.\n", ha->msix_count); 1707 return 0; 1708 1709iospace_error_exit: 1710 return -ENOMEM; 1711} 1712 1713static struct isp_operations qla2100_isp_ops = { 1714 .pci_config = qla2100_pci_config, 1715 .reset_chip = qla2x00_reset_chip, 1716 .chip_diag = qla2x00_chip_diag, 1717 .config_rings = qla2x00_config_rings, 1718 .reset_adapter = qla2x00_reset_adapter, 1719 .nvram_config = qla2x00_nvram_config, 1720 .update_fw_options = qla2x00_update_fw_options, 1721 .load_risc = qla2x00_load_risc, 1722 .pci_info_str = qla2x00_pci_info_str, 1723 .fw_version_str = qla2x00_fw_version_str, 1724 .intr_handler = qla2100_intr_handler, 1725 .enable_intrs = qla2x00_enable_intrs, 1726 .disable_intrs = qla2x00_disable_intrs, 1727 .abort_command = qla2x00_abort_command, 1728 .target_reset = qla2x00_abort_target, 1729 .lun_reset = qla2x00_lun_reset, 1730 .fabric_login = qla2x00_login_fabric, 1731 .fabric_logout = qla2x00_fabric_logout, 1732 .calc_req_entries = qla2x00_calc_iocbs_32, 1733 .build_iocbs = qla2x00_build_scsi_iocbs_32, 1734 .prep_ms_iocb = qla2x00_prep_ms_iocb, 1735 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 1736 .read_nvram = qla2x00_read_nvram_data, 1737 .write_nvram = qla2x00_write_nvram_data, 1738 .fw_dump = qla2100_fw_dump, 1739 .beacon_on = NULL, 1740 .beacon_off = NULL, 1741 .beacon_blink = NULL, 1742 .read_optrom = qla2x00_read_optrom_data, 1743 .write_optrom = qla2x00_write_optrom_data, 1744 .get_flash_version = qla2x00_get_flash_version, 1745 .start_scsi = qla2x00_start_scsi, 1746 .abort_isp = qla2x00_abort_isp, 1747 .iospace_config = qla2x00_iospace_config, 1748 .initialize_adapter = qla2x00_initialize_adapter, 1749}; 1750 1751static struct isp_operations qla2300_isp_ops = { 1752 .pci_config = qla2300_pci_config, 1753 .reset_chip = qla2x00_reset_chip, 1754 .chip_diag = qla2x00_chip_diag, 1755 .config_rings = qla2x00_config_rings, 1756 .reset_adapter = qla2x00_reset_adapter, 1757 .nvram_config = qla2x00_nvram_config, 1758 .update_fw_options = qla2x00_update_fw_options, 1759 .load_risc = qla2x00_load_risc, 1760 .pci_info_str = qla2x00_pci_info_str, 1761 .fw_version_str = qla2x00_fw_version_str, 1762 .intr_handler = qla2300_intr_handler, 1763 .enable_intrs = qla2x00_enable_intrs, 1764 .disable_intrs = qla2x00_disable_intrs, 1765 .abort_command = qla2x00_abort_command, 1766 .target_reset = qla2x00_abort_target, 1767 .lun_reset = qla2x00_lun_reset, 1768 .fabric_login = qla2x00_login_fabric, 1769 .fabric_logout = qla2x00_fabric_logout, 1770 .calc_req_entries = qla2x00_calc_iocbs_32, 1771 .build_iocbs = qla2x00_build_scsi_iocbs_32, 1772 .prep_ms_iocb = qla2x00_prep_ms_iocb, 1773 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 1774 .read_nvram = qla2x00_read_nvram_data, 1775 .write_nvram = qla2x00_write_nvram_data, 1776 .fw_dump = qla2300_fw_dump, 1777 .beacon_on = qla2x00_beacon_on, 1778 .beacon_off = qla2x00_beacon_off, 1779 .beacon_blink = qla2x00_beacon_blink, 1780 .read_optrom = qla2x00_read_optrom_data, 1781 .write_optrom = qla2x00_write_optrom_data, 1782 .get_flash_version = qla2x00_get_flash_version, 1783 .start_scsi = qla2x00_start_scsi, 1784 .abort_isp = qla2x00_abort_isp, 1785 .iospace_config = qla2x00_iospace_config, 1786 .initialize_adapter = qla2x00_initialize_adapter, 1787}; 1788 1789static struct isp_operations qla24xx_isp_ops = { 1790 .pci_config = qla24xx_pci_config, 1791 .reset_chip = qla24xx_reset_chip, 1792 .chip_diag = qla24xx_chip_diag, 1793 .config_rings = qla24xx_config_rings, 1794 .reset_adapter = qla24xx_reset_adapter, 1795 .nvram_config = qla24xx_nvram_config, 1796 .update_fw_options = qla24xx_update_fw_options, 1797 .load_risc = qla24xx_load_risc, 1798 .pci_info_str = qla24xx_pci_info_str, 1799 .fw_version_str = qla24xx_fw_version_str, 1800 .intr_handler = qla24xx_intr_handler, 1801 .enable_intrs = qla24xx_enable_intrs, 1802 .disable_intrs = qla24xx_disable_intrs, 1803 .abort_command = qla24xx_abort_command, 1804 .target_reset = qla24xx_abort_target, 1805 .lun_reset = qla24xx_lun_reset, 1806 .fabric_login = qla24xx_login_fabric, 1807 .fabric_logout = qla24xx_fabric_logout, 1808 .calc_req_entries = NULL, 1809 .build_iocbs = NULL, 1810 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1811 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1812 .read_nvram = qla24xx_read_nvram_data, 1813 .write_nvram = qla24xx_write_nvram_data, 1814 .fw_dump = qla24xx_fw_dump, 1815 .beacon_on = qla24xx_beacon_on, 1816 .beacon_off = qla24xx_beacon_off, 1817 .beacon_blink = qla24xx_beacon_blink, 1818 .read_optrom = qla24xx_read_optrom_data, 1819 .write_optrom = qla24xx_write_optrom_data, 1820 .get_flash_version = qla24xx_get_flash_version, 1821 .start_scsi = qla24xx_start_scsi, 1822 .abort_isp = qla2x00_abort_isp, 1823 .iospace_config = qla2x00_iospace_config, 1824 .initialize_adapter = qla2x00_initialize_adapter, 1825}; 1826 1827static struct isp_operations qla25xx_isp_ops = { 1828 .pci_config = qla25xx_pci_config, 1829 .reset_chip = qla24xx_reset_chip, 1830 .chip_diag = qla24xx_chip_diag, 1831 .config_rings = qla24xx_config_rings, 1832 .reset_adapter = qla24xx_reset_adapter, 1833 .nvram_config = qla24xx_nvram_config, 1834 .update_fw_options = qla24xx_update_fw_options, 1835 .load_risc = qla24xx_load_risc, 1836 .pci_info_str = qla24xx_pci_info_str, 1837 .fw_version_str = qla24xx_fw_version_str, 1838 .intr_handler = qla24xx_intr_handler, 1839 .enable_intrs = qla24xx_enable_intrs, 1840 .disable_intrs = qla24xx_disable_intrs, 1841 .abort_command = qla24xx_abort_command, 1842 .target_reset = qla24xx_abort_target, 1843 .lun_reset = qla24xx_lun_reset, 1844 .fabric_login = qla24xx_login_fabric, 1845 .fabric_logout = qla24xx_fabric_logout, 1846 .calc_req_entries = NULL, 1847 .build_iocbs = NULL, 1848 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1849 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1850 .read_nvram = qla25xx_read_nvram_data, 1851 .write_nvram = qla25xx_write_nvram_data, 1852 .fw_dump = qla25xx_fw_dump, 1853 .beacon_on = qla24xx_beacon_on, 1854 .beacon_off = qla24xx_beacon_off, 1855 .beacon_blink = qla24xx_beacon_blink, 1856 .read_optrom = qla25xx_read_optrom_data, 1857 .write_optrom = qla24xx_write_optrom_data, 1858 .get_flash_version = qla24xx_get_flash_version, 1859 .start_scsi = qla24xx_dif_start_scsi, 1860 .abort_isp = qla2x00_abort_isp, 1861 .iospace_config = qla2x00_iospace_config, 1862 .initialize_adapter = qla2x00_initialize_adapter, 1863}; 1864 1865static struct isp_operations qla81xx_isp_ops = { 1866 .pci_config = qla25xx_pci_config, 1867 .reset_chip = qla24xx_reset_chip, 1868 .chip_diag = qla24xx_chip_diag, 1869 .config_rings = qla24xx_config_rings, 1870 .reset_adapter = qla24xx_reset_adapter, 1871 .nvram_config = qla81xx_nvram_config, 1872 .update_fw_options = qla81xx_update_fw_options, 1873 .load_risc = qla81xx_load_risc, 1874 .pci_info_str = qla24xx_pci_info_str, 1875 .fw_version_str = qla24xx_fw_version_str, 1876 .intr_handler = qla24xx_intr_handler, 1877 .enable_intrs = qla24xx_enable_intrs, 1878 .disable_intrs = qla24xx_disable_intrs, 1879 .abort_command = qla24xx_abort_command, 1880 .target_reset = qla24xx_abort_target, 1881 .lun_reset = qla24xx_lun_reset, 1882 .fabric_login = qla24xx_login_fabric, 1883 .fabric_logout = qla24xx_fabric_logout, 1884 .calc_req_entries = NULL, 1885 .build_iocbs = NULL, 1886 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1887 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1888 .read_nvram = NULL, 1889 .write_nvram = NULL, 1890 .fw_dump = qla81xx_fw_dump, 1891 .beacon_on = qla24xx_beacon_on, 1892 .beacon_off = qla24xx_beacon_off, 1893 .beacon_blink = qla83xx_beacon_blink, 1894 .read_optrom = qla25xx_read_optrom_data, 1895 .write_optrom = qla24xx_write_optrom_data, 1896 .get_flash_version = qla24xx_get_flash_version, 1897 .start_scsi = qla24xx_dif_start_scsi, 1898 .abort_isp = qla2x00_abort_isp, 1899 .iospace_config = qla2x00_iospace_config, 1900 .initialize_adapter = qla2x00_initialize_adapter, 1901}; 1902 1903static struct isp_operations qla82xx_isp_ops = { 1904 .pci_config = qla82xx_pci_config, 1905 .reset_chip = qla82xx_reset_chip, 1906 .chip_diag = qla24xx_chip_diag, 1907 .config_rings = qla82xx_config_rings, 1908 .reset_adapter = qla24xx_reset_adapter, 1909 .nvram_config = qla81xx_nvram_config, 1910 .update_fw_options = qla24xx_update_fw_options, 1911 .load_risc = qla82xx_load_risc, 1912 .pci_info_str = qla24xx_pci_info_str, 1913 .fw_version_str = qla24xx_fw_version_str, 1914 .intr_handler = qla82xx_intr_handler, 1915 .enable_intrs = qla82xx_enable_intrs, 1916 .disable_intrs = qla82xx_disable_intrs, 1917 .abort_command = qla24xx_abort_command, 1918 .target_reset = qla24xx_abort_target, 1919 .lun_reset = qla24xx_lun_reset, 1920 .fabric_login = qla24xx_login_fabric, 1921 .fabric_logout = qla24xx_fabric_logout, 1922 .calc_req_entries = NULL, 1923 .build_iocbs = NULL, 1924 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1925 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1926 .read_nvram = qla24xx_read_nvram_data, 1927 .write_nvram = qla24xx_write_nvram_data, 1928 .fw_dump = qla82xx_fw_dump, 1929 .beacon_on = qla82xx_beacon_on, 1930 .beacon_off = qla82xx_beacon_off, 1931 .beacon_blink = NULL, 1932 .read_optrom = qla82xx_read_optrom_data, 1933 .write_optrom = qla82xx_write_optrom_data, 1934 .get_flash_version = qla82xx_get_flash_version, 1935 .start_scsi = qla82xx_start_scsi, 1936 .abort_isp = qla82xx_abort_isp, 1937 .iospace_config = qla82xx_iospace_config, 1938 .initialize_adapter = qla2x00_initialize_adapter, 1939}; 1940 1941static struct isp_operations qla8044_isp_ops = { 1942 .pci_config = qla82xx_pci_config, 1943 .reset_chip = qla82xx_reset_chip, 1944 .chip_diag = qla24xx_chip_diag, 1945 .config_rings = qla82xx_config_rings, 1946 .reset_adapter = qla24xx_reset_adapter, 1947 .nvram_config = qla81xx_nvram_config, 1948 .update_fw_options = qla24xx_update_fw_options, 1949 .load_risc = qla82xx_load_risc, 1950 .pci_info_str = qla24xx_pci_info_str, 1951 .fw_version_str = qla24xx_fw_version_str, 1952 .intr_handler = qla8044_intr_handler, 1953 .enable_intrs = qla82xx_enable_intrs, 1954 .disable_intrs = qla82xx_disable_intrs, 1955 .abort_command = qla24xx_abort_command, 1956 .target_reset = qla24xx_abort_target, 1957 .lun_reset = qla24xx_lun_reset, 1958 .fabric_login = qla24xx_login_fabric, 1959 .fabric_logout = qla24xx_fabric_logout, 1960 .calc_req_entries = NULL, 1961 .build_iocbs = NULL, 1962 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1963 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1964 .read_nvram = NULL, 1965 .write_nvram = NULL, 1966 .fw_dump = qla8044_fw_dump, 1967 .beacon_on = qla82xx_beacon_on, 1968 .beacon_off = qla82xx_beacon_off, 1969 .beacon_blink = NULL, 1970 .read_optrom = qla8044_read_optrom_data, 1971 .write_optrom = qla8044_write_optrom_data, 1972 .get_flash_version = qla82xx_get_flash_version, 1973 .start_scsi = qla82xx_start_scsi, 1974 .abort_isp = qla8044_abort_isp, 1975 .iospace_config = qla82xx_iospace_config, 1976 .initialize_adapter = qla2x00_initialize_adapter, 1977}; 1978 1979static struct isp_operations qla83xx_isp_ops = { 1980 .pci_config = qla25xx_pci_config, 1981 .reset_chip = qla24xx_reset_chip, 1982 .chip_diag = qla24xx_chip_diag, 1983 .config_rings = qla24xx_config_rings, 1984 .reset_adapter = qla24xx_reset_adapter, 1985 .nvram_config = qla81xx_nvram_config, 1986 .update_fw_options = qla81xx_update_fw_options, 1987 .load_risc = qla81xx_load_risc, 1988 .pci_info_str = qla24xx_pci_info_str, 1989 .fw_version_str = qla24xx_fw_version_str, 1990 .intr_handler = qla24xx_intr_handler, 1991 .enable_intrs = qla24xx_enable_intrs, 1992 .disable_intrs = qla24xx_disable_intrs, 1993 .abort_command = qla24xx_abort_command, 1994 .target_reset = qla24xx_abort_target, 1995 .lun_reset = qla24xx_lun_reset, 1996 .fabric_login = qla24xx_login_fabric, 1997 .fabric_logout = qla24xx_fabric_logout, 1998 .calc_req_entries = NULL, 1999 .build_iocbs = NULL, 2000 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2001 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2002 .read_nvram = NULL, 2003 .write_nvram = NULL, 2004 .fw_dump = qla83xx_fw_dump, 2005 .beacon_on = qla24xx_beacon_on, 2006 .beacon_off = qla24xx_beacon_off, 2007 .beacon_blink = qla83xx_beacon_blink, 2008 .read_optrom = qla25xx_read_optrom_data, 2009 .write_optrom = qla24xx_write_optrom_data, 2010 .get_flash_version = qla24xx_get_flash_version, 2011 .start_scsi = qla24xx_dif_start_scsi, 2012 .abort_isp = qla2x00_abort_isp, 2013 .iospace_config = qla83xx_iospace_config, 2014 .initialize_adapter = qla2x00_initialize_adapter, 2015}; 2016 2017static struct isp_operations qlafx00_isp_ops = { 2018 .pci_config = qlafx00_pci_config, 2019 .reset_chip = qlafx00_soft_reset, 2020 .chip_diag = qlafx00_chip_diag, 2021 .config_rings = qlafx00_config_rings, 2022 .reset_adapter = qlafx00_soft_reset, 2023 .nvram_config = NULL, 2024 .update_fw_options = NULL, 2025 .load_risc = NULL, 2026 .pci_info_str = qlafx00_pci_info_str, 2027 .fw_version_str = qlafx00_fw_version_str, 2028 .intr_handler = qlafx00_intr_handler, 2029 .enable_intrs = qlafx00_enable_intrs, 2030 .disable_intrs = qlafx00_disable_intrs, 2031 .abort_command = qla24xx_async_abort_command, 2032 .target_reset = qlafx00_abort_target, 2033 .lun_reset = qlafx00_lun_reset, 2034 .fabric_login = NULL, 2035 .fabric_logout = NULL, 2036 .calc_req_entries = NULL, 2037 .build_iocbs = NULL, 2038 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2039 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2040 .read_nvram = qla24xx_read_nvram_data, 2041 .write_nvram = qla24xx_write_nvram_data, 2042 .fw_dump = NULL, 2043 .beacon_on = qla24xx_beacon_on, 2044 .beacon_off = qla24xx_beacon_off, 2045 .beacon_blink = NULL, 2046 .read_optrom = qla24xx_read_optrom_data, 2047 .write_optrom = qla24xx_write_optrom_data, 2048 .get_flash_version = qla24xx_get_flash_version, 2049 .start_scsi = qlafx00_start_scsi, 2050 .abort_isp = qlafx00_abort_isp, 2051 .iospace_config = qlafx00_iospace_config, 2052 .initialize_adapter = qlafx00_initialize_adapter, 2053}; 2054 2055static struct isp_operations qla27xx_isp_ops = { 2056 .pci_config = qla25xx_pci_config, 2057 .reset_chip = qla24xx_reset_chip, 2058 .chip_diag = qla24xx_chip_diag, 2059 .config_rings = qla24xx_config_rings, 2060 .reset_adapter = qla24xx_reset_adapter, 2061 .nvram_config = qla81xx_nvram_config, 2062 .update_fw_options = qla81xx_update_fw_options, 2063 .load_risc = qla81xx_load_risc, 2064 .pci_info_str = qla24xx_pci_info_str, 2065 .fw_version_str = qla24xx_fw_version_str, 2066 .intr_handler = qla24xx_intr_handler, 2067 .enable_intrs = qla24xx_enable_intrs, 2068 .disable_intrs = qla24xx_disable_intrs, 2069 .abort_command = qla24xx_abort_command, 2070 .target_reset = qla24xx_abort_target, 2071 .lun_reset = qla24xx_lun_reset, 2072 .fabric_login = qla24xx_login_fabric, 2073 .fabric_logout = qla24xx_fabric_logout, 2074 .calc_req_entries = NULL, 2075 .build_iocbs = NULL, 2076 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2077 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2078 .read_nvram = NULL, 2079 .write_nvram = NULL, 2080 .fw_dump = qla27xx_fwdump, 2081 .beacon_on = qla24xx_beacon_on, 2082 .beacon_off = qla24xx_beacon_off, 2083 .beacon_blink = qla83xx_beacon_blink, 2084 .read_optrom = qla25xx_read_optrom_data, 2085 .write_optrom = qla24xx_write_optrom_data, 2086 .get_flash_version = qla24xx_get_flash_version, 2087 .start_scsi = qla24xx_dif_start_scsi, 2088 .abort_isp = qla2x00_abort_isp, 2089 .iospace_config = qla83xx_iospace_config, 2090 .initialize_adapter = qla2x00_initialize_adapter, 2091}; 2092 2093static inline void 2094qla2x00_set_isp_flags(struct qla_hw_data *ha) 2095{ 2096 ha->device_type = DT_EXTENDED_IDS; 2097 switch (ha->pdev->device) { 2098 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2099 ha->device_type |= DT_ISP2100; 2100 ha->device_type &= ~DT_EXTENDED_IDS; 2101 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2102 break; 2103 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2104 ha->device_type |= DT_ISP2200; 2105 ha->device_type &= ~DT_EXTENDED_IDS; 2106 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2107 break; 2108 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2109 ha->device_type |= DT_ISP2300; 2110 ha->device_type |= DT_ZIO_SUPPORTED; 2111 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2112 break; 2113 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2114 ha->device_type |= DT_ISP2312; 2115 ha->device_type |= DT_ZIO_SUPPORTED; 2116 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2117 break; 2118 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2119 ha->device_type |= DT_ISP2322; 2120 ha->device_type |= DT_ZIO_SUPPORTED; 2121 if (ha->pdev->subsystem_vendor == 0x1028 && 2122 ha->pdev->subsystem_device == 0x0170) 2123 ha->device_type |= DT_OEM_001; 2124 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2125 break; 2126 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2127 ha->device_type |= DT_ISP6312; 2128 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2129 break; 2130 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2131 ha->device_type |= DT_ISP6322; 2132 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2133 break; 2134 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2135 ha->device_type |= DT_ISP2422; 2136 ha->device_type |= DT_ZIO_SUPPORTED; 2137 ha->device_type |= DT_FWI2; 2138 ha->device_type |= DT_IIDMA; 2139 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2140 break; 2141 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2142 ha->device_type |= DT_ISP2432; 2143 ha->device_type |= DT_ZIO_SUPPORTED; 2144 ha->device_type |= DT_FWI2; 2145 ha->device_type |= DT_IIDMA; 2146 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2147 break; 2148 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2149 ha->device_type |= DT_ISP8432; 2150 ha->device_type |= DT_ZIO_SUPPORTED; 2151 ha->device_type |= DT_FWI2; 2152 ha->device_type |= DT_IIDMA; 2153 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2154 break; 2155 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2156 ha->device_type |= DT_ISP5422; 2157 ha->device_type |= DT_FWI2; 2158 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2159 break; 2160 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2161 ha->device_type |= DT_ISP5432; 2162 ha->device_type |= DT_FWI2; 2163 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2164 break; 2165 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2166 ha->device_type |= DT_ISP2532; 2167 ha->device_type |= DT_ZIO_SUPPORTED; 2168 ha->device_type |= DT_FWI2; 2169 ha->device_type |= DT_IIDMA; 2170 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2171 break; 2172 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2173 ha->device_type |= DT_ISP8001; 2174 ha->device_type |= DT_ZIO_SUPPORTED; 2175 ha->device_type |= DT_FWI2; 2176 ha->device_type |= DT_IIDMA; 2177 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2178 break; 2179 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2180 ha->device_type |= DT_ISP8021; 2181 ha->device_type |= DT_ZIO_SUPPORTED; 2182 ha->device_type |= DT_FWI2; 2183 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2184 /* Initialize 82XX ISP flags */ 2185 qla82xx_init_flags(ha); 2186 break; 2187 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2188 ha->device_type |= DT_ISP8044; 2189 ha->device_type |= DT_ZIO_SUPPORTED; 2190 ha->device_type |= DT_FWI2; 2191 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2192 /* Initialize 82XX ISP flags */ 2193 qla82xx_init_flags(ha); 2194 break; 2195 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2196 ha->device_type |= DT_ISP2031; 2197 ha->device_type |= DT_ZIO_SUPPORTED; 2198 ha->device_type |= DT_FWI2; 2199 ha->device_type |= DT_IIDMA; 2200 ha->device_type |= DT_T10_PI; 2201 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2202 break; 2203 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2204 ha->device_type |= DT_ISP8031; 2205 ha->device_type |= DT_ZIO_SUPPORTED; 2206 ha->device_type |= DT_FWI2; 2207 ha->device_type |= DT_IIDMA; 2208 ha->device_type |= DT_T10_PI; 2209 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2210 break; 2211 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2212 ha->device_type |= DT_ISPFX00; 2213 break; 2214 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2215 ha->device_type |= DT_ISP2071; 2216 ha->device_type |= DT_ZIO_SUPPORTED; 2217 ha->device_type |= DT_FWI2; 2218 ha->device_type |= DT_IIDMA; 2219 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2220 break; 2221 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2222 ha->device_type |= DT_ISP2271; 2223 ha->device_type |= DT_ZIO_SUPPORTED; 2224 ha->device_type |= DT_FWI2; 2225 ha->device_type |= DT_IIDMA; 2226 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2227 break; 2228 } 2229 2230 if (IS_QLA82XX(ha)) 2231 ha->port_no = ha->portnum & 1; 2232 else { 2233 /* Get adapter physical port no from interrupt pin register. */ 2234 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2235 if (IS_QLA27XX(ha)) 2236 ha->port_no--; 2237 else 2238 ha->port_no = !(ha->port_no & 1); 2239 } 2240 2241 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2242 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2243 ha->device_type, ha->port_no, ha->fw_srisc_address); 2244} 2245 2246static void 2247qla2xxx_scan_start(struct Scsi_Host *shost) 2248{ 2249 scsi_qla_host_t *vha = shost_priv(shost); 2250 2251 if (vha->hw->flags.running_gold_fw) 2252 return; 2253 2254 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2255 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2256 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2257 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2258} 2259 2260static int 2261qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2262{ 2263 scsi_qla_host_t *vha = shost_priv(shost); 2264 2265 if (!vha->host) 2266 return 1; 2267 if (time > vha->hw->loop_reset_delay * HZ) 2268 return 1; 2269 2270 return atomic_read(&vha->loop_state) == LOOP_READY; 2271} 2272 2273/* 2274 * PCI driver interface 2275 */ 2276static int 2277qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2278{ 2279 int ret = -ENODEV; 2280 struct Scsi_Host *host; 2281 scsi_qla_host_t *base_vha = NULL; 2282 struct qla_hw_data *ha; 2283 char pci_info[30]; 2284 char fw_str[30], wq_name[30]; 2285 struct scsi_host_template *sht; 2286 int bars, mem_only = 0; 2287 uint16_t req_length = 0, rsp_length = 0; 2288 struct req_que *req = NULL; 2289 struct rsp_que *rsp = NULL; 2290 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2291 sht = &qla2xxx_driver_template; 2292 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2293 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2294 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2295 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2296 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2297 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2298 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2299 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2300 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2301 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2302 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2303 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2304 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2305 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271) { 2306 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2307 mem_only = 1; 2308 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2309 "Mem only adapter.\n"); 2310 } 2311 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2312 "Bars=%d.\n", bars); 2313 2314 if (mem_only) { 2315 if (pci_enable_device_mem(pdev)) 2316 goto probe_out; 2317 } else { 2318 if (pci_enable_device(pdev)) 2319 goto probe_out; 2320 } 2321 2322 /* This may fail but that's ok */ 2323 pci_enable_pcie_error_reporting(pdev); 2324 2325 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2326 if (!ha) { 2327 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2328 "Unable to allocate memory for ha.\n"); 2329 goto probe_out; 2330 } 2331 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2332 "Memory allocated for ha=%p.\n", ha); 2333 ha->pdev = pdev; 2334 ha->tgt.enable_class_2 = ql2xenableclass2; 2335 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2336 spin_lock_init(&ha->tgt.q_full_lock); 2337 2338 /* Clear our data area */ 2339 ha->bars = bars; 2340 ha->mem_only = mem_only; 2341 spin_lock_init(&ha->hardware_lock); 2342 spin_lock_init(&ha->vport_slock); 2343 mutex_init(&ha->selflogin_lock); 2344 mutex_init(&ha->optrom_mutex); 2345 2346 /* Set ISP-type information. */ 2347 qla2x00_set_isp_flags(ha); 2348 2349 /* Set EEH reset type to fundamental if required by hba */ 2350 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 2351 IS_QLA83XX(ha) || IS_QLA27XX(ha)) 2352 pdev->needs_freset = 1; 2353 2354 ha->prev_topology = 0; 2355 ha->init_cb_size = sizeof(init_cb_t); 2356 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2357 ha->optrom_size = OPTROM_SIZE_2300; 2358 2359 /* Assign ISP specific operations. */ 2360 if (IS_QLA2100(ha)) { 2361 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2362 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2363 req_length = REQUEST_ENTRY_CNT_2100; 2364 rsp_length = RESPONSE_ENTRY_CNT_2100; 2365 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2366 ha->gid_list_info_size = 4; 2367 ha->flash_conf_off = ~0; 2368 ha->flash_data_off = ~0; 2369 ha->nvram_conf_off = ~0; 2370 ha->nvram_data_off = ~0; 2371 ha->isp_ops = &qla2100_isp_ops; 2372 } else if (IS_QLA2200(ha)) { 2373 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2374 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 2375 req_length = REQUEST_ENTRY_CNT_2200; 2376 rsp_length = RESPONSE_ENTRY_CNT_2100; 2377 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2378 ha->gid_list_info_size = 4; 2379 ha->flash_conf_off = ~0; 2380 ha->flash_data_off = ~0; 2381 ha->nvram_conf_off = ~0; 2382 ha->nvram_data_off = ~0; 2383 ha->isp_ops = &qla2100_isp_ops; 2384 } else if (IS_QLA23XX(ha)) { 2385 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2386 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2387 req_length = REQUEST_ENTRY_CNT_2200; 2388 rsp_length = RESPONSE_ENTRY_CNT_2300; 2389 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2390 ha->gid_list_info_size = 6; 2391 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2392 ha->optrom_size = OPTROM_SIZE_2322; 2393 ha->flash_conf_off = ~0; 2394 ha->flash_data_off = ~0; 2395 ha->nvram_conf_off = ~0; 2396 ha->nvram_data_off = ~0; 2397 ha->isp_ops = &qla2300_isp_ops; 2398 } else if (IS_QLA24XX_TYPE(ha)) { 2399 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2400 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2401 req_length = REQUEST_ENTRY_CNT_24XX; 2402 rsp_length = RESPONSE_ENTRY_CNT_2300; 2403 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2404 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2405 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2406 ha->gid_list_info_size = 8; 2407 ha->optrom_size = OPTROM_SIZE_24XX; 2408 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2409 ha->isp_ops = &qla24xx_isp_ops; 2410 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2411 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2412 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2413 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2414 } else if (IS_QLA25XX(ha)) { 2415 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2416 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2417 req_length = REQUEST_ENTRY_CNT_24XX; 2418 rsp_length = RESPONSE_ENTRY_CNT_2300; 2419 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2420 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2421 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2422 ha->gid_list_info_size = 8; 2423 ha->optrom_size = OPTROM_SIZE_25XX; 2424 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2425 ha->isp_ops = &qla25xx_isp_ops; 2426 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2427 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2428 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2429 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2430 } else if (IS_QLA81XX(ha)) { 2431 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2432 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2433 req_length = REQUEST_ENTRY_CNT_24XX; 2434 rsp_length = RESPONSE_ENTRY_CNT_2300; 2435 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2436 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2437 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2438 ha->gid_list_info_size = 8; 2439 ha->optrom_size = OPTROM_SIZE_81XX; 2440 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2441 ha->isp_ops = &qla81xx_isp_ops; 2442 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2443 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2444 ha->nvram_conf_off = ~0; 2445 ha->nvram_data_off = ~0; 2446 } else if (IS_QLA82XX(ha)) { 2447 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2448 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2449 req_length = REQUEST_ENTRY_CNT_82XX; 2450 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2451 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2452 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2453 ha->gid_list_info_size = 8; 2454 ha->optrom_size = OPTROM_SIZE_82XX; 2455 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2456 ha->isp_ops = &qla82xx_isp_ops; 2457 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2458 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2459 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2460 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2461 } else if (IS_QLA8044(ha)) { 2462 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2463 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2464 req_length = REQUEST_ENTRY_CNT_82XX; 2465 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2466 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2467 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2468 ha->gid_list_info_size = 8; 2469 ha->optrom_size = OPTROM_SIZE_83XX; 2470 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2471 ha->isp_ops = &qla8044_isp_ops; 2472 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2473 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2474 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2475 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2476 } else if (IS_QLA83XX(ha)) { 2477 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2478 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2479 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2480 req_length = REQUEST_ENTRY_CNT_83XX; 2481 rsp_length = RESPONSE_ENTRY_CNT_2300; 2482 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2483 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2484 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2485 ha->gid_list_info_size = 8; 2486 ha->optrom_size = OPTROM_SIZE_83XX; 2487 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2488 ha->isp_ops = &qla83xx_isp_ops; 2489 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2490 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2491 ha->nvram_conf_off = ~0; 2492 ha->nvram_data_off = ~0; 2493 } else if (IS_QLAFX00(ha)) { 2494 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 2495 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 2496 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 2497 req_length = REQUEST_ENTRY_CNT_FX00; 2498 rsp_length = RESPONSE_ENTRY_CNT_FX00; 2499 ha->isp_ops = &qlafx00_isp_ops; 2500 ha->port_down_retry_count = 30; /* default value */ 2501 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 2502 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 2503 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 2504 ha->mr.fw_hbt_en = 1; 2505 ha->mr.host_info_resend = false; 2506 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 2507 } else if (IS_QLA27XX(ha)) { 2508 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2509 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2510 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2511 req_length = REQUEST_ENTRY_CNT_24XX; 2512 rsp_length = RESPONSE_ENTRY_CNT_2300; 2513 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2514 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2515 ha->gid_list_info_size = 8; 2516 ha->optrom_size = OPTROM_SIZE_83XX; 2517 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2518 ha->isp_ops = &qla27xx_isp_ops; 2519 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2520 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2521 ha->nvram_conf_off = ~0; 2522 ha->nvram_data_off = ~0; 2523 } 2524 2525 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 2526 "mbx_count=%d, req_length=%d, " 2527 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 2528 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 2529 "max_fibre_devices=%d.\n", 2530 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 2531 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 2532 ha->nvram_npiv_size, ha->max_fibre_devices); 2533 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 2534 "isp_ops=%p, flash_conf_off=%d, " 2535 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 2536 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 2537 ha->nvram_conf_off, ha->nvram_data_off); 2538 2539 /* Configure PCI I/O space */ 2540 ret = ha->isp_ops->iospace_config(ha); 2541 if (ret) 2542 goto iospace_config_failed; 2543 2544 ql_log_pci(ql_log_info, pdev, 0x001d, 2545 "Found an ISP%04X irq %d iobase 0x%p.\n", 2546 pdev->device, pdev->irq, ha->iobase); 2547 mutex_init(&ha->vport_lock); 2548 init_completion(&ha->mbx_cmd_comp); 2549 complete(&ha->mbx_cmd_comp); 2550 init_completion(&ha->mbx_intr_comp); 2551 init_completion(&ha->dcbx_comp); 2552 init_completion(&ha->lb_portup_comp); 2553 2554 set_bit(0, (unsigned long *) ha->vp_idx_map); 2555 2556 qla2x00_config_dma_addressing(ha); 2557 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 2558 "64 Bit addressing is %s.\n", 2559 ha->flags.enable_64bit_addressing ? "enable" : 2560 "disable"); 2561 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 2562 if (ret) { 2563 ql_log_pci(ql_log_fatal, pdev, 0x0031, 2564 "Failed to allocate memory for adapter, aborting.\n"); 2565 2566 goto probe_hw_failed; 2567 } 2568 2569 req->max_q_depth = MAX_Q_DEPTH; 2570 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 2571 req->max_q_depth = ql2xmaxqdepth; 2572 2573 2574 base_vha = qla2x00_create_host(sht, ha); 2575 if (!base_vha) { 2576 ret = -ENOMEM; 2577 qla2x00_mem_free(ha); 2578 qla2x00_free_req_que(ha, req); 2579 qla2x00_free_rsp_que(ha, rsp); 2580 goto probe_hw_failed; 2581 } 2582 2583 pci_set_drvdata(pdev, base_vha); 2584 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 2585 2586 host = base_vha->host; 2587 base_vha->req = req; 2588 if (IS_QLA2XXX_MIDTYPE(ha)) 2589 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx; 2590 else 2591 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 2592 base_vha->vp_idx; 2593 2594 /* Setup fcport template structure. */ 2595 ha->mr.fcport.vha = base_vha; 2596 ha->mr.fcport.port_type = FCT_UNKNOWN; 2597 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 2598 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 2599 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 2600 ha->mr.fcport.scan_state = 1; 2601 2602 /* Set the SG table size based on ISP type */ 2603 if (!IS_FWI2_CAPABLE(ha)) { 2604 if (IS_QLA2100(ha)) 2605 host->sg_tablesize = 32; 2606 } else { 2607 if (!IS_QLA82XX(ha)) 2608 host->sg_tablesize = QLA_SG_ALL; 2609 } 2610 host->max_id = ha->max_fibre_devices; 2611 host->cmd_per_lun = 3; 2612 host->unique_id = host->host_no; 2613 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 2614 host->max_cmd_len = 32; 2615 else 2616 host->max_cmd_len = MAX_CMDSZ; 2617 host->max_channel = MAX_BUSES - 1; 2618 /* Older HBAs support only 16-bit LUNs */ 2619 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 2620 ql2xmaxlun > 0xffff) 2621 host->max_lun = 0xffff; 2622 else 2623 host->max_lun = ql2xmaxlun; 2624 host->transportt = qla2xxx_transport_template; 2625 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 2626 2627 ql_dbg(ql_dbg_init, base_vha, 0x0033, 2628 "max_id=%d this_id=%d " 2629 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 2630 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 2631 host->this_id, host->cmd_per_lun, host->unique_id, 2632 host->max_cmd_len, host->max_channel, host->max_lun, 2633 host->transportt, sht->vendor_id); 2634 2635que_init: 2636 /* Alloc arrays of request and response ring ptrs */ 2637 if (!qla2x00_alloc_queues(ha, req, rsp)) { 2638 ql_log(ql_log_fatal, base_vha, 0x003d, 2639 "Failed to allocate memory for queue pointers..." 2640 "aborting.\n"); 2641 goto probe_init_failed; 2642 } 2643 2644 qlt_probe_one_stage1(base_vha, ha); 2645 2646 /* Set up the irqs */ 2647 ret = qla2x00_request_irqs(ha, rsp); 2648 if (ret) 2649 goto probe_init_failed; 2650 2651 pci_save_state(pdev); 2652 2653 /* Assign back pointers */ 2654 rsp->req = req; 2655 req->rsp = rsp; 2656 2657 if (IS_QLAFX00(ha)) { 2658 ha->rsp_q_map[0] = rsp; 2659 ha->req_q_map[0] = req; 2660 set_bit(0, ha->req_qid_map); 2661 set_bit(0, ha->rsp_qid_map); 2662 } 2663 2664 /* FWI2-capable only. */ 2665 req->req_q_in = &ha->iobase->isp24.req_q_in; 2666 req->req_q_out = &ha->iobase->isp24.req_q_out; 2667 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 2668 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 2669 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 2670 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 2671 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 2672 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 2673 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 2674 } 2675 2676 if (IS_QLAFX00(ha)) { 2677 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 2678 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 2679 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 2680 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 2681 } 2682 2683 if (IS_P3P_TYPE(ha)) { 2684 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 2685 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 2686 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 2687 } 2688 2689 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 2690 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 2691 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 2692 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 2693 "req->req_q_in=%p req->req_q_out=%p " 2694 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 2695 req->req_q_in, req->req_q_out, 2696 rsp->rsp_q_in, rsp->rsp_q_out); 2697 ql_dbg(ql_dbg_init, base_vha, 0x003e, 2698 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 2699 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 2700 ql_dbg(ql_dbg_init, base_vha, 0x003f, 2701 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 2702 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 2703 2704 if (ha->isp_ops->initialize_adapter(base_vha)) { 2705 ql_log(ql_log_fatal, base_vha, 0x00d6, 2706 "Failed to initialize adapter - Adapter flags %x.\n", 2707 base_vha->device_flags); 2708 2709 if (IS_QLA82XX(ha)) { 2710 qla82xx_idc_lock(ha); 2711 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2712 QLA8XXX_DEV_FAILED); 2713 qla82xx_idc_unlock(ha); 2714 ql_log(ql_log_fatal, base_vha, 0x00d7, 2715 "HW State: FAILED.\n"); 2716 } else if (IS_QLA8044(ha)) { 2717 qla8044_idc_lock(ha); 2718 qla8044_wr_direct(base_vha, 2719 QLA8044_CRB_DEV_STATE_INDEX, 2720 QLA8XXX_DEV_FAILED); 2721 qla8044_idc_unlock(ha); 2722 ql_log(ql_log_fatal, base_vha, 0x0150, 2723 "HW State: FAILED.\n"); 2724 } 2725 2726 ret = -ENODEV; 2727 goto probe_failed; 2728 } 2729 2730 if (IS_QLAFX00(ha)) 2731 host->can_queue = QLAFX00_MAX_CANQUEUE; 2732 else 2733 host->can_queue = req->num_outstanding_cmds - 10; 2734 2735 ql_dbg(ql_dbg_init, base_vha, 0x0032, 2736 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 2737 host->can_queue, base_vha->req, 2738 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 2739 2740 if (ha->mqenable) { 2741 if (qla25xx_setup_mode(base_vha)) { 2742 ql_log(ql_log_warn, base_vha, 0x00ec, 2743 "Failed to create queues, falling back to single queue mode.\n"); 2744 goto que_init; 2745 } 2746 } 2747 2748 if (ha->flags.running_gold_fw) 2749 goto skip_dpc; 2750 2751 /* 2752 * Startup the kernel thread for this host adapter 2753 */ 2754 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 2755 "%s_dpc", base_vha->host_str); 2756 if (IS_ERR(ha->dpc_thread)) { 2757 ql_log(ql_log_fatal, base_vha, 0x00ed, 2758 "Failed to start DPC thread.\n"); 2759 ret = PTR_ERR(ha->dpc_thread); 2760 goto probe_failed; 2761 } 2762 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 2763 "DPC thread started successfully.\n"); 2764 2765 /* 2766 * If we're not coming up in initiator mode, we might sit for 2767 * a while without waking up the dpc thread, which leads to a 2768 * stuck process warning. So just kick the dpc once here and 2769 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 2770 */ 2771 qla2xxx_wake_dpc(base_vha); 2772 2773 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 2774 2775 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 2776 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 2777 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 2778 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 2779 2780 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 2781 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 2782 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 2783 INIT_WORK(&ha->idc_state_handler, 2784 qla83xx_idc_state_handler_work); 2785 INIT_WORK(&ha->nic_core_unrecoverable, 2786 qla83xx_nic_core_unrecoverable_work); 2787 } 2788 2789skip_dpc: 2790 list_add_tail(&base_vha->list, &ha->vp_list); 2791 base_vha->host->irq = ha->pdev->irq; 2792 2793 /* Initialized the timer */ 2794 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL); 2795 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 2796 "Started qla2x00_timer with " 2797 "interval=%d.\n", WATCH_INTERVAL); 2798 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 2799 "Detected hba at address=%p.\n", 2800 ha); 2801 2802 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 2803 if (ha->fw_attributes & BIT_4) { 2804 int prot = 0, guard; 2805 base_vha->flags.difdix_supported = 1; 2806 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 2807 "Registering for DIF/DIX type 1 and 3 protection.\n"); 2808 if (ql2xenabledif == 1) 2809 prot = SHOST_DIX_TYPE0_PROTECTION; 2810 scsi_host_set_prot(host, 2811 prot | SHOST_DIF_TYPE1_PROTECTION 2812 | SHOST_DIF_TYPE2_PROTECTION 2813 | SHOST_DIF_TYPE3_PROTECTION 2814 | SHOST_DIX_TYPE1_PROTECTION 2815 | SHOST_DIX_TYPE2_PROTECTION 2816 | SHOST_DIX_TYPE3_PROTECTION); 2817 2818 guard = SHOST_DIX_GUARD_CRC; 2819 2820 if (IS_PI_IPGUARD_CAPABLE(ha) && 2821 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 2822 guard |= SHOST_DIX_GUARD_IP; 2823 2824 scsi_host_set_guard(host, guard); 2825 } else 2826 base_vha->flags.difdix_supported = 0; 2827 } 2828 2829 ha->isp_ops->enable_intrs(ha); 2830 2831 if (IS_QLAFX00(ha)) { 2832 ret = qlafx00_fx_disc(base_vha, 2833 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 2834 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 2835 QLA_SG_ALL : 128; 2836 } 2837 2838 ret = scsi_add_host(host, &pdev->dev); 2839 if (ret) 2840 goto probe_failed; 2841 2842 base_vha->flags.init_done = 1; 2843 base_vha->flags.online = 1; 2844 ha->prev_minidump_failed = 0; 2845 2846 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 2847 "Init done and hba is online.\n"); 2848 2849 if (qla_ini_mode_enabled(base_vha)) 2850 scsi_scan_host(host); 2851 else 2852 ql_dbg(ql_dbg_init, base_vha, 0x0122, 2853 "skipping scsi_scan_host() for non-initiator port\n"); 2854 2855 qla2x00_alloc_sysfs_attr(base_vha); 2856 2857 if (IS_QLAFX00(ha)) { 2858 ret = qlafx00_fx_disc(base_vha, 2859 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 2860 2861 /* Register system information */ 2862 ret = qlafx00_fx_disc(base_vha, 2863 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 2864 } 2865 2866 qla2x00_init_host_attr(base_vha); 2867 2868 qla2x00_dfs_setup(base_vha); 2869 2870 ql_log(ql_log_info, base_vha, 0x00fb, 2871 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 2872 ql_log(ql_log_info, base_vha, 0x00fc, 2873 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 2874 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info), 2875 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 2876 base_vha->host_no, 2877 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 2878 2879 qlt_add_target(ha, base_vha); 2880 2881 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 2882 return 0; 2883 2884probe_init_failed: 2885 qla2x00_free_req_que(ha, req); 2886 ha->req_q_map[0] = NULL; 2887 clear_bit(0, ha->req_qid_map); 2888 qla2x00_free_rsp_que(ha, rsp); 2889 ha->rsp_q_map[0] = NULL; 2890 clear_bit(0, ha->rsp_qid_map); 2891 ha->max_req_queues = ha->max_rsp_queues = 0; 2892 2893probe_failed: 2894 if (base_vha->timer_active) 2895 qla2x00_stop_timer(base_vha); 2896 base_vha->flags.online = 0; 2897 if (ha->dpc_thread) { 2898 struct task_struct *t = ha->dpc_thread; 2899 2900 ha->dpc_thread = NULL; 2901 kthread_stop(t); 2902 } 2903 2904 qla2x00_free_device(base_vha); 2905 2906 scsi_host_put(base_vha->host); 2907 2908probe_hw_failed: 2909 qla2x00_clear_drv_active(ha); 2910 2911iospace_config_failed: 2912 if (IS_P3P_TYPE(ha)) { 2913 if (!ha->nx_pcibase) 2914 iounmap((device_reg_t *)ha->nx_pcibase); 2915 if (!ql2xdbwr) 2916 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 2917 } else { 2918 if (ha->iobase) 2919 iounmap(ha->iobase); 2920 if (ha->cregbase) 2921 iounmap(ha->cregbase); 2922 } 2923 pci_release_selected_regions(ha->pdev, ha->bars); 2924 kfree(ha); 2925 ha = NULL; 2926 2927probe_out: 2928 pci_disable_device(pdev); 2929 return ret; 2930} 2931 2932static void 2933qla2x00_shutdown(struct pci_dev *pdev) 2934{ 2935 scsi_qla_host_t *vha; 2936 struct qla_hw_data *ha; 2937 2938 if (!atomic_read(&pdev->enable_cnt)) 2939 return; 2940 2941 vha = pci_get_drvdata(pdev); 2942 ha = vha->hw; 2943 2944 /* Notify ISPFX00 firmware */ 2945 if (IS_QLAFX00(ha)) 2946 qlafx00_driver_shutdown(vha, 20); 2947 2948 /* Turn-off FCE trace */ 2949 if (ha->flags.fce_enabled) { 2950 qla2x00_disable_fce_trace(vha, NULL, NULL); 2951 ha->flags.fce_enabled = 0; 2952 } 2953 2954 /* Turn-off EFT trace */ 2955 if (ha->eft) 2956 qla2x00_disable_eft_trace(vha); 2957 2958 /* Stop currently executing firmware. */ 2959 qla2x00_try_to_stop_firmware(vha); 2960 2961 /* Turn adapter off line */ 2962 vha->flags.online = 0; 2963 2964 /* turn-off interrupts on the card */ 2965 if (ha->interrupts_on) { 2966 vha->flags.init_done = 0; 2967 ha->isp_ops->disable_intrs(ha); 2968 } 2969 2970 qla2x00_free_irqs(vha); 2971 2972 qla2x00_free_fw_dump(ha); 2973 2974 pci_disable_pcie_error_reporting(pdev); 2975 pci_disable_device(pdev); 2976} 2977 2978/* Deletes all the virtual ports for a given ha */ 2979static void 2980qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 2981{ 2982 struct Scsi_Host *scsi_host; 2983 scsi_qla_host_t *vha; 2984 unsigned long flags; 2985 2986 mutex_lock(&ha->vport_lock); 2987 while (ha->cur_vport_count) { 2988 spin_lock_irqsave(&ha->vport_slock, flags); 2989 2990 BUG_ON(base_vha->list.next == &ha->vp_list); 2991 /* This assumes first entry in ha->vp_list is always base vha */ 2992 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 2993 scsi_host = scsi_host_get(vha->host); 2994 2995 spin_unlock_irqrestore(&ha->vport_slock, flags); 2996 mutex_unlock(&ha->vport_lock); 2997 2998 fc_vport_terminate(vha->fc_vport); 2999 scsi_host_put(vha->host); 3000 3001 mutex_lock(&ha->vport_lock); 3002 } 3003 mutex_unlock(&ha->vport_lock); 3004} 3005 3006/* Stops all deferred work threads */ 3007static void 3008qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3009{ 3010 /* Flush the work queue and remove it */ 3011 if (ha->wq) { 3012 flush_workqueue(ha->wq); 3013 destroy_workqueue(ha->wq); 3014 ha->wq = NULL; 3015 } 3016 3017 /* Cancel all work and destroy DPC workqueues */ 3018 if (ha->dpc_lp_wq) { 3019 cancel_work_sync(&ha->idc_aen); 3020 destroy_workqueue(ha->dpc_lp_wq); 3021 ha->dpc_lp_wq = NULL; 3022 } 3023 3024 if (ha->dpc_hp_wq) { 3025 cancel_work_sync(&ha->nic_core_reset); 3026 cancel_work_sync(&ha->idc_state_handler); 3027 cancel_work_sync(&ha->nic_core_unrecoverable); 3028 destroy_workqueue(ha->dpc_hp_wq); 3029 ha->dpc_hp_wq = NULL; 3030 } 3031 3032 /* Kill the kernel thread for this host */ 3033 if (ha->dpc_thread) { 3034 struct task_struct *t = ha->dpc_thread; 3035 3036 /* 3037 * qla2xxx_wake_dpc checks for ->dpc_thread 3038 * so we need to zero it out. 3039 */ 3040 ha->dpc_thread = NULL; 3041 kthread_stop(t); 3042 } 3043} 3044 3045static void 3046qla2x00_unmap_iobases(struct qla_hw_data *ha) 3047{ 3048 if (IS_QLA82XX(ha)) { 3049 3050 iounmap((device_reg_t *)ha->nx_pcibase); 3051 if (!ql2xdbwr) 3052 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3053 } else { 3054 if (ha->iobase) 3055 iounmap(ha->iobase); 3056 3057 if (ha->cregbase) 3058 iounmap(ha->cregbase); 3059 3060 if (ha->mqiobase) 3061 iounmap(ha->mqiobase); 3062 3063 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase) 3064 iounmap(ha->msixbase); 3065 } 3066} 3067 3068static void 3069qla2x00_clear_drv_active(struct qla_hw_data *ha) 3070{ 3071 if (IS_QLA8044(ha)) { 3072 qla8044_idc_lock(ha); 3073 qla8044_clear_drv_active(ha); 3074 qla8044_idc_unlock(ha); 3075 } else if (IS_QLA82XX(ha)) { 3076 qla82xx_idc_lock(ha); 3077 qla82xx_clear_drv_active(ha); 3078 qla82xx_idc_unlock(ha); 3079 } 3080} 3081 3082static void 3083qla2x00_remove_one(struct pci_dev *pdev) 3084{ 3085 scsi_qla_host_t *base_vha; 3086 struct qla_hw_data *ha; 3087 3088 base_vha = pci_get_drvdata(pdev); 3089 ha = base_vha->hw; 3090 3091 /* Indicate device removal to prevent future board_disable and wait 3092 * until any pending board_disable has completed. */ 3093 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3094 cancel_work_sync(&ha->board_disable); 3095 3096 /* 3097 * If the PCI device is disabled then there was a PCI-disconnect and 3098 * qla2x00_disable_board_on_pci_error has taken care of most of the 3099 * resources. 3100 */ 3101 if (!atomic_read(&pdev->enable_cnt)) { 3102 scsi_host_put(base_vha->host); 3103 kfree(ha); 3104 pci_set_drvdata(pdev, NULL); 3105 return; 3106 } 3107 3108 qla2x00_wait_for_hba_ready(base_vha); 3109 3110 set_bit(UNLOADING, &base_vha->dpc_flags); 3111 3112 if (IS_QLAFX00(ha)) 3113 qlafx00_driver_shutdown(base_vha, 20); 3114 3115 qla2x00_delete_all_vps(ha, base_vha); 3116 3117 if (IS_QLA8031(ha)) { 3118 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3119 "Clearing fcoe driver presence.\n"); 3120 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3121 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3122 "Error while clearing DRV-Presence.\n"); 3123 } 3124 3125 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 3126 3127 qla2x00_dfs_remove(base_vha); 3128 3129 qla84xx_put_chip(base_vha); 3130 3131 /* Laser should be disabled only for ISP2031 */ 3132 if (IS_QLA2031(ha)) 3133 qla83xx_disable_laser(base_vha); 3134 3135 /* Disable timer */ 3136 if (base_vha->timer_active) 3137 qla2x00_stop_timer(base_vha); 3138 3139 base_vha->flags.online = 0; 3140 3141 qla2x00_destroy_deferred_work(ha); 3142 3143 qlt_remove_target(ha, base_vha); 3144 3145 qla2x00_free_sysfs_attr(base_vha, true); 3146 3147 fc_remove_host(base_vha->host); 3148 3149 scsi_remove_host(base_vha->host); 3150 3151 qla2x00_free_device(base_vha); 3152 3153 qla2x00_clear_drv_active(ha); 3154 3155 scsi_host_put(base_vha->host); 3156 3157 qla2x00_unmap_iobases(ha); 3158 3159 pci_release_selected_regions(ha->pdev, ha->bars); 3160 kfree(ha); 3161 ha = NULL; 3162 3163 pci_disable_pcie_error_reporting(pdev); 3164 3165 pci_disable_device(pdev); 3166} 3167 3168static void 3169qla2x00_free_device(scsi_qla_host_t *vha) 3170{ 3171 struct qla_hw_data *ha = vha->hw; 3172 3173 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3174 3175 /* Disable timer */ 3176 if (vha->timer_active) 3177 qla2x00_stop_timer(vha); 3178 3179 qla25xx_delete_queues(vha); 3180 3181 if (ha->flags.fce_enabled) 3182 qla2x00_disable_fce_trace(vha, NULL, NULL); 3183 3184 if (ha->eft) 3185 qla2x00_disable_eft_trace(vha); 3186 3187 /* Stop currently executing firmware. */ 3188 qla2x00_try_to_stop_firmware(vha); 3189 3190 vha->flags.online = 0; 3191 3192 /* turn-off interrupts on the card */ 3193 if (ha->interrupts_on) { 3194 vha->flags.init_done = 0; 3195 ha->isp_ops->disable_intrs(ha); 3196 } 3197 3198 qla2x00_free_irqs(vha); 3199 3200 qla2x00_free_fcports(vha); 3201 3202 qla2x00_mem_free(ha); 3203 3204 qla82xx_md_free(vha); 3205 3206 qla2x00_free_queues(ha); 3207} 3208 3209void qla2x00_free_fcports(struct scsi_qla_host *vha) 3210{ 3211 fc_port_t *fcport, *tfcport; 3212 3213 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) { 3214 list_del(&fcport->list); 3215 qla2x00_clear_loop_id(fcport); 3216 kfree(fcport); 3217 fcport = NULL; 3218 } 3219} 3220 3221static inline void 3222qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport, 3223 int defer) 3224{ 3225 struct fc_rport *rport; 3226 scsi_qla_host_t *base_vha; 3227 unsigned long flags; 3228 3229 if (!fcport->rport) 3230 return; 3231 3232 rport = fcport->rport; 3233 if (defer) { 3234 base_vha = pci_get_drvdata(vha->hw->pdev); 3235 spin_lock_irqsave(vha->host->host_lock, flags); 3236 fcport->drport = rport; 3237 spin_unlock_irqrestore(vha->host->host_lock, flags); 3238 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen); 3239 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); 3240 qla2xxx_wake_dpc(base_vha); 3241 } else { 3242 int now; 3243 fc_remote_port_delete(rport); 3244 qlt_do_generation_tick(vha, &now); 3245 qlt_fc_port_deleted(vha, fcport, now); 3246 } 3247} 3248 3249/* 3250 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 3251 * 3252 * Input: ha = adapter block pointer. fcport = port structure pointer. 3253 * 3254 * Return: None. 3255 * 3256 * Context: 3257 */ 3258void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 3259 int do_login, int defer) 3260{ 3261 if (IS_QLAFX00(vha->hw)) { 3262 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3263 qla2x00_schedule_rport_del(vha, fcport, defer); 3264 return; 3265 } 3266 3267 if (atomic_read(&fcport->state) == FCS_ONLINE && 3268 vha->vp_idx == fcport->vha->vp_idx) { 3269 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3270 qla2x00_schedule_rport_del(vha, fcport, defer); 3271 } 3272 /* 3273 * We may need to retry the login, so don't change the state of the 3274 * port but do the retries. 3275 */ 3276 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 3277 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3278 3279 if (!do_login) 3280 return; 3281 3282 if (fcport->login_retry == 0) { 3283 fcport->login_retry = vha->hw->login_retry_count; 3284 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 3285 3286 ql_dbg(ql_dbg_disc, vha, 0x2067, 3287 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n", 3288 fcport->port_name, fcport->loop_id, fcport->login_retry); 3289 } 3290} 3291 3292/* 3293 * qla2x00_mark_all_devices_lost 3294 * Updates fcport state when device goes offline. 3295 * 3296 * Input: 3297 * ha = adapter block pointer. 3298 * fcport = port structure pointer. 3299 * 3300 * Return: 3301 * None. 3302 * 3303 * Context: 3304 */ 3305void 3306qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer) 3307{ 3308 fc_port_t *fcport; 3309 3310 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3311 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx) 3312 continue; 3313 3314 /* 3315 * No point in marking the device as lost, if the device is 3316 * already DEAD. 3317 */ 3318 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD) 3319 continue; 3320 if (atomic_read(&fcport->state) == FCS_ONLINE) { 3321 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3322 if (defer) 3323 qla2x00_schedule_rport_del(vha, fcport, defer); 3324 else if (vha->vp_idx == fcport->vha->vp_idx) 3325 qla2x00_schedule_rport_del(vha, fcport, defer); 3326 } 3327 } 3328} 3329 3330/* 3331* qla2x00_mem_alloc 3332* Allocates adapter memory. 3333* 3334* Returns: 3335* 0 = success. 3336* !0 = failure. 3337*/ 3338static int 3339qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 3340 struct req_que **req, struct rsp_que **rsp) 3341{ 3342 char name[16]; 3343 3344 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 3345 &ha->init_cb_dma, GFP_KERNEL); 3346 if (!ha->init_cb) 3347 goto fail; 3348 3349 if (qlt_mem_alloc(ha) < 0) 3350 goto fail_free_init_cb; 3351 3352 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 3353 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 3354 if (!ha->gid_list) 3355 goto fail_free_tgt_mem; 3356 3357 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 3358 if (!ha->srb_mempool) 3359 goto fail_free_gid_list; 3360 3361 if (IS_P3P_TYPE(ha)) { 3362 /* Allocate cache for CT6 Ctx. */ 3363 if (!ctx_cachep) { 3364 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 3365 sizeof(struct ct6_dsd), 0, 3366 SLAB_HWCACHE_ALIGN, NULL); 3367 if (!ctx_cachep) 3368 goto fail_free_gid_list; 3369 } 3370 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 3371 ctx_cachep); 3372 if (!ha->ctx_mempool) 3373 goto fail_free_srb_mempool; 3374 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 3375 "ctx_cachep=%p ctx_mempool=%p.\n", 3376 ctx_cachep, ha->ctx_mempool); 3377 } 3378 3379 /* Get memory for cached NVRAM */ 3380 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 3381 if (!ha->nvram) 3382 goto fail_free_ctx_mempool; 3383 3384 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 3385 ha->pdev->device); 3386 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3387 DMA_POOL_SIZE, 8, 0); 3388 if (!ha->s_dma_pool) 3389 goto fail_free_nvram; 3390 3391 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 3392 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 3393 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 3394 3395 if (IS_P3P_TYPE(ha) || ql2xenabledif) { 3396 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3397 DSD_LIST_DMA_POOL_SIZE, 8, 0); 3398 if (!ha->dl_dma_pool) { 3399 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 3400 "Failed to allocate memory for dl_dma_pool.\n"); 3401 goto fail_s_dma_pool; 3402 } 3403 3404 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3405 FCP_CMND_DMA_POOL_SIZE, 8, 0); 3406 if (!ha->fcp_cmnd_dma_pool) { 3407 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 3408 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 3409 goto fail_dl_dma_pool; 3410 } 3411 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 3412 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n", 3413 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool); 3414 } 3415 3416 /* Allocate memory for SNS commands */ 3417 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 3418 /* Get consistent memory allocated for SNS commands */ 3419 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 3420 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 3421 if (!ha->sns_cmd) 3422 goto fail_dma_pool; 3423 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 3424 "sns_cmd: %p.\n", ha->sns_cmd); 3425 } else { 3426 /* Get consistent memory allocated for MS IOCB */ 3427 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3428 &ha->ms_iocb_dma); 3429 if (!ha->ms_iocb) 3430 goto fail_dma_pool; 3431 /* Get consistent memory allocated for CT SNS commands */ 3432 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 3433 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 3434 if (!ha->ct_sns) 3435 goto fail_free_ms_iocb; 3436 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 3437 "ms_iocb=%p ct_sns=%p.\n", 3438 ha->ms_iocb, ha->ct_sns); 3439 } 3440 3441 /* Allocate memory for request ring */ 3442 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 3443 if (!*req) { 3444 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 3445 "Failed to allocate memory for req.\n"); 3446 goto fail_req; 3447 } 3448 (*req)->length = req_len; 3449 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 3450 ((*req)->length + 1) * sizeof(request_t), 3451 &(*req)->dma, GFP_KERNEL); 3452 if (!(*req)->ring) { 3453 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 3454 "Failed to allocate memory for req_ring.\n"); 3455 goto fail_req_ring; 3456 } 3457 /* Allocate memory for response ring */ 3458 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 3459 if (!*rsp) { 3460 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 3461 "Failed to allocate memory for rsp.\n"); 3462 goto fail_rsp; 3463 } 3464 (*rsp)->hw = ha; 3465 (*rsp)->length = rsp_len; 3466 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 3467 ((*rsp)->length + 1) * sizeof(response_t), 3468 &(*rsp)->dma, GFP_KERNEL); 3469 if (!(*rsp)->ring) { 3470 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 3471 "Failed to allocate memory for rsp_ring.\n"); 3472 goto fail_rsp_ring; 3473 } 3474 (*req)->rsp = *rsp; 3475 (*rsp)->req = *req; 3476 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 3477 "req=%p req->length=%d req->ring=%p rsp=%p " 3478 "rsp->length=%d rsp->ring=%p.\n", 3479 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 3480 (*rsp)->ring); 3481 /* Allocate memory for NVRAM data for vports */ 3482 if (ha->nvram_npiv_size) { 3483 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) * 3484 ha->nvram_npiv_size, GFP_KERNEL); 3485 if (!ha->npiv_info) { 3486 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 3487 "Failed to allocate memory for npiv_info.\n"); 3488 goto fail_npiv_info; 3489 } 3490 } else 3491 ha->npiv_info = NULL; 3492 3493 /* Get consistent memory allocated for EX-INIT-CB. */ 3494 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 3495 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3496 &ha->ex_init_cb_dma); 3497 if (!ha->ex_init_cb) 3498 goto fail_ex_init_cb; 3499 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 3500 "ex_init_cb=%p.\n", ha->ex_init_cb); 3501 } 3502 3503 INIT_LIST_HEAD(&ha->gbl_dsd_list); 3504 3505 /* Get consistent memory allocated for Async Port-Database. */ 3506 if (!IS_FWI2_CAPABLE(ha)) { 3507 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3508 &ha->async_pd_dma); 3509 if (!ha->async_pd) 3510 goto fail_async_pd; 3511 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 3512 "async_pd=%p.\n", ha->async_pd); 3513 } 3514 3515 INIT_LIST_HEAD(&ha->vp_list); 3516 3517 /* Allocate memory for our loop_id bitmap */ 3518 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long), 3519 GFP_KERNEL); 3520 if (!ha->loop_id_map) 3521 goto fail_async_pd; 3522 else { 3523 qla2x00_set_reserved_loop_ids(ha); 3524 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 3525 "loop_id_map=%p.\n", ha->loop_id_map); 3526 } 3527 3528 return 0; 3529 3530fail_async_pd: 3531 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 3532fail_ex_init_cb: 3533 kfree(ha->npiv_info); 3534fail_npiv_info: 3535 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 3536 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 3537 (*rsp)->ring = NULL; 3538 (*rsp)->dma = 0; 3539fail_rsp_ring: 3540 kfree(*rsp); 3541fail_rsp: 3542 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 3543 sizeof(request_t), (*req)->ring, (*req)->dma); 3544 (*req)->ring = NULL; 3545 (*req)->dma = 0; 3546fail_req_ring: 3547 kfree(*req); 3548fail_req: 3549 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 3550 ha->ct_sns, ha->ct_sns_dma); 3551 ha->ct_sns = NULL; 3552 ha->ct_sns_dma = 0; 3553fail_free_ms_iocb: 3554 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 3555 ha->ms_iocb = NULL; 3556 ha->ms_iocb_dma = 0; 3557fail_dma_pool: 3558 if (IS_QLA82XX(ha) || ql2xenabledif) { 3559 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 3560 ha->fcp_cmnd_dma_pool = NULL; 3561 } 3562fail_dl_dma_pool: 3563 if (IS_QLA82XX(ha) || ql2xenabledif) { 3564 dma_pool_destroy(ha->dl_dma_pool); 3565 ha->dl_dma_pool = NULL; 3566 } 3567fail_s_dma_pool: 3568 dma_pool_destroy(ha->s_dma_pool); 3569 ha->s_dma_pool = NULL; 3570fail_free_nvram: 3571 kfree(ha->nvram); 3572 ha->nvram = NULL; 3573fail_free_ctx_mempool: 3574 mempool_destroy(ha->ctx_mempool); 3575 ha->ctx_mempool = NULL; 3576fail_free_srb_mempool: 3577 mempool_destroy(ha->srb_mempool); 3578 ha->srb_mempool = NULL; 3579fail_free_gid_list: 3580 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 3581 ha->gid_list, 3582 ha->gid_list_dma); 3583 ha->gid_list = NULL; 3584 ha->gid_list_dma = 0; 3585fail_free_tgt_mem: 3586 qlt_mem_free(ha); 3587fail_free_init_cb: 3588 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 3589 ha->init_cb_dma); 3590 ha->init_cb = NULL; 3591 ha->init_cb_dma = 0; 3592fail: 3593 ql_log(ql_log_fatal, NULL, 0x0030, 3594 "Memory allocation failure.\n"); 3595 return -ENOMEM; 3596} 3597 3598/* 3599* qla2x00_free_fw_dump 3600* Frees fw dump stuff. 3601* 3602* Input: 3603* ha = adapter block pointer 3604*/ 3605static void 3606qla2x00_free_fw_dump(struct qla_hw_data *ha) 3607{ 3608 if (ha->fce) 3609 dma_free_coherent(&ha->pdev->dev, 3610 FCE_SIZE, ha->fce, ha->fce_dma); 3611 3612 if (ha->eft) 3613 dma_free_coherent(&ha->pdev->dev, 3614 EFT_SIZE, ha->eft, ha->eft_dma); 3615 3616 if (ha->fw_dump) 3617 vfree(ha->fw_dump); 3618 if (ha->fw_dump_template) 3619 vfree(ha->fw_dump_template); 3620 3621 ha->fce = NULL; 3622 ha->fce_dma = 0; 3623 ha->eft = NULL; 3624 ha->eft_dma = 0; 3625 ha->fw_dumped = 0; 3626 ha->fw_dump_cap_flags = 0; 3627 ha->fw_dump_reading = 0; 3628 ha->fw_dump = NULL; 3629 ha->fw_dump_len = 0; 3630 ha->fw_dump_template = NULL; 3631 ha->fw_dump_template_len = 0; 3632} 3633 3634/* 3635* qla2x00_mem_free 3636* Frees all adapter allocated memory. 3637* 3638* Input: 3639* ha = adapter block pointer. 3640*/ 3641static void 3642qla2x00_mem_free(struct qla_hw_data *ha) 3643{ 3644 qla2x00_free_fw_dump(ha); 3645 3646 if (ha->mctp_dump) 3647 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 3648 ha->mctp_dump_dma); 3649 3650 if (ha->srb_mempool) 3651 mempool_destroy(ha->srb_mempool); 3652 3653 if (ha->dcbx_tlv) 3654 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 3655 ha->dcbx_tlv, ha->dcbx_tlv_dma); 3656 3657 if (ha->xgmac_data) 3658 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 3659 ha->xgmac_data, ha->xgmac_data_dma); 3660 3661 if (ha->sns_cmd) 3662 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 3663 ha->sns_cmd, ha->sns_cmd_dma); 3664 3665 if (ha->ct_sns) 3666 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 3667 ha->ct_sns, ha->ct_sns_dma); 3668 3669 if (ha->sfp_data) 3670 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma); 3671 3672 if (ha->ms_iocb) 3673 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 3674 3675 if (ha->ex_init_cb) 3676 dma_pool_free(ha->s_dma_pool, 3677 ha->ex_init_cb, ha->ex_init_cb_dma); 3678 3679 if (ha->async_pd) 3680 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 3681 3682 if (ha->s_dma_pool) 3683 dma_pool_destroy(ha->s_dma_pool); 3684 3685 if (ha->gid_list) 3686 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 3687 ha->gid_list, ha->gid_list_dma); 3688 3689 if (IS_QLA82XX(ha)) { 3690 if (!list_empty(&ha->gbl_dsd_list)) { 3691 struct dsd_dma *dsd_ptr, *tdsd_ptr; 3692 3693 /* clean up allocated prev pool */ 3694 list_for_each_entry_safe(dsd_ptr, 3695 tdsd_ptr, &ha->gbl_dsd_list, list) { 3696 dma_pool_free(ha->dl_dma_pool, 3697 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 3698 list_del(&dsd_ptr->list); 3699 kfree(dsd_ptr); 3700 } 3701 } 3702 } 3703 3704 if (ha->dl_dma_pool) 3705 dma_pool_destroy(ha->dl_dma_pool); 3706 3707 if (ha->fcp_cmnd_dma_pool) 3708 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 3709 3710 if (ha->ctx_mempool) 3711 mempool_destroy(ha->ctx_mempool); 3712 3713 qlt_mem_free(ha); 3714 3715 if (ha->init_cb) 3716 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 3717 ha->init_cb, ha->init_cb_dma); 3718 vfree(ha->optrom_buffer); 3719 kfree(ha->nvram); 3720 kfree(ha->npiv_info); 3721 kfree(ha->swl); 3722 kfree(ha->loop_id_map); 3723 3724 ha->srb_mempool = NULL; 3725 ha->ctx_mempool = NULL; 3726 ha->sns_cmd = NULL; 3727 ha->sns_cmd_dma = 0; 3728 ha->ct_sns = NULL; 3729 ha->ct_sns_dma = 0; 3730 ha->ms_iocb = NULL; 3731 ha->ms_iocb_dma = 0; 3732 ha->init_cb = NULL; 3733 ha->init_cb_dma = 0; 3734 ha->ex_init_cb = NULL; 3735 ha->ex_init_cb_dma = 0; 3736 ha->async_pd = NULL; 3737 ha->async_pd_dma = 0; 3738 3739 ha->s_dma_pool = NULL; 3740 ha->dl_dma_pool = NULL; 3741 ha->fcp_cmnd_dma_pool = NULL; 3742 3743 ha->gid_list = NULL; 3744 ha->gid_list_dma = 0; 3745 3746 ha->tgt.atio_ring = NULL; 3747 ha->tgt.atio_dma = 0; 3748 ha->tgt.tgt_vp_map = NULL; 3749} 3750 3751struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 3752 struct qla_hw_data *ha) 3753{ 3754 struct Scsi_Host *host; 3755 struct scsi_qla_host *vha = NULL; 3756 3757 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 3758 if (host == NULL) { 3759 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 3760 "Failed to allocate host from the scsi layer, aborting.\n"); 3761 goto fail; 3762 } 3763 3764 /* Clear our data area */ 3765 vha = shost_priv(host); 3766 memset(vha, 0, sizeof(scsi_qla_host_t)); 3767 3768 vha->host = host; 3769 vha->host_no = host->host_no; 3770 vha->hw = ha; 3771 3772 INIT_LIST_HEAD(&vha->vp_fcports); 3773 INIT_LIST_HEAD(&vha->work_list); 3774 INIT_LIST_HEAD(&vha->list); 3775 INIT_LIST_HEAD(&vha->qla_cmd_list); 3776 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list); 3777 3778 spin_lock_init(&vha->work_lock); 3779 spin_lock_init(&vha->cmd_list_lock); 3780 3781 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); 3782 ql_dbg(ql_dbg_init, vha, 0x0041, 3783 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 3784 vha->host, vha->hw, vha, 3785 dev_name(&(ha->pdev->dev))); 3786 3787 return vha; 3788 3789fail: 3790 return vha; 3791} 3792 3793static struct qla_work_evt * 3794qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 3795{ 3796 struct qla_work_evt *e; 3797 uint8_t bail; 3798 3799 QLA_VHA_MARK_BUSY(vha, bail); 3800 if (bail) 3801 return NULL; 3802 3803 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 3804 if (!e) { 3805 QLA_VHA_MARK_NOT_BUSY(vha); 3806 return NULL; 3807 } 3808 3809 INIT_LIST_HEAD(&e->list); 3810 e->type = type; 3811 e->flags = QLA_EVT_FLAG_FREE; 3812 return e; 3813} 3814 3815static int 3816qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 3817{ 3818 unsigned long flags; 3819 3820 spin_lock_irqsave(&vha->work_lock, flags); 3821 list_add_tail(&e->list, &vha->work_list); 3822 spin_unlock_irqrestore(&vha->work_lock, flags); 3823 qla2xxx_wake_dpc(vha); 3824 3825 return QLA_SUCCESS; 3826} 3827 3828int 3829qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 3830 u32 data) 3831{ 3832 struct qla_work_evt *e; 3833 3834 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 3835 if (!e) 3836 return QLA_FUNCTION_FAILED; 3837 3838 e->u.aen.code = code; 3839 e->u.aen.data = data; 3840 return qla2x00_post_work(vha, e); 3841} 3842 3843int 3844qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 3845{ 3846 struct qla_work_evt *e; 3847 3848 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 3849 if (!e) 3850 return QLA_FUNCTION_FAILED; 3851 3852 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 3853 return qla2x00_post_work(vha, e); 3854} 3855 3856#define qla2x00_post_async_work(name, type) \ 3857int qla2x00_post_async_##name##_work( \ 3858 struct scsi_qla_host *vha, \ 3859 fc_port_t *fcport, uint16_t *data) \ 3860{ \ 3861 struct qla_work_evt *e; \ 3862 \ 3863 e = qla2x00_alloc_work(vha, type); \ 3864 if (!e) \ 3865 return QLA_FUNCTION_FAILED; \ 3866 \ 3867 e->u.logio.fcport = fcport; \ 3868 if (data) { \ 3869 e->u.logio.data[0] = data[0]; \ 3870 e->u.logio.data[1] = data[1]; \ 3871 } \ 3872 return qla2x00_post_work(vha, e); \ 3873} 3874 3875qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 3876qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE); 3877qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 3878qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE); 3879qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 3880qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE); 3881 3882int 3883qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 3884{ 3885 struct qla_work_evt *e; 3886 3887 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 3888 if (!e) 3889 return QLA_FUNCTION_FAILED; 3890 3891 e->u.uevent.code = code; 3892 return qla2x00_post_work(vha, e); 3893} 3894 3895static void 3896qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 3897{ 3898 char event_string[40]; 3899 char *envp[] = { event_string, NULL }; 3900 3901 switch (code) { 3902 case QLA_UEVENT_CODE_FW_DUMP: 3903 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", 3904 vha->host_no); 3905 break; 3906 default: 3907 /* do nothing */ 3908 break; 3909 } 3910 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 3911} 3912 3913int 3914qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 3915 uint32_t *data, int cnt) 3916{ 3917 struct qla_work_evt *e; 3918 3919 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 3920 if (!e) 3921 return QLA_FUNCTION_FAILED; 3922 3923 e->u.aenfx.evtcode = evtcode; 3924 e->u.aenfx.count = cnt; 3925 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 3926 return qla2x00_post_work(vha, e); 3927} 3928 3929void 3930qla2x00_do_work(struct scsi_qla_host *vha) 3931{ 3932 struct qla_work_evt *e, *tmp; 3933 unsigned long flags; 3934 LIST_HEAD(work); 3935 3936 spin_lock_irqsave(&vha->work_lock, flags); 3937 list_splice_init(&vha->work_list, &work); 3938 spin_unlock_irqrestore(&vha->work_lock, flags); 3939 3940 list_for_each_entry_safe(e, tmp, &work, list) { 3941 list_del_init(&e->list); 3942 3943 switch (e->type) { 3944 case QLA_EVT_AEN: 3945 fc_host_post_event(vha->host, fc_get_event_number(), 3946 e->u.aen.code, e->u.aen.data); 3947 break; 3948 case QLA_EVT_IDC_ACK: 3949 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 3950 break; 3951 case QLA_EVT_ASYNC_LOGIN: 3952 qla2x00_async_login(vha, e->u.logio.fcport, 3953 e->u.logio.data); 3954 break; 3955 case QLA_EVT_ASYNC_LOGIN_DONE: 3956 qla2x00_async_login_done(vha, e->u.logio.fcport, 3957 e->u.logio.data); 3958 break; 3959 case QLA_EVT_ASYNC_LOGOUT: 3960 qla2x00_async_logout(vha, e->u.logio.fcport); 3961 break; 3962 case QLA_EVT_ASYNC_LOGOUT_DONE: 3963 qla2x00_async_logout_done(vha, e->u.logio.fcport, 3964 e->u.logio.data); 3965 break; 3966 case QLA_EVT_ASYNC_ADISC: 3967 qla2x00_async_adisc(vha, e->u.logio.fcport, 3968 e->u.logio.data); 3969 break; 3970 case QLA_EVT_ASYNC_ADISC_DONE: 3971 qla2x00_async_adisc_done(vha, e->u.logio.fcport, 3972 e->u.logio.data); 3973 break; 3974 case QLA_EVT_UEVENT: 3975 qla2x00_uevent_emit(vha, e->u.uevent.code); 3976 break; 3977 case QLA_EVT_AENFX: 3978 qlafx00_process_aen(vha, e); 3979 break; 3980 } 3981 if (e->flags & QLA_EVT_FLAG_FREE) 3982 kfree(e); 3983 3984 /* For each work completed decrement vha ref count */ 3985 QLA_VHA_MARK_NOT_BUSY(vha); 3986 } 3987} 3988 3989/* Relogins all the fcports of a vport 3990 * Context: dpc thread 3991 */ 3992void qla2x00_relogin(struct scsi_qla_host *vha) 3993{ 3994 fc_port_t *fcport; 3995 int status; 3996 uint16_t next_loopid = 0; 3997 struct qla_hw_data *ha = vha->hw; 3998 uint16_t data[2]; 3999 4000 list_for_each_entry(fcport, &vha->vp_fcports, list) { 4001 /* 4002 * If the port is not ONLINE then try to login 4003 * to it if we haven't run out of retries. 4004 */ 4005 if (atomic_read(&fcport->state) != FCS_ONLINE && 4006 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) { 4007 fcport->login_retry--; 4008 if (fcport->flags & FCF_FABRIC_DEVICE) { 4009 if (fcport->flags & FCF_FCP2_DEVICE) 4010 ha->isp_ops->fabric_logout(vha, 4011 fcport->loop_id, 4012 fcport->d_id.b.domain, 4013 fcport->d_id.b.area, 4014 fcport->d_id.b.al_pa); 4015 4016 if (fcport->loop_id == FC_NO_LOOP_ID) { 4017 fcport->loop_id = next_loopid = 4018 ha->min_external_loopid; 4019 status = qla2x00_find_new_loop_id( 4020 vha, fcport); 4021 if (status != QLA_SUCCESS) { 4022 /* Ran out of IDs to use */ 4023 break; 4024 } 4025 } 4026 4027 if (IS_ALOGIO_CAPABLE(ha)) { 4028 fcport->flags |= FCF_ASYNC_SENT; 4029 data[0] = 0; 4030 data[1] = QLA_LOGIO_LOGIN_RETRIED; 4031 status = qla2x00_post_async_login_work( 4032 vha, fcport, data); 4033 if (status == QLA_SUCCESS) 4034 continue; 4035 /* Attempt a retry. */ 4036 status = 1; 4037 } else { 4038 status = qla2x00_fabric_login(vha, 4039 fcport, &next_loopid); 4040 if (status == QLA_SUCCESS) { 4041 int status2; 4042 uint8_t opts; 4043 4044 opts = 0; 4045 if (fcport->flags & 4046 FCF_FCP2_DEVICE) 4047 opts |= BIT_1; 4048 status2 = 4049 qla2x00_get_port_database( 4050 vha, fcport, opts); 4051 if (status2 != QLA_SUCCESS) 4052 status = 1; 4053 } 4054 } 4055 } else 4056 status = qla2x00_local_device_login(vha, 4057 fcport); 4058 4059 if (status == QLA_SUCCESS) { 4060 fcport->old_loop_id = fcport->loop_id; 4061 4062 ql_dbg(ql_dbg_disc, vha, 0x2003, 4063 "Port login OK: logged in ID 0x%x.\n", 4064 fcport->loop_id); 4065 4066 qla2x00_update_fcport(vha, fcport); 4067 4068 } else if (status == 1) { 4069 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 4070 /* retry the login again */ 4071 ql_dbg(ql_dbg_disc, vha, 0x2007, 4072 "Retrying %d login again loop_id 0x%x.\n", 4073 fcport->login_retry, fcport->loop_id); 4074 } else { 4075 fcport->login_retry = 0; 4076 } 4077 4078 if (fcport->login_retry == 0 && status != QLA_SUCCESS) 4079 qla2x00_clear_loop_id(fcport); 4080 } 4081 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 4082 break; 4083 } 4084} 4085 4086/* Schedule work on any of the dpc-workqueues */ 4087void 4088qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 4089{ 4090 struct qla_hw_data *ha = base_vha->hw; 4091 4092 switch (work_code) { 4093 case MBA_IDC_AEN: /* 0x8200 */ 4094 if (ha->dpc_lp_wq) 4095 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 4096 break; 4097 4098 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 4099 if (!ha->flags.nic_core_reset_hdlr_active) { 4100 if (ha->dpc_hp_wq) 4101 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 4102 } else 4103 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 4104 "NIC Core reset is already active. Skip " 4105 "scheduling it again.\n"); 4106 break; 4107 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 4108 if (ha->dpc_hp_wq) 4109 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 4110 break; 4111 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 4112 if (ha->dpc_hp_wq) 4113 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 4114 break; 4115 default: 4116 ql_log(ql_log_warn, base_vha, 0xb05f, 4117 "Unknown work-code=0x%x.\n", work_code); 4118 } 4119 4120 return; 4121} 4122 4123/* Work: Perform NIC Core Unrecoverable state handling */ 4124void 4125qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 4126{ 4127 struct qla_hw_data *ha = 4128 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 4129 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4130 uint32_t dev_state = 0; 4131 4132 qla83xx_idc_lock(base_vha, 0); 4133 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4134 qla83xx_reset_ownership(base_vha); 4135 if (ha->flags.nic_core_reset_owner) { 4136 ha->flags.nic_core_reset_owner = 0; 4137 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 4138 QLA8XXX_DEV_FAILED); 4139 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 4140 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 4141 } 4142 qla83xx_idc_unlock(base_vha, 0); 4143} 4144 4145/* Work: Execute IDC state handler */ 4146void 4147qla83xx_idc_state_handler_work(struct work_struct *work) 4148{ 4149 struct qla_hw_data *ha = 4150 container_of(work, struct qla_hw_data, idc_state_handler); 4151 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4152 uint32_t dev_state = 0; 4153 4154 qla83xx_idc_lock(base_vha, 0); 4155 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4156 if (dev_state == QLA8XXX_DEV_FAILED || 4157 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 4158 qla83xx_idc_state_handler(base_vha); 4159 qla83xx_idc_unlock(base_vha, 0); 4160} 4161 4162static int 4163qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 4164{ 4165 int rval = QLA_SUCCESS; 4166 unsigned long heart_beat_wait = jiffies + (1 * HZ); 4167 uint32_t heart_beat_counter1, heart_beat_counter2; 4168 4169 do { 4170 if (time_after(jiffies, heart_beat_wait)) { 4171 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 4172 "Nic Core f/w is not alive.\n"); 4173 rval = QLA_FUNCTION_FAILED; 4174 break; 4175 } 4176 4177 qla83xx_idc_lock(base_vha, 0); 4178 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 4179 &heart_beat_counter1); 4180 qla83xx_idc_unlock(base_vha, 0); 4181 msleep(100); 4182 qla83xx_idc_lock(base_vha, 0); 4183 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 4184 &heart_beat_counter2); 4185 qla83xx_idc_unlock(base_vha, 0); 4186 } while (heart_beat_counter1 == heart_beat_counter2); 4187 4188 return rval; 4189} 4190 4191/* Work: Perform NIC Core Reset handling */ 4192void 4193qla83xx_nic_core_reset_work(struct work_struct *work) 4194{ 4195 struct qla_hw_data *ha = 4196 container_of(work, struct qla_hw_data, nic_core_reset); 4197 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4198 uint32_t dev_state = 0; 4199 4200 if (IS_QLA2031(ha)) { 4201 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 4202 ql_log(ql_log_warn, base_vha, 0xb081, 4203 "Failed to dump mctp\n"); 4204 return; 4205 } 4206 4207 if (!ha->flags.nic_core_reset_hdlr_active) { 4208 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 4209 qla83xx_idc_lock(base_vha, 0); 4210 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 4211 &dev_state); 4212 qla83xx_idc_unlock(base_vha, 0); 4213 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 4214 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 4215 "Nic Core f/w is alive.\n"); 4216 return; 4217 } 4218 } 4219 4220 ha->flags.nic_core_reset_hdlr_active = 1; 4221 if (qla83xx_nic_core_reset(base_vha)) { 4222 /* NIC Core reset failed. */ 4223 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 4224 "NIC Core reset failed.\n"); 4225 } 4226 ha->flags.nic_core_reset_hdlr_active = 0; 4227 } 4228} 4229 4230/* Work: Handle 8200 IDC aens */ 4231void 4232qla83xx_service_idc_aen(struct work_struct *work) 4233{ 4234 struct qla_hw_data *ha = 4235 container_of(work, struct qla_hw_data, idc_aen); 4236 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4237 uint32_t dev_state, idc_control; 4238 4239 qla83xx_idc_lock(base_vha, 0); 4240 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4241 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 4242 qla83xx_idc_unlock(base_vha, 0); 4243 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 4244 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 4245 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 4246 "Application requested NIC Core Reset.\n"); 4247 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 4248 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 4249 QLA_SUCCESS) { 4250 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 4251 "Other protocol driver requested NIC Core Reset.\n"); 4252 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 4253 } 4254 } else if (dev_state == QLA8XXX_DEV_FAILED || 4255 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 4256 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 4257 } 4258} 4259 4260static void 4261qla83xx_wait_logic(void) 4262{ 4263 int i; 4264 4265 /* Yield CPU */ 4266 if (!in_interrupt()) { 4267 /* 4268 * Wait about 200ms before retrying again. 4269 * This controls the number of retries for single 4270 * lock operation. 4271 */ 4272 msleep(100); 4273 schedule(); 4274 } else { 4275 for (i = 0; i < 20; i++) 4276 cpu_relax(); /* This a nop instr on i386 */ 4277 } 4278} 4279 4280static int 4281qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 4282{ 4283 int rval; 4284 uint32_t data; 4285 uint32_t idc_lck_rcvry_stage_mask = 0x3; 4286 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 4287 struct qla_hw_data *ha = base_vha->hw; 4288 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 4289 "Trying force recovery of the IDC lock.\n"); 4290 4291 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 4292 if (rval) 4293 return rval; 4294 4295 if ((data & idc_lck_rcvry_stage_mask) > 0) { 4296 return QLA_SUCCESS; 4297 } else { 4298 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 4299 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 4300 data); 4301 if (rval) 4302 return rval; 4303 4304 msleep(200); 4305 4306 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 4307 &data); 4308 if (rval) 4309 return rval; 4310 4311 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 4312 data &= (IDC_LOCK_RECOVERY_STAGE2 | 4313 ~(idc_lck_rcvry_stage_mask)); 4314 rval = qla83xx_wr_reg(base_vha, 4315 QLA83XX_IDC_LOCK_RECOVERY, data); 4316 if (rval) 4317 return rval; 4318 4319 /* Forcefully perform IDC UnLock */ 4320 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 4321 &data); 4322 if (rval) 4323 return rval; 4324 /* Clear lock-id by setting 0xff */ 4325 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 4326 0xff); 4327 if (rval) 4328 return rval; 4329 /* Clear lock-recovery by setting 0x0 */ 4330 rval = qla83xx_wr_reg(base_vha, 4331 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 4332 if (rval) 4333 return rval; 4334 } else 4335 return QLA_SUCCESS; 4336 } 4337 4338 return rval; 4339} 4340 4341static int 4342qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 4343{ 4344 int rval = QLA_SUCCESS; 4345 uint32_t o_drv_lockid, n_drv_lockid; 4346 unsigned long lock_recovery_timeout; 4347 4348 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 4349retry_lockid: 4350 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 4351 if (rval) 4352 goto exit; 4353 4354 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 4355 if (time_after_eq(jiffies, lock_recovery_timeout)) { 4356 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 4357 return QLA_SUCCESS; 4358 else 4359 return QLA_FUNCTION_FAILED; 4360 } 4361 4362 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 4363 if (rval) 4364 goto exit; 4365 4366 if (o_drv_lockid == n_drv_lockid) { 4367 qla83xx_wait_logic(); 4368 goto retry_lockid; 4369 } else 4370 return QLA_SUCCESS; 4371 4372exit: 4373 return rval; 4374} 4375 4376void 4377qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 4378{ 4379 uint16_t options = (requester_id << 15) | BIT_6; 4380 uint32_t data; 4381 uint32_t lock_owner; 4382 struct qla_hw_data *ha = base_vha->hw; 4383 4384 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 4385retry_lock: 4386 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 4387 == QLA_SUCCESS) { 4388 if (data) { 4389 /* Setting lock-id to our function-number */ 4390 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 4391 ha->portnum); 4392 } else { 4393 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 4394 &lock_owner); 4395 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 4396 "Failed to acquire IDC lock, acquired by %d, " 4397 "retrying...\n", lock_owner); 4398 4399 /* Retry/Perform IDC-Lock recovery */ 4400 if (qla83xx_idc_lock_recovery(base_vha) 4401 == QLA_SUCCESS) { 4402 qla83xx_wait_logic(); 4403 goto retry_lock; 4404 } else 4405 ql_log(ql_log_warn, base_vha, 0xb075, 4406 "IDC Lock recovery FAILED.\n"); 4407 } 4408 4409 } 4410 4411 return; 4412 4413 /* XXX: IDC-lock implementation using access-control mbx */ 4414retry_lock2: 4415 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 4416 ql_dbg(ql_dbg_p3p, base_vha, 0xb072, 4417 "Failed to acquire IDC lock. retrying...\n"); 4418 /* Retry/Perform IDC-Lock recovery */ 4419 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) { 4420 qla83xx_wait_logic(); 4421 goto retry_lock2; 4422 } else 4423 ql_log(ql_log_warn, base_vha, 0xb076, 4424 "IDC Lock recovery FAILED.\n"); 4425 } 4426 4427 return; 4428} 4429 4430void 4431qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 4432{ 4433 uint16_t options = (requester_id << 15) | BIT_7, retry; 4434 uint32_t data; 4435 struct qla_hw_data *ha = base_vha->hw; 4436 4437 /* IDC-unlock implementation using driver-unlock/lock-id 4438 * remote registers 4439 */ 4440 retry = 0; 4441retry_unlock: 4442 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 4443 == QLA_SUCCESS) { 4444 if (data == ha->portnum) { 4445 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 4446 /* Clearing lock-id by setting 0xff */ 4447 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 4448 } else if (retry < 10) { 4449 /* SV: XXX: IDC unlock retrying needed here? */ 4450 4451 /* Retry for IDC-unlock */ 4452 qla83xx_wait_logic(); 4453 retry++; 4454 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 4455 "Failed to release IDC lock, retyring=%d\n", retry); 4456 goto retry_unlock; 4457 } 4458 } else if (retry < 10) { 4459 /* Retry for IDC-unlock */ 4460 qla83xx_wait_logic(); 4461 retry++; 4462 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 4463 "Failed to read drv-lockid, retyring=%d\n", retry); 4464 goto retry_unlock; 4465 } 4466 4467 return; 4468 4469 /* XXX: IDC-unlock implementation using access-control mbx */ 4470 retry = 0; 4471retry_unlock2: 4472 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 4473 if (retry < 10) { 4474 /* Retry for IDC-unlock */ 4475 qla83xx_wait_logic(); 4476 retry++; 4477 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 4478 "Failed to release IDC lock, retyring=%d\n", retry); 4479 goto retry_unlock2; 4480 } 4481 } 4482 4483 return; 4484} 4485 4486int 4487__qla83xx_set_drv_presence(scsi_qla_host_t *vha) 4488{ 4489 int rval = QLA_SUCCESS; 4490 struct qla_hw_data *ha = vha->hw; 4491 uint32_t drv_presence; 4492 4493 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 4494 if (rval == QLA_SUCCESS) { 4495 drv_presence |= (1 << ha->portnum); 4496 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 4497 drv_presence); 4498 } 4499 4500 return rval; 4501} 4502 4503int 4504qla83xx_set_drv_presence(scsi_qla_host_t *vha) 4505{ 4506 int rval = QLA_SUCCESS; 4507 4508 qla83xx_idc_lock(vha, 0); 4509 rval = __qla83xx_set_drv_presence(vha); 4510 qla83xx_idc_unlock(vha, 0); 4511 4512 return rval; 4513} 4514 4515int 4516__qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 4517{ 4518 int rval = QLA_SUCCESS; 4519 struct qla_hw_data *ha = vha->hw; 4520 uint32_t drv_presence; 4521 4522 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 4523 if (rval == QLA_SUCCESS) { 4524 drv_presence &= ~(1 << ha->portnum); 4525 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 4526 drv_presence); 4527 } 4528 4529 return rval; 4530} 4531 4532int 4533qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 4534{ 4535 int rval = QLA_SUCCESS; 4536 4537 qla83xx_idc_lock(vha, 0); 4538 rval = __qla83xx_clear_drv_presence(vha); 4539 qla83xx_idc_unlock(vha, 0); 4540 4541 return rval; 4542} 4543 4544static void 4545qla83xx_need_reset_handler(scsi_qla_host_t *vha) 4546{ 4547 struct qla_hw_data *ha = vha->hw; 4548 uint32_t drv_ack, drv_presence; 4549 unsigned long ack_timeout; 4550 4551 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 4552 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 4553 while (1) { 4554 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 4555 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 4556 if ((drv_ack & drv_presence) == drv_presence) 4557 break; 4558 4559 if (time_after_eq(jiffies, ack_timeout)) { 4560 ql_log(ql_log_warn, vha, 0xb067, 4561 "RESET ACK TIMEOUT! drv_presence=0x%x " 4562 "drv_ack=0x%x\n", drv_presence, drv_ack); 4563 /* 4564 * The function(s) which did not ack in time are forced 4565 * to withdraw any further participation in the IDC 4566 * reset. 4567 */ 4568 if (drv_ack != drv_presence) 4569 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 4570 drv_ack); 4571 break; 4572 } 4573 4574 qla83xx_idc_unlock(vha, 0); 4575 msleep(1000); 4576 qla83xx_idc_lock(vha, 0); 4577 } 4578 4579 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 4580 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 4581} 4582 4583static int 4584qla83xx_device_bootstrap(scsi_qla_host_t *vha) 4585{ 4586 int rval = QLA_SUCCESS; 4587 uint32_t idc_control; 4588 4589 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 4590 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 4591 4592 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 4593 __qla83xx_get_idc_control(vha, &idc_control); 4594 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 4595 __qla83xx_set_idc_control(vha, 0); 4596 4597 qla83xx_idc_unlock(vha, 0); 4598 rval = qla83xx_restart_nic_firmware(vha); 4599 qla83xx_idc_lock(vha, 0); 4600 4601 if (rval != QLA_SUCCESS) { 4602 ql_log(ql_log_fatal, vha, 0xb06a, 4603 "Failed to restart NIC f/w.\n"); 4604 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 4605 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 4606 } else { 4607 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 4608 "Success in restarting nic f/w.\n"); 4609 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 4610 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 4611 } 4612 4613 return rval; 4614} 4615 4616/* Assumes idc_lock always held on entry */ 4617int 4618qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 4619{ 4620 struct qla_hw_data *ha = base_vha->hw; 4621 int rval = QLA_SUCCESS; 4622 unsigned long dev_init_timeout; 4623 uint32_t dev_state; 4624 4625 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 4626 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 4627 4628 while (1) { 4629 4630 if (time_after_eq(jiffies, dev_init_timeout)) { 4631 ql_log(ql_log_warn, base_vha, 0xb06e, 4632 "Initialization TIMEOUT!\n"); 4633 /* Init timeout. Disable further NIC Core 4634 * communication. 4635 */ 4636 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 4637 QLA8XXX_DEV_FAILED); 4638 ql_log(ql_log_info, base_vha, 0xb06f, 4639 "HW State: FAILED.\n"); 4640 } 4641 4642 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4643 switch (dev_state) { 4644 case QLA8XXX_DEV_READY: 4645 if (ha->flags.nic_core_reset_owner) 4646 qla83xx_idc_audit(base_vha, 4647 IDC_AUDIT_COMPLETION); 4648 ha->flags.nic_core_reset_owner = 0; 4649 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 4650 "Reset_owner reset by 0x%x.\n", 4651 ha->portnum); 4652 goto exit; 4653 case QLA8XXX_DEV_COLD: 4654 if (ha->flags.nic_core_reset_owner) 4655 rval = qla83xx_device_bootstrap(base_vha); 4656 else { 4657 /* Wait for AEN to change device-state */ 4658 qla83xx_idc_unlock(base_vha, 0); 4659 msleep(1000); 4660 qla83xx_idc_lock(base_vha, 0); 4661 } 4662 break; 4663 case QLA8XXX_DEV_INITIALIZING: 4664 /* Wait for AEN to change device-state */ 4665 qla83xx_idc_unlock(base_vha, 0); 4666 msleep(1000); 4667 qla83xx_idc_lock(base_vha, 0); 4668 break; 4669 case QLA8XXX_DEV_NEED_RESET: 4670 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 4671 qla83xx_need_reset_handler(base_vha); 4672 else { 4673 /* Wait for AEN to change device-state */ 4674 qla83xx_idc_unlock(base_vha, 0); 4675 msleep(1000); 4676 qla83xx_idc_lock(base_vha, 0); 4677 } 4678 /* reset timeout value after need reset handler */ 4679 dev_init_timeout = jiffies + 4680 (ha->fcoe_dev_init_timeout * HZ); 4681 break; 4682 case QLA8XXX_DEV_NEED_QUIESCENT: 4683 /* XXX: DEBUG for now */ 4684 qla83xx_idc_unlock(base_vha, 0); 4685 msleep(1000); 4686 qla83xx_idc_lock(base_vha, 0); 4687 break; 4688 case QLA8XXX_DEV_QUIESCENT: 4689 /* XXX: DEBUG for now */ 4690 if (ha->flags.quiesce_owner) 4691 goto exit; 4692 4693 qla83xx_idc_unlock(base_vha, 0); 4694 msleep(1000); 4695 qla83xx_idc_lock(base_vha, 0); 4696 dev_init_timeout = jiffies + 4697 (ha->fcoe_dev_init_timeout * HZ); 4698 break; 4699 case QLA8XXX_DEV_FAILED: 4700 if (ha->flags.nic_core_reset_owner) 4701 qla83xx_idc_audit(base_vha, 4702 IDC_AUDIT_COMPLETION); 4703 ha->flags.nic_core_reset_owner = 0; 4704 __qla83xx_clear_drv_presence(base_vha); 4705 qla83xx_idc_unlock(base_vha, 0); 4706 qla8xxx_dev_failed_handler(base_vha); 4707 rval = QLA_FUNCTION_FAILED; 4708 qla83xx_idc_lock(base_vha, 0); 4709 goto exit; 4710 case QLA8XXX_BAD_VALUE: 4711 qla83xx_idc_unlock(base_vha, 0); 4712 msleep(1000); 4713 qla83xx_idc_lock(base_vha, 0); 4714 break; 4715 default: 4716 ql_log(ql_log_warn, base_vha, 0xb071, 4717 "Unknown Device State: %x.\n", dev_state); 4718 qla83xx_idc_unlock(base_vha, 0); 4719 qla8xxx_dev_failed_handler(base_vha); 4720 rval = QLA_FUNCTION_FAILED; 4721 qla83xx_idc_lock(base_vha, 0); 4722 goto exit; 4723 } 4724 } 4725 4726exit: 4727 return rval; 4728} 4729 4730void 4731qla2x00_disable_board_on_pci_error(struct work_struct *work) 4732{ 4733 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 4734 board_disable); 4735 struct pci_dev *pdev = ha->pdev; 4736 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4737 4738 ql_log(ql_log_warn, base_vha, 0x015b, 4739 "Disabling adapter.\n"); 4740 4741 set_bit(UNLOADING, &base_vha->dpc_flags); 4742 4743 qla2x00_delete_all_vps(ha, base_vha); 4744 4745 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 4746 4747 qla2x00_dfs_remove(base_vha); 4748 4749 qla84xx_put_chip(base_vha); 4750 4751 if (base_vha->timer_active) 4752 qla2x00_stop_timer(base_vha); 4753 4754 base_vha->flags.online = 0; 4755 4756 qla2x00_destroy_deferred_work(ha); 4757 4758 /* 4759 * Do not try to stop beacon blink as it will issue a mailbox 4760 * command. 4761 */ 4762 qla2x00_free_sysfs_attr(base_vha, false); 4763 4764 fc_remove_host(base_vha->host); 4765 4766 scsi_remove_host(base_vha->host); 4767 4768 base_vha->flags.init_done = 0; 4769 qla25xx_delete_queues(base_vha); 4770 qla2x00_free_irqs(base_vha); 4771 qla2x00_free_fcports(base_vha); 4772 qla2x00_mem_free(ha); 4773 qla82xx_md_free(base_vha); 4774 qla2x00_free_queues(ha); 4775 4776 qla2x00_unmap_iobases(ha); 4777 4778 pci_release_selected_regions(ha->pdev, ha->bars); 4779 pci_disable_pcie_error_reporting(pdev); 4780 pci_disable_device(pdev); 4781 4782 /* 4783 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 4784 */ 4785} 4786 4787/************************************************************************** 4788* qla2x00_do_dpc 4789* This kernel thread is a task that is schedule by the interrupt handler 4790* to perform the background processing for interrupts. 4791* 4792* Notes: 4793* This task always run in the context of a kernel thread. It 4794* is kick-off by the driver's detect code and starts up 4795* up one per adapter. It immediately goes to sleep and waits for 4796* some fibre event. When either the interrupt handler or 4797* the timer routine detects a event it will one of the task 4798* bits then wake us up. 4799**************************************************************************/ 4800static int 4801qla2x00_do_dpc(void *data) 4802{ 4803 int rval; 4804 scsi_qla_host_t *base_vha; 4805 struct qla_hw_data *ha; 4806 4807 ha = (struct qla_hw_data *)data; 4808 base_vha = pci_get_drvdata(ha->pdev); 4809 4810 set_user_nice(current, MIN_NICE); 4811 4812 set_current_state(TASK_INTERRUPTIBLE); 4813 while (!kthread_should_stop()) { 4814 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 4815 "DPC handler sleeping.\n"); 4816 4817 schedule(); 4818 4819 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 4820 goto end_loop; 4821 4822 if (ha->flags.eeh_busy) { 4823 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 4824 "eeh_busy=%d.\n", ha->flags.eeh_busy); 4825 goto end_loop; 4826 } 4827 4828 ha->dpc_active = 1; 4829 4830 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 4831 "DPC handler waking up, dpc_flags=0x%lx.\n", 4832 base_vha->dpc_flags); 4833 4834 qla2x00_do_work(base_vha); 4835 4836 if (IS_P3P_TYPE(ha)) { 4837 if (IS_QLA8044(ha)) { 4838 if (test_and_clear_bit(ISP_UNRECOVERABLE, 4839 &base_vha->dpc_flags)) { 4840 qla8044_idc_lock(ha); 4841 qla8044_wr_direct(base_vha, 4842 QLA8044_CRB_DEV_STATE_INDEX, 4843 QLA8XXX_DEV_FAILED); 4844 qla8044_idc_unlock(ha); 4845 ql_log(ql_log_info, base_vha, 0x4004, 4846 "HW State: FAILED.\n"); 4847 qla8044_device_state_handler(base_vha); 4848 continue; 4849 } 4850 4851 } else { 4852 if (test_and_clear_bit(ISP_UNRECOVERABLE, 4853 &base_vha->dpc_flags)) { 4854 qla82xx_idc_lock(ha); 4855 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 4856 QLA8XXX_DEV_FAILED); 4857 qla82xx_idc_unlock(ha); 4858 ql_log(ql_log_info, base_vha, 0x0151, 4859 "HW State: FAILED.\n"); 4860 qla82xx_device_state_handler(base_vha); 4861 continue; 4862 } 4863 } 4864 4865 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 4866 &base_vha->dpc_flags)) { 4867 4868 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 4869 "FCoE context reset scheduled.\n"); 4870 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 4871 &base_vha->dpc_flags))) { 4872 if (qla82xx_fcoe_ctx_reset(base_vha)) { 4873 /* FCoE-ctx reset failed. 4874 * Escalate to chip-reset 4875 */ 4876 set_bit(ISP_ABORT_NEEDED, 4877 &base_vha->dpc_flags); 4878 } 4879 clear_bit(ABORT_ISP_ACTIVE, 4880 &base_vha->dpc_flags); 4881 } 4882 4883 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 4884 "FCoE context reset end.\n"); 4885 } 4886 } else if (IS_QLAFX00(ha)) { 4887 if (test_and_clear_bit(ISP_UNRECOVERABLE, 4888 &base_vha->dpc_flags)) { 4889 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 4890 "Firmware Reset Recovery\n"); 4891 if (qlafx00_reset_initialize(base_vha)) { 4892 /* Failed. Abort isp later. */ 4893 if (!test_bit(UNLOADING, 4894 &base_vha->dpc_flags)) { 4895 set_bit(ISP_UNRECOVERABLE, 4896 &base_vha->dpc_flags); 4897 ql_dbg(ql_dbg_dpc, base_vha, 4898 0x4021, 4899 "Reset Recovery Failed\n"); 4900 } 4901 } 4902 } 4903 4904 if (test_and_clear_bit(FX00_TARGET_SCAN, 4905 &base_vha->dpc_flags)) { 4906 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 4907 "ISPFx00 Target Scan scheduled\n"); 4908 if (qlafx00_rescan_isp(base_vha)) { 4909 if (!test_bit(UNLOADING, 4910 &base_vha->dpc_flags)) 4911 set_bit(ISP_UNRECOVERABLE, 4912 &base_vha->dpc_flags); 4913 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 4914 "ISPFx00 Target Scan Failed\n"); 4915 } 4916 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 4917 "ISPFx00 Target Scan End\n"); 4918 } 4919 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 4920 &base_vha->dpc_flags)) { 4921 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 4922 "ISPFx00 Host Info resend scheduled\n"); 4923 qlafx00_fx_disc(base_vha, 4924 &base_vha->hw->mr.fcport, 4925 FXDISC_REG_HOST_INFO); 4926 } 4927 } 4928 4929 if (test_and_clear_bit(ISP_ABORT_NEEDED, 4930 &base_vha->dpc_flags)) { 4931 4932 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 4933 "ISP abort scheduled.\n"); 4934 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 4935 &base_vha->dpc_flags))) { 4936 4937 if (ha->isp_ops->abort_isp(base_vha)) { 4938 /* failed. retry later */ 4939 set_bit(ISP_ABORT_NEEDED, 4940 &base_vha->dpc_flags); 4941 } 4942 clear_bit(ABORT_ISP_ACTIVE, 4943 &base_vha->dpc_flags); 4944 } 4945 4946 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 4947 "ISP abort end.\n"); 4948 } 4949 4950 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, 4951 &base_vha->dpc_flags)) { 4952 qla2x00_update_fcports(base_vha); 4953 } 4954 4955 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) { 4956 int ret; 4957 ret = qla2x00_send_change_request(base_vha, 0x3, 0); 4958 if (ret != QLA_SUCCESS) 4959 ql_log(ql_log_warn, base_vha, 0x121, 4960 "Failed to enable receiving of RSCN " 4961 "requests: 0x%x.\n", ret); 4962 clear_bit(SCR_PENDING, &base_vha->dpc_flags); 4963 } 4964 4965 if (IS_QLAFX00(ha)) 4966 goto loop_resync_check; 4967 4968 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 4969 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 4970 "Quiescence mode scheduled.\n"); 4971 if (IS_P3P_TYPE(ha)) { 4972 if (IS_QLA82XX(ha)) 4973 qla82xx_device_state_handler(base_vha); 4974 if (IS_QLA8044(ha)) 4975 qla8044_device_state_handler(base_vha); 4976 clear_bit(ISP_QUIESCE_NEEDED, 4977 &base_vha->dpc_flags); 4978 if (!ha->flags.quiesce_owner) { 4979 qla2x00_perform_loop_resync(base_vha); 4980 if (IS_QLA82XX(ha)) { 4981 qla82xx_idc_lock(ha); 4982 qla82xx_clear_qsnt_ready( 4983 base_vha); 4984 qla82xx_idc_unlock(ha); 4985 } else if (IS_QLA8044(ha)) { 4986 qla8044_idc_lock(ha); 4987 qla8044_clear_qsnt_ready( 4988 base_vha); 4989 qla8044_idc_unlock(ha); 4990 } 4991 } 4992 } else { 4993 clear_bit(ISP_QUIESCE_NEEDED, 4994 &base_vha->dpc_flags); 4995 qla2x00_quiesce_io(base_vha); 4996 } 4997 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 4998 "Quiescence mode end.\n"); 4999 } 5000 5001 if (test_and_clear_bit(RESET_MARKER_NEEDED, 5002 &base_vha->dpc_flags) && 5003 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 5004 5005 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 5006 "Reset marker scheduled.\n"); 5007 qla2x00_rst_aen(base_vha); 5008 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 5009 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 5010 "Reset marker end.\n"); 5011 } 5012 5013 /* Retry each device up to login retry count */ 5014 if ((test_and_clear_bit(RELOGIN_NEEDED, 5015 &base_vha->dpc_flags)) && 5016 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 5017 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 5018 5019 ql_dbg(ql_dbg_dpc, base_vha, 0x400d, 5020 "Relogin scheduled.\n"); 5021 qla2x00_relogin(base_vha); 5022 ql_dbg(ql_dbg_dpc, base_vha, 0x400e, 5023 "Relogin end.\n"); 5024 } 5025loop_resync_check: 5026 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 5027 &base_vha->dpc_flags)) { 5028 5029 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 5030 "Loop resync scheduled.\n"); 5031 5032 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 5033 &base_vha->dpc_flags))) { 5034 5035 rval = qla2x00_loop_resync(base_vha); 5036 5037 clear_bit(LOOP_RESYNC_ACTIVE, 5038 &base_vha->dpc_flags); 5039 } 5040 5041 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 5042 "Loop resync end.\n"); 5043 } 5044 5045 if (IS_QLAFX00(ha)) 5046 goto intr_on_check; 5047 5048 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 5049 atomic_read(&base_vha->loop_state) == LOOP_READY) { 5050 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 5051 qla2xxx_flash_npiv_conf(base_vha); 5052 } 5053 5054intr_on_check: 5055 if (!ha->interrupts_on) 5056 ha->isp_ops->enable_intrs(ha); 5057 5058 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 5059 &base_vha->dpc_flags)) { 5060 if (ha->beacon_blink_led == 1) 5061 ha->isp_ops->beacon_blink(base_vha); 5062 } 5063 5064 if (!IS_QLAFX00(ha)) 5065 qla2x00_do_dpc_all_vps(base_vha); 5066 5067 ha->dpc_active = 0; 5068end_loop: 5069 set_current_state(TASK_INTERRUPTIBLE); 5070 } /* End of while(1) */ 5071 __set_current_state(TASK_RUNNING); 5072 5073 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 5074 "DPC handler exiting.\n"); 5075 5076 /* 5077 * Make sure that nobody tries to wake us up again. 5078 */ 5079 ha->dpc_active = 0; 5080 5081 /* Cleanup any residual CTX SRBs. */ 5082 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 5083 5084 return 0; 5085} 5086 5087void 5088qla2xxx_wake_dpc(struct scsi_qla_host *vha) 5089{ 5090 struct qla_hw_data *ha = vha->hw; 5091 struct task_struct *t = ha->dpc_thread; 5092 5093 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 5094 wake_up_process(t); 5095} 5096 5097/* 5098* qla2x00_rst_aen 5099* Processes asynchronous reset. 5100* 5101* Input: 5102* ha = adapter block pointer. 5103*/ 5104static void 5105qla2x00_rst_aen(scsi_qla_host_t *vha) 5106{ 5107 if (vha->flags.online && !vha->flags.reset_active && 5108 !atomic_read(&vha->loop_down_timer) && 5109 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 5110 do { 5111 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 5112 5113 /* 5114 * Issue marker command only when we are going to start 5115 * the I/O. 5116 */ 5117 vha->marker_needed = 1; 5118 } while (!atomic_read(&vha->loop_down_timer) && 5119 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 5120 } 5121} 5122 5123/************************************************************************** 5124* qla2x00_timer 5125* 5126* Description: 5127* One second timer 5128* 5129* Context: Interrupt 5130***************************************************************************/ 5131void 5132qla2x00_timer(scsi_qla_host_t *vha) 5133{ 5134 unsigned long cpu_flags = 0; 5135 int start_dpc = 0; 5136 int index; 5137 srb_t *sp; 5138 uint16_t w; 5139 struct qla_hw_data *ha = vha->hw; 5140 struct req_que *req; 5141 5142 if (ha->flags.eeh_busy) { 5143 ql_dbg(ql_dbg_timer, vha, 0x6000, 5144 "EEH = %d, restarting timer.\n", 5145 ha->flags.eeh_busy); 5146 qla2x00_restart_timer(vha, WATCH_INTERVAL); 5147 return; 5148 } 5149 5150 /* 5151 * Hardware read to raise pending EEH errors during mailbox waits. If 5152 * the read returns -1 then disable the board. 5153 */ 5154 if (!pci_channel_offline(ha->pdev)) { 5155 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 5156 qla2x00_check_reg16_for_disconnect(vha, w); 5157 } 5158 5159 /* Make sure qla82xx_watchdog is run only for physical port */ 5160 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 5161 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 5162 start_dpc++; 5163 if (IS_QLA82XX(ha)) 5164 qla82xx_watchdog(vha); 5165 else if (IS_QLA8044(ha)) 5166 qla8044_watchdog(vha); 5167 } 5168 5169 if (!vha->vp_idx && IS_QLAFX00(ha)) 5170 qlafx00_timer_routine(vha); 5171 5172 /* Loop down handler. */ 5173 if (atomic_read(&vha->loop_down_timer) > 0 && 5174 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 5175 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 5176 && vha->flags.online) { 5177 5178 if (atomic_read(&vha->loop_down_timer) == 5179 vha->loop_down_abort_time) { 5180 5181 ql_log(ql_log_info, vha, 0x6008, 5182 "Loop down - aborting the queues before time expires.\n"); 5183 5184 if (!IS_QLA2100(ha) && vha->link_down_timeout) 5185 atomic_set(&vha->loop_state, LOOP_DEAD); 5186 5187 /* 5188 * Schedule an ISP abort to return any FCP2-device 5189 * commands. 5190 */ 5191 /* NPIV - scan physical port only */ 5192 if (!vha->vp_idx) { 5193 spin_lock_irqsave(&ha->hardware_lock, 5194 cpu_flags); 5195 req = ha->req_q_map[0]; 5196 for (index = 1; 5197 index < req->num_outstanding_cmds; 5198 index++) { 5199 fc_port_t *sfcp; 5200 5201 sp = req->outstanding_cmds[index]; 5202 if (!sp) 5203 continue; 5204 if (sp->type != SRB_SCSI_CMD) 5205 continue; 5206 sfcp = sp->fcport; 5207 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 5208 continue; 5209 5210 if (IS_QLA82XX(ha)) 5211 set_bit(FCOE_CTX_RESET_NEEDED, 5212 &vha->dpc_flags); 5213 else 5214 set_bit(ISP_ABORT_NEEDED, 5215 &vha->dpc_flags); 5216 break; 5217 } 5218 spin_unlock_irqrestore(&ha->hardware_lock, 5219 cpu_flags); 5220 } 5221 start_dpc++; 5222 } 5223 5224 /* if the loop has been down for 4 minutes, reinit adapter */ 5225 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 5226 if (!(vha->device_flags & DFLG_NO_CABLE)) { 5227 ql_log(ql_log_warn, vha, 0x6009, 5228 "Loop down - aborting ISP.\n"); 5229 5230 if (IS_QLA82XX(ha)) 5231 set_bit(FCOE_CTX_RESET_NEEDED, 5232 &vha->dpc_flags); 5233 else 5234 set_bit(ISP_ABORT_NEEDED, 5235 &vha->dpc_flags); 5236 } 5237 } 5238 ql_dbg(ql_dbg_timer, vha, 0x600a, 5239 "Loop down - seconds remaining %d.\n", 5240 atomic_read(&vha->loop_down_timer)); 5241 } 5242 /* Check if beacon LED needs to be blinked for physical host only */ 5243 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 5244 /* There is no beacon_blink function for ISP82xx */ 5245 if (!IS_P3P_TYPE(ha)) { 5246 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 5247 start_dpc++; 5248 } 5249 } 5250 5251 /* Process any deferred work. */ 5252 if (!list_empty(&vha->work_list)) 5253 start_dpc++; 5254 5255 /* Schedule the DPC routine if needed */ 5256 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 5257 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 5258 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 5259 start_dpc || 5260 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 5261 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 5262 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 5263 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 5264 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 5265 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) { 5266 ql_dbg(ql_dbg_timer, vha, 0x600b, 5267 "isp_abort_needed=%d loop_resync_needed=%d " 5268 "fcport_update_needed=%d start_dpc=%d " 5269 "reset_marker_needed=%d", 5270 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 5271 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 5272 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 5273 start_dpc, 5274 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 5275 ql_dbg(ql_dbg_timer, vha, 0x600c, 5276 "beacon_blink_needed=%d isp_unrecoverable=%d " 5277 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 5278 "relogin_needed=%d.\n", 5279 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 5280 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 5281 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 5282 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 5283 test_bit(RELOGIN_NEEDED, &vha->dpc_flags)); 5284 qla2xxx_wake_dpc(vha); 5285 } 5286 5287 qla2x00_restart_timer(vha, WATCH_INTERVAL); 5288} 5289 5290/* Firmware interface routines. */ 5291 5292#define FW_BLOBS 11 5293#define FW_ISP21XX 0 5294#define FW_ISP22XX 1 5295#define FW_ISP2300 2 5296#define FW_ISP2322 3 5297#define FW_ISP24XX 4 5298#define FW_ISP25XX 5 5299#define FW_ISP81XX 6 5300#define FW_ISP82XX 7 5301#define FW_ISP2031 8 5302#define FW_ISP8031 9 5303#define FW_ISP27XX 10 5304 5305#define FW_FILE_ISP21XX "ql2100_fw.bin" 5306#define FW_FILE_ISP22XX "ql2200_fw.bin" 5307#define FW_FILE_ISP2300 "ql2300_fw.bin" 5308#define FW_FILE_ISP2322 "ql2322_fw.bin" 5309#define FW_FILE_ISP24XX "ql2400_fw.bin" 5310#define FW_FILE_ISP25XX "ql2500_fw.bin" 5311#define FW_FILE_ISP81XX "ql8100_fw.bin" 5312#define FW_FILE_ISP82XX "ql8200_fw.bin" 5313#define FW_FILE_ISP2031 "ql2600_fw.bin" 5314#define FW_FILE_ISP8031 "ql8300_fw.bin" 5315#define FW_FILE_ISP27XX "ql2700_fw.bin" 5316 5317 5318static DEFINE_MUTEX(qla_fw_lock); 5319 5320static struct fw_blob qla_fw_blobs[FW_BLOBS] = { 5321 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 5322 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 5323 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 5324 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 5325 { .name = FW_FILE_ISP24XX, }, 5326 { .name = FW_FILE_ISP25XX, }, 5327 { .name = FW_FILE_ISP81XX, }, 5328 { .name = FW_FILE_ISP82XX, }, 5329 { .name = FW_FILE_ISP2031, }, 5330 { .name = FW_FILE_ISP8031, }, 5331 { .name = FW_FILE_ISP27XX, }, 5332}; 5333 5334struct fw_blob * 5335qla2x00_request_firmware(scsi_qla_host_t *vha) 5336{ 5337 struct qla_hw_data *ha = vha->hw; 5338 struct fw_blob *blob; 5339 5340 if (IS_QLA2100(ha)) { 5341 blob = &qla_fw_blobs[FW_ISP21XX]; 5342 } else if (IS_QLA2200(ha)) { 5343 blob = &qla_fw_blobs[FW_ISP22XX]; 5344 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 5345 blob = &qla_fw_blobs[FW_ISP2300]; 5346 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 5347 blob = &qla_fw_blobs[FW_ISP2322]; 5348 } else if (IS_QLA24XX_TYPE(ha)) { 5349 blob = &qla_fw_blobs[FW_ISP24XX]; 5350 } else if (IS_QLA25XX(ha)) { 5351 blob = &qla_fw_blobs[FW_ISP25XX]; 5352 } else if (IS_QLA81XX(ha)) { 5353 blob = &qla_fw_blobs[FW_ISP81XX]; 5354 } else if (IS_QLA82XX(ha)) { 5355 blob = &qla_fw_blobs[FW_ISP82XX]; 5356 } else if (IS_QLA2031(ha)) { 5357 blob = &qla_fw_blobs[FW_ISP2031]; 5358 } else if (IS_QLA8031(ha)) { 5359 blob = &qla_fw_blobs[FW_ISP8031]; 5360 } else if (IS_QLA27XX(ha)) { 5361 blob = &qla_fw_blobs[FW_ISP27XX]; 5362 } else { 5363 return NULL; 5364 } 5365 5366 mutex_lock(&qla_fw_lock); 5367 if (blob->fw) 5368 goto out; 5369 5370 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 5371 ql_log(ql_log_warn, vha, 0x0063, 5372 "Failed to load firmware image (%s).\n", blob->name); 5373 blob->fw = NULL; 5374 blob = NULL; 5375 goto out; 5376 } 5377 5378out: 5379 mutex_unlock(&qla_fw_lock); 5380 return blob; 5381} 5382 5383static void 5384qla2x00_release_firmware(void) 5385{ 5386 int idx; 5387 5388 mutex_lock(&qla_fw_lock); 5389 for (idx = 0; idx < FW_BLOBS; idx++) 5390 release_firmware(qla_fw_blobs[idx].fw); 5391 mutex_unlock(&qla_fw_lock); 5392} 5393 5394static pci_ers_result_t 5395qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 5396{ 5397 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 5398 struct qla_hw_data *ha = vha->hw; 5399 5400 ql_dbg(ql_dbg_aer, vha, 0x9000, 5401 "PCI error detected, state %x.\n", state); 5402 5403 switch (state) { 5404 case pci_channel_io_normal: 5405 ha->flags.eeh_busy = 0; 5406 return PCI_ERS_RESULT_CAN_RECOVER; 5407 case pci_channel_io_frozen: 5408 ha->flags.eeh_busy = 1; 5409 /* For ISP82XX complete any pending mailbox cmd */ 5410 if (IS_QLA82XX(ha)) { 5411 ha->flags.isp82xx_fw_hung = 1; 5412 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n"); 5413 qla82xx_clear_pending_mbx(vha); 5414 } 5415 qla2x00_free_irqs(vha); 5416 pci_disable_device(pdev); 5417 /* Return back all IOs */ 5418 qla2x00_abort_all_cmds(vha, DID_RESET << 16); 5419 return PCI_ERS_RESULT_NEED_RESET; 5420 case pci_channel_io_perm_failure: 5421 ha->flags.pci_channel_io_perm_failure = 1; 5422 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 5423 return PCI_ERS_RESULT_DISCONNECT; 5424 } 5425 return PCI_ERS_RESULT_NEED_RESET; 5426} 5427 5428static pci_ers_result_t 5429qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 5430{ 5431 int risc_paused = 0; 5432 uint32_t stat; 5433 unsigned long flags; 5434 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 5435 struct qla_hw_data *ha = base_vha->hw; 5436 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 5437 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 5438 5439 if (IS_QLA82XX(ha)) 5440 return PCI_ERS_RESULT_RECOVERED; 5441 5442 spin_lock_irqsave(&ha->hardware_lock, flags); 5443 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 5444 stat = RD_REG_DWORD(®->hccr); 5445 if (stat & HCCR_RISC_PAUSE) 5446 risc_paused = 1; 5447 } else if (IS_QLA23XX(ha)) { 5448 stat = RD_REG_DWORD(®->u.isp2300.host_status); 5449 if (stat & HSR_RISC_PAUSED) 5450 risc_paused = 1; 5451 } else if (IS_FWI2_CAPABLE(ha)) { 5452 stat = RD_REG_DWORD(®24->host_status); 5453 if (stat & HSRX_RISC_PAUSED) 5454 risc_paused = 1; 5455 } 5456 spin_unlock_irqrestore(&ha->hardware_lock, flags); 5457 5458 if (risc_paused) { 5459 ql_log(ql_log_info, base_vha, 0x9003, 5460 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 5461 ha->isp_ops->fw_dump(base_vha, 0); 5462 5463 return PCI_ERS_RESULT_NEED_RESET; 5464 } else 5465 return PCI_ERS_RESULT_RECOVERED; 5466} 5467 5468static uint32_t 5469qla82xx_error_recovery(scsi_qla_host_t *base_vha) 5470{ 5471 uint32_t rval = QLA_FUNCTION_FAILED; 5472 uint32_t drv_active = 0; 5473 struct qla_hw_data *ha = base_vha->hw; 5474 int fn; 5475 struct pci_dev *other_pdev = NULL; 5476 5477 ql_dbg(ql_dbg_aer, base_vha, 0x9006, 5478 "Entered %s.\n", __func__); 5479 5480 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 5481 5482 if (base_vha->flags.online) { 5483 /* Abort all outstanding commands, 5484 * so as to be requeued later */ 5485 qla2x00_abort_isp_cleanup(base_vha); 5486 } 5487 5488 5489 fn = PCI_FUNC(ha->pdev->devfn); 5490 while (fn > 0) { 5491 fn--; 5492 ql_dbg(ql_dbg_aer, base_vha, 0x9007, 5493 "Finding pci device at function = 0x%x.\n", fn); 5494 other_pdev = 5495 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus), 5496 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn), 5497 fn)); 5498 5499 if (!other_pdev) 5500 continue; 5501 if (atomic_read(&other_pdev->enable_cnt)) { 5502 ql_dbg(ql_dbg_aer, base_vha, 0x9008, 5503 "Found PCI func available and enable at 0x%x.\n", 5504 fn); 5505 pci_dev_put(other_pdev); 5506 break; 5507 } 5508 pci_dev_put(other_pdev); 5509 } 5510 5511 if (!fn) { 5512 /* Reset owner */ 5513 ql_dbg(ql_dbg_aer, base_vha, 0x9009, 5514 "This devfn is reset owner = 0x%x.\n", 5515 ha->pdev->devfn); 5516 qla82xx_idc_lock(ha); 5517 5518 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5519 QLA8XXX_DEV_INITIALIZING); 5520 5521 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 5522 QLA82XX_IDC_VERSION); 5523 5524 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 5525 ql_dbg(ql_dbg_aer, base_vha, 0x900a, 5526 "drv_active = 0x%x.\n", drv_active); 5527 5528 qla82xx_idc_unlock(ha); 5529 /* Reset if device is not already reset 5530 * drv_active would be 0 if a reset has already been done 5531 */ 5532 if (drv_active) 5533 rval = qla82xx_start_firmware(base_vha); 5534 else 5535 rval = QLA_SUCCESS; 5536 qla82xx_idc_lock(ha); 5537 5538 if (rval != QLA_SUCCESS) { 5539 ql_log(ql_log_info, base_vha, 0x900b, 5540 "HW State: FAILED.\n"); 5541 qla82xx_clear_drv_active(ha); 5542 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5543 QLA8XXX_DEV_FAILED); 5544 } else { 5545 ql_log(ql_log_info, base_vha, 0x900c, 5546 "HW State: READY.\n"); 5547 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5548 QLA8XXX_DEV_READY); 5549 qla82xx_idc_unlock(ha); 5550 ha->flags.isp82xx_fw_hung = 0; 5551 rval = qla82xx_restart_isp(base_vha); 5552 qla82xx_idc_lock(ha); 5553 /* Clear driver state register */ 5554 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); 5555 qla82xx_set_drv_active(base_vha); 5556 } 5557 qla82xx_idc_unlock(ha); 5558 } else { 5559 ql_dbg(ql_dbg_aer, base_vha, 0x900d, 5560 "This devfn is not reset owner = 0x%x.\n", 5561 ha->pdev->devfn); 5562 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) == 5563 QLA8XXX_DEV_READY)) { 5564 ha->flags.isp82xx_fw_hung = 0; 5565 rval = qla82xx_restart_isp(base_vha); 5566 qla82xx_idc_lock(ha); 5567 qla82xx_set_drv_active(base_vha); 5568 qla82xx_idc_unlock(ha); 5569 } 5570 } 5571 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 5572 5573 return rval; 5574} 5575 5576static pci_ers_result_t 5577qla2xxx_pci_slot_reset(struct pci_dev *pdev) 5578{ 5579 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 5580 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 5581 struct qla_hw_data *ha = base_vha->hw; 5582 struct rsp_que *rsp; 5583 int rc, retries = 10; 5584 5585 ql_dbg(ql_dbg_aer, base_vha, 0x9004, 5586 "Slot Reset.\n"); 5587 5588 /* Workaround: qla2xxx driver which access hardware earlier 5589 * needs error state to be pci_channel_io_online. 5590 * Otherwise mailbox command timesout. 5591 */ 5592 pdev->error_state = pci_channel_io_normal; 5593 5594 pci_restore_state(pdev); 5595 5596 /* pci_restore_state() clears the saved_state flag of the device 5597 * save restored state which resets saved_state flag 5598 */ 5599 pci_save_state(pdev); 5600 5601 if (ha->mem_only) 5602 rc = pci_enable_device_mem(pdev); 5603 else 5604 rc = pci_enable_device(pdev); 5605 5606 if (rc) { 5607 ql_log(ql_log_warn, base_vha, 0x9005, 5608 "Can't re-enable PCI device after reset.\n"); 5609 goto exit_slot_reset; 5610 } 5611 5612 rsp = ha->rsp_q_map[0]; 5613 if (qla2x00_request_irqs(ha, rsp)) 5614 goto exit_slot_reset; 5615 5616 if (ha->isp_ops->pci_config(base_vha)) 5617 goto exit_slot_reset; 5618 5619 if (IS_QLA82XX(ha)) { 5620 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) { 5621 ret = PCI_ERS_RESULT_RECOVERED; 5622 goto exit_slot_reset; 5623 } else 5624 goto exit_slot_reset; 5625 } 5626 5627 while (ha->flags.mbox_busy && retries--) 5628 msleep(1000); 5629 5630 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 5631 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) 5632 ret = PCI_ERS_RESULT_RECOVERED; 5633 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 5634 5635 5636exit_slot_reset: 5637 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 5638 "slot_reset return %x.\n", ret); 5639 5640 return ret; 5641} 5642 5643static void 5644qla2xxx_pci_resume(struct pci_dev *pdev) 5645{ 5646 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 5647 struct qla_hw_data *ha = base_vha->hw; 5648 int ret; 5649 5650 ql_dbg(ql_dbg_aer, base_vha, 0x900f, 5651 "pci_resume.\n"); 5652 5653 ret = qla2x00_wait_for_hba_online(base_vha); 5654 if (ret != QLA_SUCCESS) { 5655 ql_log(ql_log_fatal, base_vha, 0x9002, 5656 "The device failed to resume I/O from slot/link_reset.\n"); 5657 } 5658 5659 pci_cleanup_aer_uncorrect_error_status(pdev); 5660 5661 ha->flags.eeh_busy = 0; 5662} 5663 5664static void 5665qla83xx_disable_laser(scsi_qla_host_t *vha) 5666{ 5667 uint32_t reg, data, fn; 5668 struct qla_hw_data *ha = vha->hw; 5669 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24; 5670 5671 /* pci func #/port # */ 5672 ql_dbg(ql_dbg_init, vha, 0x004b, 5673 "Disabling Laser for hba: %p\n", vha); 5674 5675 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) & 5676 (BIT_15|BIT_14|BIT_13|BIT_12)); 5677 5678 fn = (fn >> 12); 5679 5680 if (fn & 1) 5681 reg = PORT_1_2031; 5682 else 5683 reg = PORT_0_2031; 5684 5685 data = LASER_OFF_2031; 5686 5687 qla83xx_wr_reg(vha, reg, data); 5688} 5689 5690static const struct pci_error_handlers qla2xxx_err_handler = { 5691 .error_detected = qla2xxx_pci_error_detected, 5692 .mmio_enabled = qla2xxx_pci_mmio_enabled, 5693 .slot_reset = qla2xxx_pci_slot_reset, 5694 .resume = qla2xxx_pci_resume, 5695}; 5696 5697static struct pci_device_id qla2xxx_pci_tbl[] = { 5698 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 5699 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 5700 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 5701 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 5702 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 5703 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 5704 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 5705 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 5706 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 5707 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 5708 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 5709 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 5710 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 5711 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 5712 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 5713 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 5714 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 5715 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 5716 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 5717 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 5718 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 5719 { 0 }, 5720}; 5721MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 5722 5723static struct pci_driver qla2xxx_pci_driver = { 5724 .name = QLA2XXX_DRIVER_NAME, 5725 .driver = { 5726 .owner = THIS_MODULE, 5727 }, 5728 .id_table = qla2xxx_pci_tbl, 5729 .probe = qla2x00_probe_one, 5730 .remove = qla2x00_remove_one, 5731 .shutdown = qla2x00_shutdown, 5732 .err_handler = &qla2xxx_err_handler, 5733}; 5734 5735static const struct file_operations apidev_fops = { 5736 .owner = THIS_MODULE, 5737 .llseek = noop_llseek, 5738}; 5739 5740/** 5741 * qla2x00_module_init - Module initialization. 5742 **/ 5743static int __init 5744qla2x00_module_init(void) 5745{ 5746 int ret = 0; 5747 5748 /* Allocate cache for SRBs. */ 5749 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 5750 SLAB_HWCACHE_ALIGN, NULL); 5751 if (srb_cachep == NULL) { 5752 ql_log(ql_log_fatal, NULL, 0x0001, 5753 "Unable to allocate SRB cache...Failing load!.\n"); 5754 return -ENOMEM; 5755 } 5756 5757 /* Initialize target kmem_cache and mem_pools */ 5758 ret = qlt_init(); 5759 if (ret < 0) { 5760 kmem_cache_destroy(srb_cachep); 5761 return ret; 5762 } else if (ret > 0) { 5763 /* 5764 * If initiator mode is explictly disabled by qlt_init(), 5765 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 5766 * performing scsi_scan_target() during LOOP UP event. 5767 */ 5768 qla2xxx_transport_functions.disable_target_scan = 1; 5769 qla2xxx_transport_vport_functions.disable_target_scan = 1; 5770 } 5771 5772 /* Derive version string. */ 5773 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 5774 if (ql2xextended_error_logging) 5775 strcat(qla2x00_version_str, "-debug"); 5776 5777 qla2xxx_transport_template = 5778 fc_attach_transport(&qla2xxx_transport_functions); 5779 if (!qla2xxx_transport_template) { 5780 kmem_cache_destroy(srb_cachep); 5781 ql_log(ql_log_fatal, NULL, 0x0002, 5782 "fc_attach_transport failed...Failing load!.\n"); 5783 qlt_exit(); 5784 return -ENODEV; 5785 } 5786 5787 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 5788 if (apidev_major < 0) { 5789 ql_log(ql_log_fatal, NULL, 0x0003, 5790 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 5791 } 5792 5793 qla2xxx_transport_vport_template = 5794 fc_attach_transport(&qla2xxx_transport_vport_functions); 5795 if (!qla2xxx_transport_vport_template) { 5796 kmem_cache_destroy(srb_cachep); 5797 qlt_exit(); 5798 fc_release_transport(qla2xxx_transport_template); 5799 ql_log(ql_log_fatal, NULL, 0x0004, 5800 "fc_attach_transport vport failed...Failing load!.\n"); 5801 return -ENODEV; 5802 } 5803 ql_log(ql_log_info, NULL, 0x0005, 5804 "QLogic Fibre Channel HBA Driver: %s.\n", 5805 qla2x00_version_str); 5806 ret = pci_register_driver(&qla2xxx_pci_driver); 5807 if (ret) { 5808 kmem_cache_destroy(srb_cachep); 5809 qlt_exit(); 5810 fc_release_transport(qla2xxx_transport_template); 5811 fc_release_transport(qla2xxx_transport_vport_template); 5812 ql_log(ql_log_fatal, NULL, 0x0006, 5813 "pci_register_driver failed...ret=%d Failing load!.\n", 5814 ret); 5815 } 5816 return ret; 5817} 5818 5819/** 5820 * qla2x00_module_exit - Module cleanup. 5821 **/ 5822static void __exit 5823qla2x00_module_exit(void) 5824{ 5825 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 5826 pci_unregister_driver(&qla2xxx_pci_driver); 5827 qla2x00_release_firmware(); 5828 kmem_cache_destroy(srb_cachep); 5829 qlt_exit(); 5830 if (ctx_cachep) 5831 kmem_cache_destroy(ctx_cachep); 5832 fc_release_transport(qla2xxx_transport_template); 5833 fc_release_transport(qla2xxx_transport_vport_template); 5834} 5835 5836module_init(qla2x00_module_init); 5837module_exit(qla2x00_module_exit); 5838 5839MODULE_AUTHOR("QLogic Corporation"); 5840MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 5841MODULE_LICENSE("GPL"); 5842MODULE_VERSION(QLA2XXX_VERSION); 5843MODULE_FIRMWARE(FW_FILE_ISP21XX); 5844MODULE_FIRMWARE(FW_FILE_ISP22XX); 5845MODULE_FIRMWARE(FW_FILE_ISP2300); 5846MODULE_FIRMWARE(FW_FILE_ISP2322); 5847MODULE_FIRMWARE(FW_FILE_ISP24XX); 5848MODULE_FIRMWARE(FW_FILE_ISP25XX); 5849MODULE_FIRMWARE(FW_FILE_ISP2031); 5850MODULE_FIRMWARE(FW_FILE_ISP8031); 5851MODULE_FIRMWARE(FW_FILE_ISP27XX); 5852