1/* 2 * Copyright (c) 2000-2014 LSI Corporation. 3 * 4 * 5 * Name: mpi2.h 6 * Title: MPI Message independent structures and definitions 7 * including System Interface Register Set and 8 * scatter/gather formats. 9 * Creation Date: June 21, 2006 10 * 11 * mpi2.h Version: 02.00.31 12 * 13 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 14 * prefix are for use only on MPI v2.5 products, and must not be used 15 * with MPI v2.0 products. Unless otherwise noted, names beginning with 16 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 17 * 18 * Version History 19 * --------------- 20 * 21 * Date Version Description 22 * -------- -------- ------------------------------------------------------ 23 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 24 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT. 25 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT. 26 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT. 27 * Moved ReplyPostHostIndex register to offset 0x6C of the 28 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for 29 * MPI2_REPLY_POST_HOST_INDEX_OFFSET. 30 * Added union of request descriptors. 31 * Added union of reply descriptors. 32 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT. 33 * Added define for MPI2_VERSION_02_00. 34 * Fixed the size of the FunctionDependent5 field in the 35 * MPI2_DEFAULT_REPLY structure. 36 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT. 37 * Removed the MPI-defined Fault Codes and extended the 38 * product specific codes up to 0xEFFF. 39 * Added a sixth key value for the WriteSequence register 40 * and changed the flush value to 0x0. 41 * Added message function codes for Diagnostic Buffer Post 42 * and Diagnsotic Release. 43 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED 44 * Moved MPI2_VERSION_UNION from mpi2_ioc.h. 45 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT. 46 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT. 47 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT. 48 * Added #defines for marking a reply descriptor as unused. 49 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT. 50 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT. 51 * Moved LUN field defines from mpi2_init.h. 52 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT. 53 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT. 54 * In all request and reply descriptors, replaced VF_ID 55 * field with MSIxIndex field. 56 * Removed DevHandle field from 57 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those 58 * bytes reserved. 59 * Added RAID Accelerator functionality. 60 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT. 61 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT. 62 * Added MSI-x index mask and shift for Reply Post Host 63 * Index register. 64 * Added function code for Host Based Discovery Action. 65 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT. 66 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL. 67 * Added defines for product-specific range of message 68 * function codes, 0xF0 to 0xFF. 69 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT. 70 * Added alternative defines for the SGE Direction bit. 71 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT. 72 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT. 73 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define. 74 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT. 75 * Added MPI2_FUNCTION_SEND_HOST_MESSAGE. 76 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT. 77 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT. 78 * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT. 79 * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT. 80 * Incorporating additions for MPI v2.5. 81 * 02-06-12 02.00.24 Bumped MPI2_HEADER_VERSION_UNIT. 82 * 03-29-12 02.00.25 Bumped MPI2_HEADER_VERSION_UNIT. 83 * Added Hard Reset delay timings. 84 * 07-10-12 02.00.26 Bumped MPI2_HEADER_VERSION_UNIT. 85 * 07-26-12 02.00.27 Bumped MPI2_HEADER_VERSION_UNIT. 86 * 11-27-12 02.00.28 Bumped MPI2_HEADER_VERSION_UNIT. 87 * 12-20-12 02.00.29 Bumped MPI2_HEADER_VERSION_UNIT. 88 * Added MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET. 89 * 04-09-13 02.00.30 Bumped MPI2_HEADER_VERSION_UNIT. 90 * 04-17-13 02.00.31 Bumped MPI2_HEADER_VERSION_UNIT. 91 * -------------------------------------------------------------------------- 92 */ 93 94#ifndef MPI2_H 95#define MPI2_H 96 97/***************************************************************************** 98* 99* MPI Version Definitions 100* 101*****************************************************************************/ 102 103#define MPI2_VERSION_MAJOR_MASK (0xFF00) 104#define MPI2_VERSION_MAJOR_SHIFT (8) 105#define MPI2_VERSION_MINOR_MASK (0x00FF) 106#define MPI2_VERSION_MINOR_SHIFT (0) 107 108/*major version for all MPI v2.x */ 109#define MPI2_VERSION_MAJOR (0x02) 110 111/*minor version for MPI v2.0 compatible products */ 112#define MPI2_VERSION_MINOR (0x00) 113#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 114 MPI2_VERSION_MINOR) 115#define MPI2_VERSION_02_00 (0x0200) 116 117/*minor version for MPI v2.5 compatible products */ 118#define MPI25_VERSION_MINOR (0x05) 119#define MPI25_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 120 MPI25_VERSION_MINOR) 121#define MPI2_VERSION_02_05 (0x0205) 122 123/*Unit and Dev versioning for this MPI header set */ 124#define MPI2_HEADER_VERSION_UNIT (0x1F) 125#define MPI2_HEADER_VERSION_DEV (0x00) 126#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 127#define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 128#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 129#define MPI2_HEADER_VERSION_DEV_SHIFT (0) 130#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \ 131 MPI2_HEADER_VERSION_DEV) 132 133/***************************************************************************** 134* 135* IOC State Definitions 136* 137*****************************************************************************/ 138 139#define MPI2_IOC_STATE_RESET (0x00000000) 140#define MPI2_IOC_STATE_READY (0x10000000) 141#define MPI2_IOC_STATE_OPERATIONAL (0x20000000) 142#define MPI2_IOC_STATE_FAULT (0x40000000) 143 144#define MPI2_IOC_STATE_MASK (0xF0000000) 145#define MPI2_IOC_STATE_SHIFT (28) 146 147/*Fault state range for prodcut specific codes */ 148#define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000) 149#define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF) 150 151/***************************************************************************** 152* 153* System Interface Register Definitions 154* 155*****************************************************************************/ 156 157typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS { 158 U32 Doorbell; /*0x00 */ 159 U32 WriteSequence; /*0x04 */ 160 U32 HostDiagnostic; /*0x08 */ 161 U32 Reserved1; /*0x0C */ 162 U32 DiagRWData; /*0x10 */ 163 U32 DiagRWAddressLow; /*0x14 */ 164 U32 DiagRWAddressHigh; /*0x18 */ 165 U32 Reserved2[5]; /*0x1C */ 166 U32 HostInterruptStatus; /*0x30 */ 167 U32 HostInterruptMask; /*0x34 */ 168 U32 DCRData; /*0x38 */ 169 U32 DCRAddress; /*0x3C */ 170 U32 Reserved3[2]; /*0x40 */ 171 U32 ReplyFreeHostIndex; /*0x48 */ 172 U32 Reserved4[8]; /*0x4C */ 173 U32 ReplyPostHostIndex; /*0x6C */ 174 U32 Reserved5; /*0x70 */ 175 U32 HCBSize; /*0x74 */ 176 U32 HCBAddressLow; /*0x78 */ 177 U32 HCBAddressHigh; /*0x7C */ 178 U32 Reserved6[16]; /*0x80 */ 179 U32 RequestDescriptorPostLow; /*0xC0 */ 180 U32 RequestDescriptorPostHigh; /*0xC4 */ 181 U32 Reserved7[14]; /*0xC8 */ 182} MPI2_SYSTEM_INTERFACE_REGS, 183 *PTR_MPI2_SYSTEM_INTERFACE_REGS, 184 Mpi2SystemInterfaceRegs_t, 185 *pMpi2SystemInterfaceRegs_t; 186 187/* 188 *Defines for working with the Doorbell register. 189 */ 190#define MPI2_DOORBELL_OFFSET (0x00000000) 191 192/*IOC --> System values */ 193#define MPI2_DOORBELL_USED (0x08000000) 194#define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000) 195#define MPI2_DOORBELL_WHO_INIT_SHIFT (24) 196#define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF) 197#define MPI2_DOORBELL_DATA_MASK (0x0000FFFF) 198 199/*System --> IOC values */ 200#define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000) 201#define MPI2_DOORBELL_FUNCTION_SHIFT (24) 202#define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000) 203#define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16) 204 205/* 206 *Defines for the WriteSequence register 207 */ 208#define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 209#define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F) 210#define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 211#define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 212#define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 213#define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 214#define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 215#define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 216#define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 217 218/* 219 *Defines for the HostDiagnostic register 220 */ 221#define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008) 222 223#define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800) 224#define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000) 225#define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800) 226 227#define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400) 228#define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200) 229#define MPI2_DIAG_HCB_MODE (0x00000100) 230#define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080) 231#define MPI2_DIAG_FLASH_BAD_SIG (0x00000040) 232#define MPI2_DIAG_RESET_HISTORY (0x00000020) 233#define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010) 234#define MPI2_DIAG_RESET_ADAPTER (0x00000004) 235#define MPI2_DIAG_HOLD_IOC_RESET (0x00000002) 236 237/* 238 *Offsets for DiagRWData and address 239 */ 240#define MPI2_DIAG_RW_DATA_OFFSET (0x00000010) 241#define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014) 242#define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018) 243 244/* 245 *Defines for the HostInterruptStatus register 246 */ 247#define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030) 248#define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000) 249#define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS 250#define MPI2_HIS_RESET_IRQ_STATUS (0x40000000) 251#define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008) 252#define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001) 253#define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS 254 255/* 256 *Defines for the HostInterruptMask register 257 */ 258#define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034) 259#define MPI2_HIM_RESET_IRQ_MASK (0x40000000) 260#define MPI2_HIM_REPLY_INT_MASK (0x00000008) 261#define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK 262#define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001) 263#define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK 264 265/* 266 *Offsets for DCRData and address 267 */ 268#define MPI2_DCR_DATA_OFFSET (0x00000038) 269#define MPI2_DCR_ADDRESS_OFFSET (0x0000003C) 270 271/* 272 *Offset for the Reply Free Queue 273 */ 274#define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048) 275 276/* 277 *Defines for the Reply Descriptor Post Queue 278 */ 279#define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) 280#define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF) 281#define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000) 282#define MPI2_RPHI_MSIX_INDEX_SHIFT (24) 283#define MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) /*MPI v2.5 only*/ 284 285 286/* 287 *Defines for the HCBSize and address 288 */ 289#define MPI2_HCB_SIZE_OFFSET (0x00000074) 290#define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000) 291#define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001) 292 293#define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078) 294#define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C) 295 296/* 297 *Offsets for the Request Queue 298 */ 299#define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0) 300#define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4) 301 302/*Hard Reset delay timings */ 303#define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000) 304#define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000) 305#define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000) 306 307/***************************************************************************** 308* 309* Message Descriptors 310* 311*****************************************************************************/ 312 313/*Request Descriptors */ 314 315/*Default Request Descriptor */ 316typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR { 317 U8 RequestFlags; /*0x00 */ 318 U8 MSIxIndex; /*0x01 */ 319 U16 SMID; /*0x02 */ 320 U16 LMID; /*0x04 */ 321 U16 DescriptorTypeDependent; /*0x06 */ 322} MPI2_DEFAULT_REQUEST_DESCRIPTOR, 323 *PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, 324 Mpi2DefaultRequestDescriptor_t, 325 *pMpi2DefaultRequestDescriptor_t; 326 327/*defines for the RequestFlags field */ 328#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 329#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 330#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 331#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 332#define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 333#define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 334#define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C) 335 336#define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 337 338/*High Priority Request Descriptor */ 339typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR { 340 U8 RequestFlags; /*0x00 */ 341 U8 MSIxIndex; /*0x01 */ 342 U16 SMID; /*0x02 */ 343 U16 LMID; /*0x04 */ 344 U16 Reserved1; /*0x06 */ 345} MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 346 *PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 347 Mpi2HighPriorityRequestDescriptor_t, 348 *pMpi2HighPriorityRequestDescriptor_t; 349 350/*SCSI IO Request Descriptor */ 351typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR { 352 U8 RequestFlags; /*0x00 */ 353 U8 MSIxIndex; /*0x01 */ 354 U16 SMID; /*0x02 */ 355 U16 LMID; /*0x04 */ 356 U16 DevHandle; /*0x06 */ 357} MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 358 *PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 359 Mpi2SCSIIORequestDescriptor_t, 360 *pMpi2SCSIIORequestDescriptor_t; 361 362/*SCSI Target Request Descriptor */ 363typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR { 364 U8 RequestFlags; /*0x00 */ 365 U8 MSIxIndex; /*0x01 */ 366 U16 SMID; /*0x02 */ 367 U16 LMID; /*0x04 */ 368 U16 IoIndex; /*0x06 */ 369} MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 370 *PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 371 Mpi2SCSITargetRequestDescriptor_t, 372 *pMpi2SCSITargetRequestDescriptor_t; 373 374/*RAID Accelerator Request Descriptor */ 375typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR { 376 U8 RequestFlags; /*0x00 */ 377 U8 MSIxIndex; /*0x01 */ 378 U16 SMID; /*0x02 */ 379 U16 LMID; /*0x04 */ 380 U16 Reserved; /*0x06 */ 381} MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 382 *PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 383 Mpi2RAIDAcceleratorRequestDescriptor_t, 384 *pMpi2RAIDAcceleratorRequestDescriptor_t; 385 386/*Fast Path SCSI IO Request Descriptor */ 387typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR 388 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR, 389 *PTR_MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR, 390 Mpi25FastPathSCSIIORequestDescriptor_t, 391 *pMpi25FastPathSCSIIORequestDescriptor_t; 392 393/*union of Request Descriptors */ 394typedef union _MPI2_REQUEST_DESCRIPTOR_UNION { 395 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 396 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 397 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 398 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 399 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 400 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR FastPathSCSIIO; 401 U64 Words; 402} MPI2_REQUEST_DESCRIPTOR_UNION, 403 *PTR_MPI2_REQUEST_DESCRIPTOR_UNION, 404 Mpi2RequestDescriptorUnion_t, 405 *pMpi2RequestDescriptorUnion_t; 406 407/*Reply Descriptors */ 408 409/*Default Reply Descriptor */ 410typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR { 411 U8 ReplyFlags; /*0x00 */ 412 U8 MSIxIndex; /*0x01 */ 413 U16 DescriptorTypeDependent1; /*0x02 */ 414 U32 DescriptorTypeDependent2; /*0x04 */ 415} MPI2_DEFAULT_REPLY_DESCRIPTOR, 416 *PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR, 417 Mpi2DefaultReplyDescriptor_t, 418 *pMpi2DefaultReplyDescriptor_t; 419 420/*defines for the ReplyFlags field */ 421#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 422#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 423#define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 424#define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 425#define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 426#define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 427#define MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS (0x06) 428#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 429 430/*values for marking a reply descriptor as unused */ 431#define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 432#define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 433 434/*Address Reply Descriptor */ 435typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR { 436 U8 ReplyFlags; /*0x00 */ 437 U8 MSIxIndex; /*0x01 */ 438 U16 SMID; /*0x02 */ 439 U32 ReplyFrameAddress; /*0x04 */ 440} MPI2_ADDRESS_REPLY_DESCRIPTOR, 441 *PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR, 442 Mpi2AddressReplyDescriptor_t, 443 *pMpi2AddressReplyDescriptor_t; 444 445#define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00) 446 447/*SCSI IO Success Reply Descriptor */ 448typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR { 449 U8 ReplyFlags; /*0x00 */ 450 U8 MSIxIndex; /*0x01 */ 451 U16 SMID; /*0x02 */ 452 U16 TaskTag; /*0x04 */ 453 U16 Reserved1; /*0x06 */ 454} MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 455 *PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 456 Mpi2SCSIIOSuccessReplyDescriptor_t, 457 *pMpi2SCSIIOSuccessReplyDescriptor_t; 458 459/*TargetAssist Success Reply Descriptor */ 460typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR { 461 U8 ReplyFlags; /*0x00 */ 462 U8 MSIxIndex; /*0x01 */ 463 U16 SMID; /*0x02 */ 464 U8 SequenceNumber; /*0x04 */ 465 U8 Reserved1; /*0x05 */ 466 U16 IoIndex; /*0x06 */ 467} MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 468 *PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 469 Mpi2TargetAssistSuccessReplyDescriptor_t, 470 *pMpi2TargetAssistSuccessReplyDescriptor_t; 471 472/*Target Command Buffer Reply Descriptor */ 473typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR { 474 U8 ReplyFlags; /*0x00 */ 475 U8 MSIxIndex; /*0x01 */ 476 U8 VP_ID; /*0x02 */ 477 U8 Flags; /*0x03 */ 478 U16 InitiatorDevHandle; /*0x04 */ 479 U16 IoIndex; /*0x06 */ 480} MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 481 *PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 482 Mpi2TargetCommandBufferReplyDescriptor_t, 483 *pMpi2TargetCommandBufferReplyDescriptor_t; 484 485/*defines for Flags field */ 486#define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F) 487 488/*RAID Accelerator Success Reply Descriptor */ 489typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR { 490 U8 ReplyFlags; /*0x00 */ 491 U8 MSIxIndex; /*0x01 */ 492 U16 SMID; /*0x02 */ 493 U32 Reserved; /*0x04 */ 494} MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 495 *PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 496 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, 497 *pMpi2RAIDAcceleratorSuccessReplyDescriptor_t; 498 499/*Fast Path SCSI IO Success Reply Descriptor */ 500typedef MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR 501 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 502 *PTR_MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 503 Mpi25FastPathSCSIIOSuccessReplyDescriptor_t, 504 *pMpi25FastPathSCSIIOSuccessReplyDescriptor_t; 505 506/*union of Reply Descriptors */ 507typedef union _MPI2_REPLY_DESCRIPTORS_UNION { 508 MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 509 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 510 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 511 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 512 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 513 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess; 514 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR FastPathSCSIIOSuccess; 515 U64 Words; 516} MPI2_REPLY_DESCRIPTORS_UNION, 517 *PTR_MPI2_REPLY_DESCRIPTORS_UNION, 518 Mpi2ReplyDescriptorsUnion_t, 519 *pMpi2ReplyDescriptorsUnion_t; 520 521/***************************************************************************** 522* 523* Message Functions 524* 525*****************************************************************************/ 526 527#define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) 528#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) 529#define MPI2_FUNCTION_IOC_INIT (0x02) 530#define MPI2_FUNCTION_IOC_FACTS (0x03) 531#define MPI2_FUNCTION_CONFIG (0x04) 532#define MPI2_FUNCTION_PORT_FACTS (0x05) 533#define MPI2_FUNCTION_PORT_ENABLE (0x06) 534#define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) 535#define MPI2_FUNCTION_EVENT_ACK (0x08) 536#define MPI2_FUNCTION_FW_DOWNLOAD (0x09) 537#define MPI2_FUNCTION_TARGET_ASSIST (0x0B) 538#define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) 539#define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) 540#define MPI2_FUNCTION_FW_UPLOAD (0x12) 541#define MPI2_FUNCTION_RAID_ACTION (0x15) 542#define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) 543#define MPI2_FUNCTION_TOOLBOX (0x17) 544#define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) 545#define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) 546#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) 547#define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) 548#define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) 549#define MPI2_FUNCTION_DIAG_RELEASE (0x1E) 550#define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) 551#define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) 552#define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) 553#define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) 554#define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) 555#define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31) 556#define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) 557#define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) 558 559/*Doorbell functions */ 560#define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 561#define MPI2_FUNCTION_HANDSHAKE (0x42) 562 563/***************************************************************************** 564* 565* IOC Status Values 566* 567*****************************************************************************/ 568 569/*mask for IOCStatus status value */ 570#define MPI2_IOCSTATUS_MASK (0x7FFF) 571 572/**************************************************************************** 573* Common IOCStatus values for all replies 574****************************************************************************/ 575 576#define MPI2_IOCSTATUS_SUCCESS (0x0000) 577#define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001) 578#define MPI2_IOCSTATUS_BUSY (0x0002) 579#define MPI2_IOCSTATUS_INVALID_SGL (0x0003) 580#define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004) 581#define MPI2_IOCSTATUS_INVALID_VPID (0x0005) 582#define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) 583#define MPI2_IOCSTATUS_INVALID_FIELD (0x0007) 584#define MPI2_IOCSTATUS_INVALID_STATE (0x0008) 585#define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009) 586 587/**************************************************************************** 588* Config IOCStatus values 589****************************************************************************/ 590 591#define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) 592#define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) 593#define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) 594#define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) 595#define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) 596#define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) 597 598/**************************************************************************** 599* SCSI IO Reply 600****************************************************************************/ 601 602#define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) 603#define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042) 604#define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) 605#define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) 606#define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) 607#define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) 608#define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) 609#define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) 610#define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) 611#define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A) 612#define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B) 613#define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C) 614 615/**************************************************************************** 616* For use by SCSI Initiator and SCSI Target end-to-end data protection 617****************************************************************************/ 618 619#define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D) 620#define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E) 621#define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F) 622 623/**************************************************************************** 624* SCSI Target values 625****************************************************************************/ 626 627#define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062) 628#define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063) 629#define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) 630#define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) 631#define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A) 632#define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D) 633#define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E) 634#define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F) 635#define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070) 636#define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071) 637 638/**************************************************************************** 639* Serial Attached SCSI values 640****************************************************************************/ 641 642#define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090) 643#define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091) 644 645/**************************************************************************** 646* Diagnostic Buffer Post / Diagnostic Release values 647****************************************************************************/ 648 649#define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0) 650 651/**************************************************************************** 652* RAID Accelerator values 653****************************************************************************/ 654 655#define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0) 656 657/**************************************************************************** 658* IOCStatus flag to indicate that log info is available 659****************************************************************************/ 660 661#define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000) 662 663/**************************************************************************** 664* IOCLogInfo Types 665****************************************************************************/ 666 667#define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000) 668#define MPI2_IOCLOGINFO_TYPE_SHIFT (28) 669#define MPI2_IOCLOGINFO_TYPE_NONE (0x0) 670#define MPI2_IOCLOGINFO_TYPE_SCSI (0x1) 671#define MPI2_IOCLOGINFO_TYPE_FC (0x2) 672#define MPI2_IOCLOGINFO_TYPE_SAS (0x3) 673#define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4) 674#define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF) 675 676/***************************************************************************** 677* 678* Standard Message Structures 679* 680*****************************************************************************/ 681 682/**************************************************************************** 683*Request Message Header for all request messages 684****************************************************************************/ 685 686typedef struct _MPI2_REQUEST_HEADER { 687 U16 FunctionDependent1; /*0x00 */ 688 U8 ChainOffset; /*0x02 */ 689 U8 Function; /*0x03 */ 690 U16 FunctionDependent2; /*0x04 */ 691 U8 FunctionDependent3; /*0x06 */ 692 U8 MsgFlags; /*0x07 */ 693 U8 VP_ID; /*0x08 */ 694 U8 VF_ID; /*0x09 */ 695 U16 Reserved1; /*0x0A */ 696} MPI2_REQUEST_HEADER, *PTR_MPI2_REQUEST_HEADER, 697 MPI2RequestHeader_t, *pMPI2RequestHeader_t; 698 699/**************************************************************************** 700* Default Reply 701****************************************************************************/ 702 703typedef struct _MPI2_DEFAULT_REPLY { 704 U16 FunctionDependent1; /*0x00 */ 705 U8 MsgLength; /*0x02 */ 706 U8 Function; /*0x03 */ 707 U16 FunctionDependent2; /*0x04 */ 708 U8 FunctionDependent3; /*0x06 */ 709 U8 MsgFlags; /*0x07 */ 710 U8 VP_ID; /*0x08 */ 711 U8 VF_ID; /*0x09 */ 712 U16 Reserved1; /*0x0A */ 713 U16 FunctionDependent5; /*0x0C */ 714 U16 IOCStatus; /*0x0E */ 715 U32 IOCLogInfo; /*0x10 */ 716} MPI2_DEFAULT_REPLY, *PTR_MPI2_DEFAULT_REPLY, 717 MPI2DefaultReply_t, *pMPI2DefaultReply_t; 718 719/*common version structure/union used in messages and configuration pages */ 720 721typedef struct _MPI2_VERSION_STRUCT { 722 U8 Dev; /*0x00 */ 723 U8 Unit; /*0x01 */ 724 U8 Minor; /*0x02 */ 725 U8 Major; /*0x03 */ 726} MPI2_VERSION_STRUCT; 727 728typedef union _MPI2_VERSION_UNION { 729 MPI2_VERSION_STRUCT Struct; 730 U32 Word; 731} MPI2_VERSION_UNION; 732 733/*LUN field defines, common to many structures */ 734#define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF) 735#define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000) 736#define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF) 737#define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000) 738#define MPI2_LUN_LEVEL_1_WORD (0xFF00) 739#define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00) 740 741/***************************************************************************** 742* 743* Fusion-MPT MPI Scatter Gather Elements 744* 745*****************************************************************************/ 746 747/**************************************************************************** 748* MPI Simple Element structures 749****************************************************************************/ 750 751typedef struct _MPI2_SGE_SIMPLE32 { 752 U32 FlagsLength; 753 U32 Address; 754} MPI2_SGE_SIMPLE32, *PTR_MPI2_SGE_SIMPLE32, 755 Mpi2SGESimple32_t, *pMpi2SGESimple32_t; 756 757typedef struct _MPI2_SGE_SIMPLE64 { 758 U32 FlagsLength; 759 U64 Address; 760} MPI2_SGE_SIMPLE64, *PTR_MPI2_SGE_SIMPLE64, 761 Mpi2SGESimple64_t, *pMpi2SGESimple64_t; 762 763typedef struct _MPI2_SGE_SIMPLE_UNION { 764 U32 FlagsLength; 765 union { 766 U32 Address32; 767 U64 Address64; 768 } u; 769} MPI2_SGE_SIMPLE_UNION, 770 *PTR_MPI2_SGE_SIMPLE_UNION, 771 Mpi2SGESimpleUnion_t, 772 *pMpi2SGESimpleUnion_t; 773 774/**************************************************************************** 775* MPI Chain Element structures - for MPI v2.0 products only 776****************************************************************************/ 777 778typedef struct _MPI2_SGE_CHAIN32 { 779 U16 Length; 780 U8 NextChainOffset; 781 U8 Flags; 782 U32 Address; 783} MPI2_SGE_CHAIN32, *PTR_MPI2_SGE_CHAIN32, 784 Mpi2SGEChain32_t, *pMpi2SGEChain32_t; 785 786typedef struct _MPI2_SGE_CHAIN64 { 787 U16 Length; 788 U8 NextChainOffset; 789 U8 Flags; 790 U64 Address; 791} MPI2_SGE_CHAIN64, *PTR_MPI2_SGE_CHAIN64, 792 Mpi2SGEChain64_t, *pMpi2SGEChain64_t; 793 794typedef struct _MPI2_SGE_CHAIN_UNION { 795 U16 Length; 796 U8 NextChainOffset; 797 U8 Flags; 798 union { 799 U32 Address32; 800 U64 Address64; 801 } u; 802} MPI2_SGE_CHAIN_UNION, 803 *PTR_MPI2_SGE_CHAIN_UNION, 804 Mpi2SGEChainUnion_t, 805 *pMpi2SGEChainUnion_t; 806 807/**************************************************************************** 808* MPI Transaction Context Element structures - for MPI v2.0 products only 809****************************************************************************/ 810 811typedef struct _MPI2_SGE_TRANSACTION32 { 812 U8 Reserved; 813 U8 ContextSize; 814 U8 DetailsLength; 815 U8 Flags; 816 U32 TransactionContext[1]; 817 U32 TransactionDetails[1]; 818} MPI2_SGE_TRANSACTION32, 819 *PTR_MPI2_SGE_TRANSACTION32, 820 Mpi2SGETransaction32_t, 821 *pMpi2SGETransaction32_t; 822 823typedef struct _MPI2_SGE_TRANSACTION64 { 824 U8 Reserved; 825 U8 ContextSize; 826 U8 DetailsLength; 827 U8 Flags; 828 U32 TransactionContext[2]; 829 U32 TransactionDetails[1]; 830} MPI2_SGE_TRANSACTION64, 831 *PTR_MPI2_SGE_TRANSACTION64, 832 Mpi2SGETransaction64_t, 833 *pMpi2SGETransaction64_t; 834 835typedef struct _MPI2_SGE_TRANSACTION96 { 836 U8 Reserved; 837 U8 ContextSize; 838 U8 DetailsLength; 839 U8 Flags; 840 U32 TransactionContext[3]; 841 U32 TransactionDetails[1]; 842} MPI2_SGE_TRANSACTION96, *PTR_MPI2_SGE_TRANSACTION96, 843 Mpi2SGETransaction96_t, *pMpi2SGETransaction96_t; 844 845typedef struct _MPI2_SGE_TRANSACTION128 { 846 U8 Reserved; 847 U8 ContextSize; 848 U8 DetailsLength; 849 U8 Flags; 850 U32 TransactionContext[4]; 851 U32 TransactionDetails[1]; 852} MPI2_SGE_TRANSACTION128, *PTR_MPI2_SGE_TRANSACTION128, 853 Mpi2SGETransaction_t128, *pMpi2SGETransaction_t128; 854 855typedef struct _MPI2_SGE_TRANSACTION_UNION { 856 U8 Reserved; 857 U8 ContextSize; 858 U8 DetailsLength; 859 U8 Flags; 860 union { 861 U32 TransactionContext32[1]; 862 U32 TransactionContext64[2]; 863 U32 TransactionContext96[3]; 864 U32 TransactionContext128[4]; 865 } u; 866 U32 TransactionDetails[1]; 867} MPI2_SGE_TRANSACTION_UNION, 868 *PTR_MPI2_SGE_TRANSACTION_UNION, 869 Mpi2SGETransactionUnion_t, 870 *pMpi2SGETransactionUnion_t; 871 872/**************************************************************************** 873* MPI SGE union for IO SGL's - for MPI v2.0 products only 874****************************************************************************/ 875 876typedef struct _MPI2_MPI_SGE_IO_UNION { 877 union { 878 MPI2_SGE_SIMPLE_UNION Simple; 879 MPI2_SGE_CHAIN_UNION Chain; 880 } u; 881} MPI2_MPI_SGE_IO_UNION, *PTR_MPI2_MPI_SGE_IO_UNION, 882 Mpi2MpiSGEIOUnion_t, *pMpi2MpiSGEIOUnion_t; 883 884/**************************************************************************** 885* MPI SGE union for SGL's with Simple and Transaction elements - for MPI v2.0 products only 886****************************************************************************/ 887 888typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION { 889 union { 890 MPI2_SGE_SIMPLE_UNION Simple; 891 MPI2_SGE_TRANSACTION_UNION Transaction; 892 } u; 893} MPI2_SGE_TRANS_SIMPLE_UNION, 894 *PTR_MPI2_SGE_TRANS_SIMPLE_UNION, 895 Mpi2SGETransSimpleUnion_t, 896 *pMpi2SGETransSimpleUnion_t; 897 898/**************************************************************************** 899* All MPI SGE types union 900****************************************************************************/ 901 902typedef struct _MPI2_MPI_SGE_UNION { 903 union { 904 MPI2_SGE_SIMPLE_UNION Simple; 905 MPI2_SGE_CHAIN_UNION Chain; 906 MPI2_SGE_TRANSACTION_UNION Transaction; 907 } u; 908} MPI2_MPI_SGE_UNION, *PTR_MPI2_MPI_SGE_UNION, 909 Mpi2MpiSgeUnion_t, *pMpi2MpiSgeUnion_t; 910 911/**************************************************************************** 912* MPI SGE field definition and masks 913****************************************************************************/ 914 915/*Flags field bit definitions */ 916 917#define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80) 918#define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40) 919#define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30) 920#define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08) 921#define MPI2_SGE_FLAGS_DIRECTION (0x04) 922#define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02) 923#define MPI2_SGE_FLAGS_END_OF_LIST (0x01) 924 925#define MPI2_SGE_FLAGS_SHIFT (24) 926 927#define MPI2_SGE_LENGTH_MASK (0x00FFFFFF) 928#define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF) 929 930/*Element Type */ 931 932#define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00) 933#define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10) 934#define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30) 935#define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30) 936 937/*Address location */ 938 939#define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00) 940 941/*Direction */ 942 943#define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00) 944#define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04) 945 946#define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST) 947#define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC) 948 949/*Address Size */ 950 951#define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 952#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 953 954/*Context Size */ 955 956#define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00) 957#define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02) 958#define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04) 959#define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06) 960 961#define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000) 962#define MPI2_SGE_CHAIN_OFFSET_SHIFT (16) 963 964/**************************************************************************** 965* MPI SGE operation Macros 966****************************************************************************/ 967 968/*SIMPLE FlagsLength manipulations... */ 969#define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT) 970#define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> \ 971 MPI2_SGE_FLAGS_SHIFT) 972#define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK) 973#define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK) 974 975#define MPI2_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_SGE_SET_FLAGS(f) | \ 976 MPI2_SGE_LENGTH(l)) 977 978#define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength) 979#define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength) 980#define MPI2_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \ 981 MPI2_SGE_SET_FLAGS_LENGTH(f, l)) 982 983/*CAUTION - The following are READ-MODIFY-WRITE! */ 984#define MPI2_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \ 985 MPI2_SGE_SET_FLAGS(f)) 986#define MPI2_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \ 987 MPI2_SGE_LENGTH(l)) 988 989#define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> \ 990 MPI2_SGE_CHAIN_OFFSET_SHIFT) 991 992/***************************************************************************** 993* 994* Fusion-MPT IEEE Scatter Gather Elements 995* 996*****************************************************************************/ 997 998/**************************************************************************** 999* IEEE Simple Element structures 1000****************************************************************************/ 1001 1002/*MPI2_IEEE_SGE_SIMPLE32 is for MPI v2.0 products only */ 1003typedef struct _MPI2_IEEE_SGE_SIMPLE32 { 1004 U32 Address; 1005 U32 FlagsLength; 1006} MPI2_IEEE_SGE_SIMPLE32, *PTR_MPI2_IEEE_SGE_SIMPLE32, 1007 Mpi2IeeeSgeSimple32_t, *pMpi2IeeeSgeSimple32_t; 1008 1009typedef struct _MPI2_IEEE_SGE_SIMPLE64 { 1010 U64 Address; 1011 U32 Length; 1012 U16 Reserved1; 1013 U8 Reserved2; 1014 U8 Flags; 1015} MPI2_IEEE_SGE_SIMPLE64, *PTR_MPI2_IEEE_SGE_SIMPLE64, 1016 Mpi2IeeeSgeSimple64_t, *pMpi2IeeeSgeSimple64_t; 1017 1018typedef union _MPI2_IEEE_SGE_SIMPLE_UNION { 1019 MPI2_IEEE_SGE_SIMPLE32 Simple32; 1020 MPI2_IEEE_SGE_SIMPLE64 Simple64; 1021} MPI2_IEEE_SGE_SIMPLE_UNION, 1022 *PTR_MPI2_IEEE_SGE_SIMPLE_UNION, 1023 Mpi2IeeeSgeSimpleUnion_t, 1024 *pMpi2IeeeSgeSimpleUnion_t; 1025 1026/**************************************************************************** 1027* IEEE Chain Element structures 1028****************************************************************************/ 1029 1030/*MPI2_IEEE_SGE_CHAIN32 is for MPI v2.0 products only */ 1031typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32; 1032 1033/*MPI2_IEEE_SGE_CHAIN64 is for MPI v2.0 products only */ 1034typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64; 1035 1036typedef union _MPI2_IEEE_SGE_CHAIN_UNION { 1037 MPI2_IEEE_SGE_CHAIN32 Chain32; 1038 MPI2_IEEE_SGE_CHAIN64 Chain64; 1039} MPI2_IEEE_SGE_CHAIN_UNION, 1040 *PTR_MPI2_IEEE_SGE_CHAIN_UNION, 1041 Mpi2IeeeSgeChainUnion_t, 1042 *pMpi2IeeeSgeChainUnion_t; 1043 1044/*MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 products only */ 1045typedef struct _MPI25_IEEE_SGE_CHAIN64 { 1046 U64 Address; 1047 U32 Length; 1048 U16 Reserved1; 1049 U8 NextChainOffset; 1050 U8 Flags; 1051} MPI25_IEEE_SGE_CHAIN64, 1052 *PTR_MPI25_IEEE_SGE_CHAIN64, 1053 Mpi25IeeeSgeChain64_t, 1054 *pMpi25IeeeSgeChain64_t; 1055 1056/**************************************************************************** 1057* All IEEE SGE types union 1058****************************************************************************/ 1059 1060/*MPI2_IEEE_SGE_UNION is for MPI v2.0 products only */ 1061typedef struct _MPI2_IEEE_SGE_UNION { 1062 union { 1063 MPI2_IEEE_SGE_SIMPLE_UNION Simple; 1064 MPI2_IEEE_SGE_CHAIN_UNION Chain; 1065 } u; 1066} MPI2_IEEE_SGE_UNION, *PTR_MPI2_IEEE_SGE_UNION, 1067 Mpi2IeeeSgeUnion_t, *pMpi2IeeeSgeUnion_t; 1068 1069/**************************************************************************** 1070* IEEE SGE union for IO SGL's 1071****************************************************************************/ 1072 1073typedef union _MPI25_SGE_IO_UNION { 1074 MPI2_IEEE_SGE_SIMPLE64 IeeeSimple; 1075 MPI25_IEEE_SGE_CHAIN64 IeeeChain; 1076} MPI25_SGE_IO_UNION, *PTR_MPI25_SGE_IO_UNION, 1077 Mpi25SGEIOUnion_t, *pMpi25SGEIOUnion_t; 1078 1079/**************************************************************************** 1080* IEEE SGE field definitions and masks 1081****************************************************************************/ 1082 1083/*Flags field bit definitions */ 1084 1085#define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1086#define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1087 1088#define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1089 1090#define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1091 1092/*Element Type */ 1093 1094#define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1095#define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1096 1097/*Data Location Address Space */ 1098 1099#define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1100#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 1101#define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 1102#define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1103#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 1104#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03) 1105#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR \ 1106 (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR) 1107 1108/**************************************************************************** 1109* IEEE SGE operation Macros 1110****************************************************************************/ 1111 1112/*SIMPLE FlagsLength manipulations... */ 1113#define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT) 1114#define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) \ 1115 >> MPI2_IEEE32_SGE_FLAGS_SHIFT) 1116#define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK) 1117 1118#define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) |\ 1119 MPI2_IEEE32_SGE_LENGTH(l)) 1120 1121#define MPI2_IEEE32_pSGE_GET_FLAGS(psg) \ 1122 MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength) 1123#define MPI2_IEEE32_pSGE_GET_LENGTH(psg) \ 1124 MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength) 1125#define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \ 1126 MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l)) 1127 1128/*CAUTION - The following are READ-MODIFY-WRITE! */ 1129#define MPI2_IEEE32_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \ 1130 MPI2_IEEE32_SGE_SET_FLAGS(f)) 1131#define MPI2_IEEE32_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \ 1132 MPI2_IEEE32_SGE_LENGTH(l)) 1133 1134/***************************************************************************** 1135* 1136* Fusion-MPT MPI/IEEE Scatter Gather Unions 1137* 1138*****************************************************************************/ 1139 1140typedef union _MPI2_SIMPLE_SGE_UNION { 1141 MPI2_SGE_SIMPLE_UNION MpiSimple; 1142 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1143} MPI2_SIMPLE_SGE_UNION, *PTR_MPI2_SIMPLE_SGE_UNION, 1144 Mpi2SimpleSgeUntion_t, *pMpi2SimpleSgeUntion_t; 1145 1146typedef union _MPI2_SGE_IO_UNION { 1147 MPI2_SGE_SIMPLE_UNION MpiSimple; 1148 MPI2_SGE_CHAIN_UNION MpiChain; 1149 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1150 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 1151} MPI2_SGE_IO_UNION, *PTR_MPI2_SGE_IO_UNION, 1152 Mpi2SGEIOUnion_t, *pMpi2SGEIOUnion_t; 1153 1154/**************************************************************************** 1155* 1156* Values for SGLFlags field, used in many request messages with an SGL 1157* 1158****************************************************************************/ 1159 1160/*values for MPI SGL Data Location Address Space subfield */ 1161#define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C) 1162#define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00) 1163#define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04) 1164#define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) 1165#define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C) 1166/*values for SGL Type subfield */ 1167#define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03) 1168#define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00) 1169#define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01) 1170#define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02) 1171 1172#endif 1173