1/* 2 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc. 3 * All rights reserved 4 * www.brocade.com 5 * 6 * Linux driver for Brocade Fibre Channel Host Bus Adapter. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License (GPL) Version 2 as 10 * published by the Free Software Foundation 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 */ 17 18/* 19 * bfi_reg.h ASIC register defines for all Brocade adapter ASICs 20 */ 21 22#ifndef __BFI_REG_H__ 23#define __BFI_REG_H__ 24 25#define HOSTFN0_INT_STATUS 0x00014000 /* cb/ct */ 26#define HOSTFN1_INT_STATUS 0x00014100 /* cb/ct */ 27#define HOSTFN2_INT_STATUS 0x00014300 /* ct */ 28#define HOSTFN3_INT_STATUS 0x00014400 /* ct */ 29#define HOSTFN0_INT_MSK 0x00014004 /* cb/ct */ 30#define HOSTFN1_INT_MSK 0x00014104 /* cb/ct */ 31#define HOSTFN2_INT_MSK 0x00014304 /* ct */ 32#define HOSTFN3_INT_MSK 0x00014404 /* ct */ 33 34#define HOST_PAGE_NUM_FN0 0x00014008 /* cb/ct */ 35#define HOST_PAGE_NUM_FN1 0x00014108 /* cb/ct */ 36#define HOST_PAGE_NUM_FN2 0x00014308 /* ct */ 37#define HOST_PAGE_NUM_FN3 0x00014408 /* ct */ 38 39#define APP_PLL_LCLK_CTL_REG 0x00014204 /* cb/ct */ 40#define __P_LCLK_PLL_LOCK 0x80000000 41#define __APP_PLL_LCLK_SRAM_USE_100MHZ 0x00100000 42#define __APP_PLL_LCLK_RESET_TIMER_MK 0x000e0000 43#define __APP_PLL_LCLK_RESET_TIMER_SH 17 44#define __APP_PLL_LCLK_RESET_TIMER(_v) ((_v) << __APP_PLL_LCLK_RESET_TIMER_SH) 45#define __APP_PLL_LCLK_LOGIC_SOFT_RESET 0x00010000 46#define __APP_PLL_LCLK_CNTLMT0_1_MK 0x0000c000 47#define __APP_PLL_LCLK_CNTLMT0_1_SH 14 48#define __APP_PLL_LCLK_CNTLMT0_1(_v) ((_v) << __APP_PLL_LCLK_CNTLMT0_1_SH) 49#define __APP_PLL_LCLK_JITLMT0_1_MK 0x00003000 50#define __APP_PLL_LCLK_JITLMT0_1_SH 12 51#define __APP_PLL_LCLK_JITLMT0_1(_v) ((_v) << __APP_PLL_LCLK_JITLMT0_1_SH) 52#define __APP_PLL_LCLK_HREF 0x00000800 53#define __APP_PLL_LCLK_HDIV 0x00000400 54#define __APP_PLL_LCLK_P0_1_MK 0x00000300 55#define __APP_PLL_LCLK_P0_1_SH 8 56#define __APP_PLL_LCLK_P0_1(_v) ((_v) << __APP_PLL_LCLK_P0_1_SH) 57#define __APP_PLL_LCLK_Z0_2_MK 0x000000e0 58#define __APP_PLL_LCLK_Z0_2_SH 5 59#define __APP_PLL_LCLK_Z0_2(_v) ((_v) << __APP_PLL_LCLK_Z0_2_SH) 60#define __APP_PLL_LCLK_RSEL200500 0x00000010 61#define __APP_PLL_LCLK_ENARST 0x00000008 62#define __APP_PLL_LCLK_BYPASS 0x00000004 63#define __APP_PLL_LCLK_LRESETN 0x00000002 64#define __APP_PLL_LCLK_ENABLE 0x00000001 65#define APP_PLL_SCLK_CTL_REG 0x00014208 /* cb/ct */ 66#define __P_SCLK_PLL_LOCK 0x80000000 67#define __APP_PLL_SCLK_RESET_TIMER_MK 0x000e0000 68#define __APP_PLL_SCLK_RESET_TIMER_SH 17 69#define __APP_PLL_SCLK_RESET_TIMER(_v) ((_v) << __APP_PLL_SCLK_RESET_TIMER_SH) 70#define __APP_PLL_SCLK_LOGIC_SOFT_RESET 0x00010000 71#define __APP_PLL_SCLK_CNTLMT0_1_MK 0x0000c000 72#define __APP_PLL_SCLK_CNTLMT0_1_SH 14 73#define __APP_PLL_SCLK_CNTLMT0_1(_v) ((_v) << __APP_PLL_SCLK_CNTLMT0_1_SH) 74#define __APP_PLL_SCLK_JITLMT0_1_MK 0x00003000 75#define __APP_PLL_SCLK_JITLMT0_1_SH 12 76#define __APP_PLL_SCLK_JITLMT0_1(_v) ((_v) << __APP_PLL_SCLK_JITLMT0_1_SH) 77#define __APP_PLL_SCLK_HREF 0x00000800 78#define __APP_PLL_SCLK_HDIV 0x00000400 79#define __APP_PLL_SCLK_P0_1_MK 0x00000300 80#define __APP_PLL_SCLK_P0_1_SH 8 81#define __APP_PLL_SCLK_P0_1(_v) ((_v) << __APP_PLL_SCLK_P0_1_SH) 82#define __APP_PLL_SCLK_Z0_2_MK 0x000000e0 83#define __APP_PLL_SCLK_Z0_2_SH 5 84#define __APP_PLL_SCLK_Z0_2(_v) ((_v) << __APP_PLL_SCLK_Z0_2_SH) 85#define __APP_PLL_SCLK_RSEL200500 0x00000010 86#define __APP_PLL_SCLK_ENARST 0x00000008 87#define __APP_PLL_SCLK_BYPASS 0x00000004 88#define __APP_PLL_SCLK_LRESETN 0x00000002 89#define __APP_PLL_SCLK_ENABLE 0x00000001 90#define __ENABLE_MAC_AHB_1 0x00800000 /* ct */ 91#define __ENABLE_MAC_AHB_0 0x00400000 /* ct */ 92#define __ENABLE_MAC_1 0x00200000 /* ct */ 93#define __ENABLE_MAC_0 0x00100000 /* ct */ 94 95#define HOST_SEM0_REG 0x00014230 /* cb/ct */ 96#define HOST_SEM1_REG 0x00014234 /* cb/ct */ 97#define HOST_SEM2_REG 0x00014238 /* cb/ct */ 98#define HOST_SEM3_REG 0x0001423c /* cb/ct */ 99#define HOST_SEM4_REG 0x00014610 /* cb/ct */ 100#define HOST_SEM5_REG 0x00014614 /* cb/ct */ 101#define HOST_SEM6_REG 0x00014618 /* cb/ct */ 102#define HOST_SEM7_REG 0x0001461c /* cb/ct */ 103#define HOST_SEM0_INFO_REG 0x00014240 /* cb/ct */ 104#define HOST_SEM1_INFO_REG 0x00014244 /* cb/ct */ 105#define HOST_SEM2_INFO_REG 0x00014248 /* cb/ct */ 106#define HOST_SEM3_INFO_REG 0x0001424c /* cb/ct */ 107#define HOST_SEM4_INFO_REG 0x00014620 /* cb/ct */ 108#define HOST_SEM5_INFO_REG 0x00014624 /* cb/ct */ 109#define HOST_SEM6_INFO_REG 0x00014628 /* cb/ct */ 110#define HOST_SEM7_INFO_REG 0x0001462c /* cb/ct */ 111 112#define HOSTFN0_LPU0_CMD_STAT 0x00019000 /* cb/ct */ 113#define HOSTFN0_LPU1_CMD_STAT 0x00019004 /* cb/ct */ 114#define HOSTFN1_LPU0_CMD_STAT 0x00019010 /* cb/ct */ 115#define HOSTFN1_LPU1_CMD_STAT 0x00019014 /* cb/ct */ 116#define HOSTFN2_LPU0_CMD_STAT 0x00019150 /* ct */ 117#define HOSTFN2_LPU1_CMD_STAT 0x00019154 /* ct */ 118#define HOSTFN3_LPU0_CMD_STAT 0x00019160 /* ct */ 119#define HOSTFN3_LPU1_CMD_STAT 0x00019164 /* ct */ 120#define LPU0_HOSTFN0_CMD_STAT 0x00019008 /* cb/ct */ 121#define LPU1_HOSTFN0_CMD_STAT 0x0001900c /* cb/ct */ 122#define LPU0_HOSTFN1_CMD_STAT 0x00019018 /* cb/ct */ 123#define LPU1_HOSTFN1_CMD_STAT 0x0001901c /* cb/ct */ 124#define LPU0_HOSTFN2_CMD_STAT 0x00019158 /* ct */ 125#define LPU1_HOSTFN2_CMD_STAT 0x0001915c /* ct */ 126#define LPU0_HOSTFN3_CMD_STAT 0x00019168 /* ct */ 127#define LPU1_HOSTFN3_CMD_STAT 0x0001916c /* ct */ 128 129#define PSS_CTL_REG 0x00018800 /* cb/ct */ 130#define __PSS_I2C_CLK_DIV_MK 0x007f0000 131#define __PSS_I2C_CLK_DIV_SH 16 132#define __PSS_I2C_CLK_DIV(_v) ((_v) << __PSS_I2C_CLK_DIV_SH) 133#define __PSS_LMEM_INIT_DONE 0x00001000 134#define __PSS_LMEM_RESET 0x00000200 135#define __PSS_LMEM_INIT_EN 0x00000100 136#define __PSS_LPU1_RESET 0x00000002 137#define __PSS_LPU0_RESET 0x00000001 138#define PSS_ERR_STATUS_REG 0x00018810 /* cb/ct */ 139#define ERR_SET_REG 0x00018818 /* cb/ct */ 140#define PSS_GPIO_OUT_REG 0x000188c0 /* cb/ct */ 141#define __PSS_GPIO_OUT_REG 0x00000fff 142#define PSS_GPIO_OE_REG 0x000188c8 /* cb/ct */ 143#define __PSS_GPIO_OE_REG 0x000000ff 144 145#define HOSTFN0_LPU_MBOX0_0 0x00019200 /* cb/ct */ 146#define HOSTFN1_LPU_MBOX0_8 0x00019260 /* cb/ct */ 147#define LPU_HOSTFN0_MBOX0_0 0x00019280 /* cb/ct */ 148#define LPU_HOSTFN1_MBOX0_8 0x000192e0 /* cb/ct */ 149#define HOSTFN2_LPU_MBOX0_0 0x00019400 /* ct */ 150#define HOSTFN3_LPU_MBOX0_8 0x00019460 /* ct */ 151#define LPU_HOSTFN2_MBOX0_0 0x00019480 /* ct */ 152#define LPU_HOSTFN3_MBOX0_8 0x000194e0 /* ct */ 153 154#define HOST_MSIX_ERR_INDEX_FN0 0x0001400c /* ct */ 155#define HOST_MSIX_ERR_INDEX_FN1 0x0001410c /* ct */ 156#define HOST_MSIX_ERR_INDEX_FN2 0x0001430c /* ct */ 157#define HOST_MSIX_ERR_INDEX_FN3 0x0001440c /* ct */ 158 159#define MBIST_CTL_REG 0x00014220 /* ct */ 160#define __EDRAM_BISTR_START 0x00000004 161#define MBIST_STAT_REG 0x00014224 /* ct */ 162#define ETH_MAC_SER_REG 0x00014288 /* ct */ 163#define __APP_EMS_CKBUFAMPIN 0x00000020 164#define __APP_EMS_REFCLKSEL 0x00000010 165#define __APP_EMS_CMLCKSEL 0x00000008 166#define __APP_EMS_REFCKBUFEN2 0x00000004 167#define __APP_EMS_REFCKBUFEN1 0x00000002 168#define __APP_EMS_CHANNEL_SEL 0x00000001 169#define FNC_PERS_REG 0x00014604 /* ct */ 170#define __F3_FUNCTION_ACTIVE 0x80000000 171#define __F3_FUNCTION_MODE 0x40000000 172#define __F3_PORT_MAP_MK 0x30000000 173#define __F3_PORT_MAP_SH 28 174#define __F3_PORT_MAP(_v) ((_v) << __F3_PORT_MAP_SH) 175#define __F3_VM_MODE 0x08000000 176#define __F3_INTX_STATUS_MK 0x07000000 177#define __F3_INTX_STATUS_SH 24 178#define __F3_INTX_STATUS(_v) ((_v) << __F3_INTX_STATUS_SH) 179#define __F2_FUNCTION_ACTIVE 0x00800000 180#define __F2_FUNCTION_MODE 0x00400000 181#define __F2_PORT_MAP_MK 0x00300000 182#define __F2_PORT_MAP_SH 20 183#define __F2_PORT_MAP(_v) ((_v) << __F2_PORT_MAP_SH) 184#define __F2_VM_MODE 0x00080000 185#define __F2_INTX_STATUS_MK 0x00070000 186#define __F2_INTX_STATUS_SH 16 187#define __F2_INTX_STATUS(_v) ((_v) << __F2_INTX_STATUS_SH) 188#define __F1_FUNCTION_ACTIVE 0x00008000 189#define __F1_FUNCTION_MODE 0x00004000 190#define __F1_PORT_MAP_MK 0x00003000 191#define __F1_PORT_MAP_SH 12 192#define __F1_PORT_MAP(_v) ((_v) << __F1_PORT_MAP_SH) 193#define __F1_VM_MODE 0x00000800 194#define __F1_INTX_STATUS_MK 0x00000700 195#define __F1_INTX_STATUS_SH 8 196#define __F1_INTX_STATUS(_v) ((_v) << __F1_INTX_STATUS_SH) 197#define __F0_FUNCTION_ACTIVE 0x00000080 198#define __F0_FUNCTION_MODE 0x00000040 199#define __F0_PORT_MAP_MK 0x00000030 200#define __F0_PORT_MAP_SH 4 201#define __F0_PORT_MAP(_v) ((_v) << __F0_PORT_MAP_SH) 202#define __F0_VM_MODE 0x00000008 203#define __F0_INTX_STATUS 0x00000007 204enum { 205 __F0_INTX_STATUS_MSIX = 0x0, 206 __F0_INTX_STATUS_INTA = 0x1, 207 __F0_INTX_STATUS_INTB = 0x2, 208 __F0_INTX_STATUS_INTC = 0x3, 209 __F0_INTX_STATUS_INTD = 0x4, 210}; 211 212#define OP_MODE 0x0001460c /* ct */ 213#define __APP_ETH_CLK_LOWSPEED 0x00000004 214#define __GLOBAL_CORECLK_HALFSPEED 0x00000002 215#define __GLOBAL_FCOE_MODE 0x00000001 216#define FW_INIT_HALT_P0 0x000191ac /* ct */ 217#define __FW_INIT_HALT_P 0x00000001 218#define FW_INIT_HALT_P1 0x000191bc /* ct */ 219#define PMM_1T_RESET_REG_P0 0x0002381c /* ct */ 220#define __PMM_1T_RESET_P 0x00000001 221#define PMM_1T_RESET_REG_P1 0x00023c1c /* ct */ 222 223/** 224 * Catapult-2 specific defines 225 */ 226#define CT2_PCI_CPQ_BASE 0x00030000 227#define CT2_PCI_APP_BASE 0x00030100 228#define CT2_PCI_ETH_BASE 0x00030400 229 230/* 231 * APP block registers 232 */ 233#define CT2_HOSTFN_INT_STATUS (CT2_PCI_APP_BASE + 0x00) 234#define CT2_HOSTFN_INTR_MASK (CT2_PCI_APP_BASE + 0x04) 235#define CT2_HOSTFN_PERSONALITY0 (CT2_PCI_APP_BASE + 0x08) 236#define __PME_STATUS_ 0x00200000 237#define __PF_VF_BAR_SIZE_MODE__MK 0x00180000 238#define __PF_VF_BAR_SIZE_MODE__SH 19 239#define __PF_VF_BAR_SIZE_MODE_(_v) ((_v) << __PF_VF_BAR_SIZE_MODE__SH) 240#define __FC_LL_PORT_MAP__MK 0x00060000 241#define __FC_LL_PORT_MAP__SH 17 242#define __FC_LL_PORT_MAP_(_v) ((_v) << __FC_LL_PORT_MAP__SH) 243#define __PF_VF_ACTIVE_ 0x00010000 244#define __PF_VF_CFG_RDY_ 0x00008000 245#define __PF_VF_ENABLE_ 0x00004000 246#define __PF_DRIVER_ACTIVE_ 0x00002000 247#define __PF_PME_SEND_ENABLE_ 0x00001000 248#define __PF_EXROM_OFFSET__MK 0x00000ff0 249#define __PF_EXROM_OFFSET__SH 4 250#define __PF_EXROM_OFFSET_(_v) ((_v) << __PF_EXROM_OFFSET__SH) 251#define __FC_LL_MODE_ 0x00000008 252#define __PF_INTX_PIN_ 0x00000007 253#define CT2_HOSTFN_PERSONALITY1 (CT2_PCI_APP_BASE + 0x0C) 254#define __PF_NUM_QUEUES1__MK 0xff000000 255#define __PF_NUM_QUEUES1__SH 24 256#define __PF_NUM_QUEUES1_(_v) ((_v) << __PF_NUM_QUEUES1__SH) 257#define __PF_VF_QUE_OFFSET1__MK 0x00ff0000 258#define __PF_VF_QUE_OFFSET1__SH 16 259#define __PF_VF_QUE_OFFSET1_(_v) ((_v) << __PF_VF_QUE_OFFSET1__SH) 260#define __PF_VF_NUM_QUEUES__MK 0x0000ff00 261#define __PF_VF_NUM_QUEUES__SH 8 262#define __PF_VF_NUM_QUEUES_(_v) ((_v) << __PF_VF_NUM_QUEUES__SH) 263#define __PF_VF_QUE_OFFSET_ 0x000000ff 264#define CT2_HOSTFN_PAGE_NUM (CT2_PCI_APP_BASE + 0x18) 265#define CT2_HOSTFN_MSIX_VT_INDEX_MBOX_ERR (CT2_PCI_APP_BASE + 0x38) 266 267/* 268 * Catapult-2 CPQ block registers 269 */ 270#define CT2_HOSTFN_LPU0_MBOX0 (CT2_PCI_CPQ_BASE + 0x00) 271#define CT2_HOSTFN_LPU1_MBOX0 (CT2_PCI_CPQ_BASE + 0x20) 272#define CT2_LPU0_HOSTFN_MBOX0 (CT2_PCI_CPQ_BASE + 0x40) 273#define CT2_LPU1_HOSTFN_MBOX0 (CT2_PCI_CPQ_BASE + 0x60) 274#define CT2_HOSTFN_LPU0_CMD_STAT (CT2_PCI_CPQ_BASE + 0x80) 275#define CT2_HOSTFN_LPU1_CMD_STAT (CT2_PCI_CPQ_BASE + 0x84) 276#define CT2_LPU0_HOSTFN_CMD_STAT (CT2_PCI_CPQ_BASE + 0x88) 277#define CT2_LPU1_HOSTFN_CMD_STAT (CT2_PCI_CPQ_BASE + 0x8c) 278#define CT2_HOSTFN_LPU0_READ_STAT (CT2_PCI_CPQ_BASE + 0x90) 279#define CT2_HOSTFN_LPU1_READ_STAT (CT2_PCI_CPQ_BASE + 0x94) 280#define CT2_LPU0_HOSTFN_MBOX0_MSK (CT2_PCI_CPQ_BASE + 0x98) 281#define CT2_LPU1_HOSTFN_MBOX0_MSK (CT2_PCI_CPQ_BASE + 0x9C) 282#define CT2_HOST_SEM0_REG 0x000148f0 283#define CT2_HOST_SEM1_REG 0x000148f4 284#define CT2_HOST_SEM2_REG 0x000148f8 285#define CT2_HOST_SEM3_REG 0x000148fc 286#define CT2_HOST_SEM4_REG 0x00014900 287#define CT2_HOST_SEM5_REG 0x00014904 288#define CT2_HOST_SEM6_REG 0x00014908 289#define CT2_HOST_SEM7_REG 0x0001490c 290#define CT2_HOST_SEM0_INFO_REG 0x000148b0 291#define CT2_HOST_SEM1_INFO_REG 0x000148b4 292#define CT2_HOST_SEM2_INFO_REG 0x000148b8 293#define CT2_HOST_SEM3_INFO_REG 0x000148bc 294#define CT2_HOST_SEM4_INFO_REG 0x000148c0 295#define CT2_HOST_SEM5_INFO_REG 0x000148c4 296#define CT2_HOST_SEM6_INFO_REG 0x000148c8 297#define CT2_HOST_SEM7_INFO_REG 0x000148cc 298 299#define CT2_APP_PLL_LCLK_CTL_REG 0x00014808 300#define __APP_LPUCLK_HALFSPEED 0x40000000 301#define __APP_PLL_LCLK_LOAD 0x20000000 302#define __APP_PLL_LCLK_FBCNT_MK 0x1fe00000 303#define __APP_PLL_LCLK_FBCNT_SH 21 304#define __APP_PLL_LCLK_FBCNT(_v) ((_v) << __APP_PLL_SCLK_FBCNT_SH) 305enum { 306 __APP_PLL_LCLK_FBCNT_425_MHZ = 6, 307 __APP_PLL_LCLK_FBCNT_468_MHZ = 4, 308}; 309#define __APP_PLL_LCLK_EXTFB 0x00000800 310#define __APP_PLL_LCLK_ENOUTS 0x00000400 311#define __APP_PLL_LCLK_RATE 0x00000010 312#define CT2_APP_PLL_SCLK_CTL_REG 0x0001480c 313#define __P_SCLK_PLL_LOCK 0x80000000 314#define __APP_PLL_SCLK_REFCLK_SEL 0x40000000 315#define __APP_PLL_SCLK_CLK_DIV2 0x20000000 316#define __APP_PLL_SCLK_LOAD 0x10000000 317#define __APP_PLL_SCLK_FBCNT_MK 0x0ff00000 318#define __APP_PLL_SCLK_FBCNT_SH 20 319#define __APP_PLL_SCLK_FBCNT(_v) ((_v) << __APP_PLL_SCLK_FBCNT_SH) 320enum { 321 __APP_PLL_SCLK_FBCNT_NORM = 6, 322 __APP_PLL_SCLK_FBCNT_10G_FC = 10, 323}; 324#define __APP_PLL_SCLK_EXTFB 0x00000800 325#define __APP_PLL_SCLK_ENOUTS 0x00000400 326#define __APP_PLL_SCLK_RATE 0x00000010 327#define CT2_PCIE_MISC_REG 0x00014804 328#define __ETH_CLK_ENABLE_PORT1 0x00000010 329#define CT2_CHIP_MISC_PRG 0x000148a4 330#define __ETH_CLK_ENABLE_PORT0 0x00004000 331#define __APP_LPU_SPEED 0x00000002 332#define CT2_MBIST_STAT_REG 0x00014818 333#define CT2_MBIST_CTL_REG 0x0001481c 334#define CT2_PMM_1T_CONTROL_REG_P0 0x0002381c 335#define __PMM_1T_PNDB_P 0x00000002 336#define CT2_PMM_1T_CONTROL_REG_P1 0x00023c1c 337#define CT2_WGN_STATUS 0x00014990 338#define __A2T_AHB_LOAD 0x00000800 339#define __WGN_READY 0x00000400 340#define __GLBL_PF_VF_CFG_RDY 0x00000200 341#define CT2_NFC_STS_REG 0x00027410 342#define CT2_NFC_CSR_CLR_REG 0x00027420 343#define CT2_NFC_CSR_SET_REG 0x00027424 344#define __HALT_NFC_CONTROLLER 0x00000002 345#define __NFC_CONTROLLER_HALTED 0x00001000 346#define CT2_RSC_GPR15_REG 0x0002765c 347#define CT2_CSI_FW_CTL_REG 0x00027080 348#define CT2_CSI_FW_CTL_SET_REG 0x00027088 349#define __RESET_AND_START_SCLK_LCLK_PLLS 0x00010000 350 351#define CT2_CSI_MAC0_CONTROL_REG 0x000270d0 352#define __CSI_MAC_RESET 0x00000010 353#define __CSI_MAC_AHB_RESET 0x00000008 354#define CT2_CSI_MAC1_CONTROL_REG 0x000270d4 355#define CT2_CSI_MAC_CONTROL_REG(__n) \ 356 (CT2_CSI_MAC0_CONTROL_REG + \ 357 (__n) * (CT2_CSI_MAC1_CONTROL_REG - CT2_CSI_MAC0_CONTROL_REG)) 358 359#define CT2_NFC_FLASH_STS_REG 0x00014834 360#define __FLASH_PLL_INIT_AND_RESET_IN_PROGRESS 0x00000020 361/* 362 * Name semaphore registers based on usage 363 */ 364#define BFA_IOC0_HBEAT_REG HOST_SEM0_INFO_REG 365#define BFA_IOC0_STATE_REG HOST_SEM1_INFO_REG 366#define BFA_IOC1_HBEAT_REG HOST_SEM2_INFO_REG 367#define BFA_IOC1_STATE_REG HOST_SEM3_INFO_REG 368#define BFA_FW_USE_COUNT HOST_SEM4_INFO_REG 369#define BFA_IOC_FAIL_SYNC HOST_SEM5_INFO_REG 370 371/* 372 * CT2 semaphore register locations changed 373 */ 374#define CT2_BFA_IOC0_HBEAT_REG CT2_HOST_SEM0_INFO_REG 375#define CT2_BFA_IOC0_STATE_REG CT2_HOST_SEM1_INFO_REG 376#define CT2_BFA_IOC1_HBEAT_REG CT2_HOST_SEM2_INFO_REG 377#define CT2_BFA_IOC1_STATE_REG CT2_HOST_SEM3_INFO_REG 378#define CT2_BFA_FW_USE_COUNT CT2_HOST_SEM4_INFO_REG 379#define CT2_BFA_IOC_FAIL_SYNC CT2_HOST_SEM5_INFO_REG 380 381#define CPE_Q_NUM(__fn, __q) (((__fn) << 2) + (__q)) 382#define RME_Q_NUM(__fn, __q) (((__fn) << 2) + (__q)) 383 384/* 385 * And corresponding host interrupt status bit field defines 386 */ 387#define __HFN_INT_CPE_Q0 0x00000001U 388#define __HFN_INT_CPE_Q1 0x00000002U 389#define __HFN_INT_CPE_Q2 0x00000004U 390#define __HFN_INT_CPE_Q3 0x00000008U 391#define __HFN_INT_CPE_Q4 0x00000010U 392#define __HFN_INT_CPE_Q5 0x00000020U 393#define __HFN_INT_CPE_Q6 0x00000040U 394#define __HFN_INT_CPE_Q7 0x00000080U 395#define __HFN_INT_RME_Q0 0x00000100U 396#define __HFN_INT_RME_Q1 0x00000200U 397#define __HFN_INT_RME_Q2 0x00000400U 398#define __HFN_INT_RME_Q3 0x00000800U 399#define __HFN_INT_RME_Q4 0x00001000U 400#define __HFN_INT_RME_Q5 0x00002000U 401#define __HFN_INT_RME_Q6 0x00004000U 402#define __HFN_INT_RME_Q7 0x00008000U 403#define __HFN_INT_ERR_EMC 0x00010000U 404#define __HFN_INT_ERR_LPU0 0x00020000U 405#define __HFN_INT_ERR_LPU1 0x00040000U 406#define __HFN_INT_ERR_PSS 0x00080000U 407#define __HFN_INT_MBOX_LPU0 0x00100000U 408#define __HFN_INT_MBOX_LPU1 0x00200000U 409#define __HFN_INT_MBOX1_LPU0 0x00400000U 410#define __HFN_INT_MBOX1_LPU1 0x00800000U 411#define __HFN_INT_LL_HALT 0x01000000U 412#define __HFN_INT_CPE_MASK 0x000000ffU 413#define __HFN_INT_RME_MASK 0x0000ff00U 414#define __HFN_INT_ERR_MASK \ 415 (__HFN_INT_ERR_EMC | __HFN_INT_ERR_LPU0 | __HFN_INT_ERR_LPU1 | \ 416 __HFN_INT_ERR_PSS | __HFN_INT_LL_HALT) 417#define __HFN_INT_FN0_MASK \ 418 (__HFN_INT_CPE_Q0 | __HFN_INT_CPE_Q1 | __HFN_INT_CPE_Q2 | \ 419 __HFN_INT_CPE_Q3 | __HFN_INT_RME_Q0 | __HFN_INT_RME_Q1 | \ 420 __HFN_INT_RME_Q2 | __HFN_INT_RME_Q3 | __HFN_INT_MBOX_LPU0) 421#define __HFN_INT_FN1_MASK \ 422 (__HFN_INT_CPE_Q4 | __HFN_INT_CPE_Q5 | __HFN_INT_CPE_Q6 | \ 423 __HFN_INT_CPE_Q7 | __HFN_INT_RME_Q4 | __HFN_INT_RME_Q5 | \ 424 __HFN_INT_RME_Q6 | __HFN_INT_RME_Q7 | __HFN_INT_MBOX_LPU1) 425 426/* 427 * Host interrupt status defines for catapult-2 428 */ 429#define __HFN_INT_MBOX_LPU0_CT2 0x00010000U 430#define __HFN_INT_MBOX_LPU1_CT2 0x00020000U 431#define __HFN_INT_ERR_PSS_CT2 0x00040000U 432#define __HFN_INT_ERR_LPU0_CT2 0x00080000U 433#define __HFN_INT_ERR_LPU1_CT2 0x00100000U 434#define __HFN_INT_CPQ_HALT_CT2 0x00200000U 435#define __HFN_INT_ERR_WGN_CT2 0x00400000U 436#define __HFN_INT_ERR_LEHRX_CT2 0x00800000U 437#define __HFN_INT_ERR_LEHTX_CT2 0x01000000U 438#define __HFN_INT_ERR_MASK_CT2 \ 439 (__HFN_INT_ERR_PSS_CT2 | __HFN_INT_ERR_LPU0_CT2 | \ 440 __HFN_INT_ERR_LPU1_CT2 | __HFN_INT_CPQ_HALT_CT2 | \ 441 __HFN_INT_ERR_WGN_CT2 | __HFN_INT_ERR_LEHRX_CT2 | \ 442 __HFN_INT_ERR_LEHTX_CT2) 443#define __HFN_INT_FN0_MASK_CT2 \ 444 (__HFN_INT_CPE_Q0 | __HFN_INT_CPE_Q1 | __HFN_INT_CPE_Q2 | \ 445 __HFN_INT_CPE_Q3 | __HFN_INT_RME_Q0 | __HFN_INT_RME_Q1 | \ 446 __HFN_INT_RME_Q2 | __HFN_INT_RME_Q3 | __HFN_INT_MBOX_LPU0_CT2) 447#define __HFN_INT_FN1_MASK_CT2 \ 448 (__HFN_INT_CPE_Q4 | __HFN_INT_CPE_Q5 | __HFN_INT_CPE_Q6 | \ 449 __HFN_INT_CPE_Q7 | __HFN_INT_RME_Q4 | __HFN_INT_RME_Q5 | \ 450 __HFN_INT_RME_Q6 | __HFN_INT_RME_Q7 | __HFN_INT_MBOX_LPU1_CT2) 451 452/* 453 * asic memory map. 454 */ 455#define PSS_SMEM_PAGE_START 0x8000 456#define PSS_SMEM_PGNUM(_pg0, _ma) ((_pg0) + ((_ma) >> 15)) 457#define PSS_SMEM_PGOFF(_ma) ((_ma) & 0x7fff) 458 459#endif /* __BFI_REG_H__ */ 460