1 #ifndef dprintk
2 # define dprintk(x)
3 #endif
4 /* eg: if (nblank(dprintk(x))) */
5 #define _nblank(x) #x
6 #define nblank(x) _nblank(x)[0]
7
8 #include <linux/interrupt.h>
9 #include <linux/pci.h>
10
11 /*------------------------------------------------------------------------------
12 * D E F I N E S
13 *----------------------------------------------------------------------------*/
14
15 #define AAC_MAX_MSIX 8 /* vectors */
16 #define AAC_PCI_MSI_ENABLE 0x8000
17
18 enum {
19 AAC_ENABLE_INTERRUPT = 0x0,
20 AAC_DISABLE_INTERRUPT,
21 AAC_ENABLE_MSIX,
22 AAC_DISABLE_MSIX,
23 AAC_CLEAR_AIF_BIT,
24 AAC_CLEAR_SYNC_BIT,
25 AAC_ENABLE_INTX
26 };
27
28 #define AAC_INT_MODE_INTX (1<<0)
29 #define AAC_INT_MODE_MSI (1<<1)
30 #define AAC_INT_MODE_AIF (1<<2)
31 #define AAC_INT_MODE_SYNC (1<<3)
32 #define AAC_INT_MODE_MSIX (1<<16)
33
34 #define AAC_INT_ENABLE_TYPE1_INTX 0xfffffffb
35 #define AAC_INT_ENABLE_TYPE1_MSIX 0xfffffffa
36 #define AAC_INT_DISABLE_ALL 0xffffffff
37
38 /* Bit definitions in IOA->Host Interrupt Register */
39 #define PMC_TRANSITION_TO_OPERATIONAL (1<<31)
40 #define PMC_IOARCB_TRANSFER_FAILED (1<<28)
41 #define PMC_IOA_UNIT_CHECK (1<<27)
42 #define PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE (1<<26)
43 #define PMC_CRITICAL_IOA_OP_IN_PROGRESS (1<<25)
44 #define PMC_IOARRIN_LOST (1<<4)
45 #define PMC_SYSTEM_BUS_MMIO_ERROR (1<<3)
46 #define PMC_IOA_PROCESSOR_IN_ERROR_STATE (1<<2)
47 #define PMC_HOST_RRQ_VALID (1<<1)
48 #define PMC_OPERATIONAL_STATUS (1<<31)
49 #define PMC_ALLOW_MSIX_VECTOR0 (1<<0)
50
51 #define PMC_IOA_ERROR_INTERRUPTS (PMC_IOARCB_TRANSFER_FAILED | \
52 PMC_IOA_UNIT_CHECK | \
53 PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE | \
54 PMC_IOARRIN_LOST | \
55 PMC_SYSTEM_BUS_MMIO_ERROR | \
56 PMC_IOA_PROCESSOR_IN_ERROR_STATE)
57
58 #define PMC_ALL_INTERRUPT_BITS (PMC_IOA_ERROR_INTERRUPTS | \
59 PMC_HOST_RRQ_VALID | \
60 PMC_TRANSITION_TO_OPERATIONAL | \
61 PMC_ALLOW_MSIX_VECTOR0)
62 #define PMC_GLOBAL_INT_BIT2 0x00000004
63 #define PMC_GLOBAL_INT_BIT0 0x00000001
64
65 #ifndef AAC_DRIVER_BUILD
66 # define AAC_DRIVER_BUILD 40709
67 # define AAC_DRIVER_BRANCH "-ms"
68 #endif
69 #define MAXIMUM_NUM_CONTAINERS 32
70
71 #define AAC_NUM_MGT_FIB 8
72 #define AAC_NUM_IO_FIB (1024 - AAC_NUM_MGT_FIB)
73 #define AAC_NUM_FIB (AAC_NUM_IO_FIB + AAC_NUM_MGT_FIB)
74
75 #define AAC_MAX_LUN (8)
76
77 #define AAC_MAX_HOSTPHYSMEMPAGES (0xfffff)
78 #define AAC_MAX_32BIT_SGBCOUNT ((unsigned short)256)
79
80 #define AAC_DEBUG_INSTRUMENT_AIF_DELETE
81
82 /*
83 * These macros convert from physical channels to virtual channels
84 */
85 #define CONTAINER_CHANNEL (0)
86 #define CONTAINER_TO_CHANNEL(cont) (CONTAINER_CHANNEL)
87 #define CONTAINER_TO_ID(cont) (cont)
88 #define CONTAINER_TO_LUN(cont) (0)
89
90 #define PMC_DEVICE_S6 0x28b
91 #define PMC_DEVICE_S7 0x28c
92 #define PMC_DEVICE_S8 0x28d
93 #define PMC_DEVICE_S9 0x28f
94
95 #define aac_phys_to_logical(x) ((x)+1)
96 #define aac_logical_to_phys(x) ((x)?(x)-1:0)
97
98 /* #define AAC_DETAILED_STATUS_INFO */
99
100 struct diskparm
101 {
102 int heads;
103 int sectors;
104 int cylinders;
105 };
106
107
108 /*
109 * Firmware constants
110 */
111
112 #define CT_NONE 0
113 #define CT_OK 218
114 #define FT_FILESYS 8 /* ADAPTEC's "FSA"(tm) filesystem */
115 #define FT_DRIVE 9 /* physical disk - addressable in scsi by bus/id/lun */
116
117 /*
118 * Host side memory scatter gather list
119 * Used by the adapter for read, write, and readdirplus operations
120 * We have separate 32 and 64 bit version because even
121 * on 64 bit systems not all cards support the 64 bit version
122 */
123 struct sgentry {
124 __le32 addr; /* 32-bit address. */
125 __le32 count; /* Length. */
126 };
127
128 struct user_sgentry {
129 u32 addr; /* 32-bit address. */
130 u32 count; /* Length. */
131 };
132
133 struct sgentry64 {
134 __le32 addr[2]; /* 64-bit addr. 2 pieces for data alignment */
135 __le32 count; /* Length. */
136 };
137
138 struct user_sgentry64 {
139 u32 addr[2]; /* 64-bit addr. 2 pieces for data alignment */
140 u32 count; /* Length. */
141 };
142
143 struct sgentryraw {
144 __le32 next; /* reserved for F/W use */
145 __le32 prev; /* reserved for F/W use */
146 __le32 addr[2];
147 __le32 count;
148 __le32 flags; /* reserved for F/W use */
149 };
150
151 struct user_sgentryraw {
152 u32 next; /* reserved for F/W use */
153 u32 prev; /* reserved for F/W use */
154 u32 addr[2];
155 u32 count;
156 u32 flags; /* reserved for F/W use */
157 };
158
159 struct sge_ieee1212 {
160 u32 addrLow;
161 u32 addrHigh;
162 u32 length;
163 u32 flags;
164 };
165
166 /*
167 * SGMAP
168 *
169 * This is the SGMAP structure for all commands that use
170 * 32-bit addressing.
171 */
172
173 struct sgmap {
174 __le32 count;
175 struct sgentry sg[1];
176 };
177
178 struct user_sgmap {
179 u32 count;
180 struct user_sgentry sg[1];
181 };
182
183 struct sgmap64 {
184 __le32 count;
185 struct sgentry64 sg[1];
186 };
187
188 struct user_sgmap64 {
189 u32 count;
190 struct user_sgentry64 sg[1];
191 };
192
193 struct sgmapraw {
194 __le32 count;
195 struct sgentryraw sg[1];
196 };
197
198 struct user_sgmapraw {
199 u32 count;
200 struct user_sgentryraw sg[1];
201 };
202
203 struct creation_info
204 {
205 u8 buildnum; /* e.g., 588 */
206 u8 usec; /* e.g., 588 */
207 u8 via; /* e.g., 1 = FSU,
208 * 2 = API
209 */
210 u8 year; /* e.g., 1997 = 97 */
211 __le32 date; /*
212 * unsigned Month :4; // 1 - 12
213 * unsigned Day :6; // 1 - 32
214 * unsigned Hour :6; // 0 - 23
215 * unsigned Minute :6; // 0 - 60
216 * unsigned Second :6; // 0 - 60
217 */
218 __le32 serial[2]; /* e.g., 0x1DEADB0BFAFAF001 */
219 };
220
221
222 /*
223 * Define all the constants needed for the communication interface
224 */
225
226 /*
227 * Define how many queue entries each queue will have and the total
228 * number of entries for the entire communication interface. Also define
229 * how many queues we support.
230 *
231 * This has to match the controller
232 */
233
234 #define NUMBER_OF_COMM_QUEUES 8 // 4 command; 4 response
235 #define HOST_HIGH_CMD_ENTRIES 4
236 #define HOST_NORM_CMD_ENTRIES 8
237 #define ADAP_HIGH_CMD_ENTRIES 4
238 #define ADAP_NORM_CMD_ENTRIES 512
239 #define HOST_HIGH_RESP_ENTRIES 4
240 #define HOST_NORM_RESP_ENTRIES 512
241 #define ADAP_HIGH_RESP_ENTRIES 4
242 #define ADAP_NORM_RESP_ENTRIES 8
243
244 #define TOTAL_QUEUE_ENTRIES \
245 (HOST_NORM_CMD_ENTRIES + HOST_HIGH_CMD_ENTRIES + ADAP_NORM_CMD_ENTRIES + ADAP_HIGH_CMD_ENTRIES + \
246 HOST_NORM_RESP_ENTRIES + HOST_HIGH_RESP_ENTRIES + ADAP_NORM_RESP_ENTRIES + ADAP_HIGH_RESP_ENTRIES)
247
248
249 /*
250 * Set the queues on a 16 byte alignment
251 */
252
253 #define QUEUE_ALIGNMENT 16
254
255 /*
256 * The queue headers define the Communication Region queues. These
257 * are physically contiguous and accessible by both the adapter and the
258 * host. Even though all queue headers are in the same contiguous block
259 * they will be represented as individual units in the data structures.
260 */
261
262 struct aac_entry {
263 __le32 size; /* Size in bytes of Fib which this QE points to */
264 __le32 addr; /* Receiver address of the FIB */
265 };
266
267 /*
268 * The adapter assumes the ProducerIndex and ConsumerIndex are grouped
269 * adjacently and in that order.
270 */
271
272 struct aac_qhdr {
273 __le64 header_addr;/* Address to hand the adapter to access
274 to this queue head */
275 __le32 *producer; /* The producer index for this queue (host address) */
276 __le32 *consumer; /* The consumer index for this queue (host address) */
277 };
278
279 /*
280 * Define all the events which the adapter would like to notify
281 * the host of.
282 */
283
284 #define HostNormCmdQue 1 /* Change in host normal priority command queue */
285 #define HostHighCmdQue 2 /* Change in host high priority command queue */
286 #define HostNormRespQue 3 /* Change in host normal priority response queue */
287 #define HostHighRespQue 4 /* Change in host high priority response queue */
288 #define AdapNormRespNotFull 5
289 #define AdapHighRespNotFull 6
290 #define AdapNormCmdNotFull 7
291 #define AdapHighCmdNotFull 8
292 #define SynchCommandComplete 9
293 #define AdapInternalError 0xfe /* The adapter detected an internal error shutting down */
294
295 /*
296 * Define all the events the host wishes to notify the
297 * adapter of. The first four values much match the Qid the
298 * corresponding queue.
299 */
300
301 #define AdapNormCmdQue 2
302 #define AdapHighCmdQue 3
303 #define AdapNormRespQue 6
304 #define AdapHighRespQue 7
305 #define HostShutdown 8
306 #define HostPowerFail 9
307 #define FatalCommError 10
308 #define HostNormRespNotFull 11
309 #define HostHighRespNotFull 12
310 #define HostNormCmdNotFull 13
311 #define HostHighCmdNotFull 14
312 #define FastIo 15
313 #define AdapPrintfDone 16
314
315 /*
316 * Define all the queues that the adapter and host use to communicate
317 * Number them to match the physical queue layout.
318 */
319
320 enum aac_queue_types {
321 HostNormCmdQueue = 0, /* Adapter to host normal priority command traffic */
322 HostHighCmdQueue, /* Adapter to host high priority command traffic */
323 AdapNormCmdQueue, /* Host to adapter normal priority command traffic */
324 AdapHighCmdQueue, /* Host to adapter high priority command traffic */
325 HostNormRespQueue, /* Adapter to host normal priority response traffic */
326 HostHighRespQueue, /* Adapter to host high priority response traffic */
327 AdapNormRespQueue, /* Host to adapter normal priority response traffic */
328 AdapHighRespQueue /* Host to adapter high priority response traffic */
329 };
330
331 /*
332 * Assign type values to the FSA communication data structures
333 */
334
335 #define FIB_MAGIC 0x0001
336 #define FIB_MAGIC2 0x0004
337 #define FIB_MAGIC2_64 0x0005
338
339 /*
340 * Define the priority levels the FSA communication routines support.
341 */
342
343 #define FsaNormal 1
344
345 /* transport FIB header (PMC) */
346 struct aac_fib_xporthdr {
347 u64 HostAddress; /* FIB host address w/o xport header */
348 u32 Size; /* FIB size excluding xport header */
349 u32 Handle; /* driver handle to reference the FIB */
350 u64 Reserved[2];
351 };
352
353 #define ALIGN32 32
354
355 /*
356 * Define the FIB. The FIB is the where all the requested data and
357 * command information are put to the application on the FSA adapter.
358 */
359
360 struct aac_fibhdr {
361 __le32 XferState; /* Current transfer state for this CCB */
362 __le16 Command; /* Routing information for the destination */
363 u8 StructType; /* Type FIB */
364 u8 Unused; /* Unused */
365 __le16 Size; /* Size of this FIB in bytes */
366 __le16 SenderSize; /* Size of the FIB in the sender
367 (for response sizing) */
368 __le32 SenderFibAddress; /* Host defined data in the FIB */
369 union {
370 __le32 ReceiverFibAddress;/* Logical address of this FIB for
371 the adapter (old) */
372 __le32 SenderFibAddressHigh;/* upper 32bit of phys. FIB address */
373 __le32 TimeStamp; /* otherwise timestamp for FW internal use */
374 } u;
375 u32 Handle; /* FIB handle used for MSGU commnunication */
376 u32 Previous; /* FW internal use */
377 u32 Next; /* FW internal use */
378 };
379
380 struct hw_fib {
381 struct aac_fibhdr header;
382 u8 data[512-sizeof(struct aac_fibhdr)]; // Command specific data
383 };
384
385 /*
386 * FIB commands
387 */
388
389 #define TestCommandResponse 1
390 #define TestAdapterCommand 2
391 /*
392 * Lowlevel and comm commands
393 */
394 #define LastTestCommand 100
395 #define ReinitHostNormCommandQueue 101
396 #define ReinitHostHighCommandQueue 102
397 #define ReinitHostHighRespQueue 103
398 #define ReinitHostNormRespQueue 104
399 #define ReinitAdapNormCommandQueue 105
400 #define ReinitAdapHighCommandQueue 107
401 #define ReinitAdapHighRespQueue 108
402 #define ReinitAdapNormRespQueue 109
403 #define InterfaceShutdown 110
404 #define DmaCommandFib 120
405 #define StartProfile 121
406 #define TermProfile 122
407 #define SpeedTest 123
408 #define TakeABreakPt 124
409 #define RequestPerfData 125
410 #define SetInterruptDefTimer 126
411 #define SetInterruptDefCount 127
412 #define GetInterruptDefStatus 128
413 #define LastCommCommand 129
414 /*
415 * Filesystem commands
416 */
417 #define NuFileSystem 300
418 #define UFS 301
419 #define HostFileSystem 302
420 #define LastFileSystemCommand 303
421 /*
422 * Container Commands
423 */
424 #define ContainerCommand 500
425 #define ContainerCommand64 501
426 #define ContainerRawIo 502
427 #define ContainerRawIo2 503
428 /*
429 * Scsi Port commands (scsi passthrough)
430 */
431 #define ScsiPortCommand 600
432 #define ScsiPortCommand64 601
433 /*
434 * Misc house keeping and generic adapter initiated commands
435 */
436 #define AifRequest 700
437 #define CheckRevision 701
438 #define FsaHostShutdown 702
439 #define RequestAdapterInfo 703
440 #define IsAdapterPaused 704
441 #define SendHostTime 705
442 #define RequestSupplementAdapterInfo 706
443 #define LastMiscCommand 707
444
445 /*
446 * Commands that will target the failover level on the FSA adapter
447 */
448
449 enum fib_xfer_state {
450 HostOwned = (1<<0),
451 AdapterOwned = (1<<1),
452 FibInitialized = (1<<2),
453 FibEmpty = (1<<3),
454 AllocatedFromPool = (1<<4),
455 SentFromHost = (1<<5),
456 SentFromAdapter = (1<<6),
457 ResponseExpected = (1<<7),
458 NoResponseExpected = (1<<8),
459 AdapterProcessed = (1<<9),
460 HostProcessed = (1<<10),
461 HighPriority = (1<<11),
462 NormalPriority = (1<<12),
463 Async = (1<<13),
464 AsyncIo = (1<<13), // rpbfix: remove with new regime
465 PageFileIo = (1<<14), // rpbfix: remove with new regime
466 ShutdownRequest = (1<<15),
467 LazyWrite = (1<<16), // rpbfix: remove with new regime
468 AdapterMicroFib = (1<<17),
469 BIOSFibPath = (1<<18),
470 FastResponseCapable = (1<<19),
471 ApiFib = (1<<20), /* Its an API Fib */
472 /* PMC NEW COMM: There is no more AIF data pending */
473 NoMoreAifDataAvailable = (1<<21)
474 };
475
476 /*
477 * The following defines needs to be updated any time there is an
478 * incompatible change made to the aac_init structure.
479 */
480
481 #define ADAPTER_INIT_STRUCT_REVISION 3
482 #define ADAPTER_INIT_STRUCT_REVISION_4 4 // rocket science
483 #define ADAPTER_INIT_STRUCT_REVISION_6 6 /* PMC src */
484 #define ADAPTER_INIT_STRUCT_REVISION_7 7 /* Denali */
485
486 struct aac_init
487 {
488 __le32 InitStructRevision;
489 __le32 Sa_MSIXVectors;
490 __le32 fsrev;
491 __le32 CommHeaderAddress;
492 __le32 FastIoCommAreaAddress;
493 __le32 AdapterFibsPhysicalAddress;
494 __le32 AdapterFibsVirtualAddress;
495 __le32 AdapterFibsSize;
496 __le32 AdapterFibAlign;
497 __le32 printfbuf;
498 __le32 printfbufsiz;
499 __le32 HostPhysMemPages; /* number of 4k pages of host
500 physical memory */
501 __le32 HostElapsedSeconds; /* number of seconds since 1970. */
502 /*
503 * ADAPTER_INIT_STRUCT_REVISION_4 begins here
504 */
505 __le32 InitFlags; /* flags for supported features */
506 #define INITFLAGS_NEW_COMM_SUPPORTED 0x00000001
507 #define INITFLAGS_DRIVER_USES_UTC_TIME 0x00000010
508 #define INITFLAGS_DRIVER_SUPPORTS_PM 0x00000020
509 #define INITFLAGS_NEW_COMM_TYPE1_SUPPORTED 0x00000040
510 #define INITFLAGS_FAST_JBOD_SUPPORTED 0x00000080
511 #define INITFLAGS_NEW_COMM_TYPE2_SUPPORTED 0x00000100
512 __le32 MaxIoCommands; /* max outstanding commands */
513 __le32 MaxIoSize; /* largest I/O command */
514 __le32 MaxFibSize; /* largest FIB to adapter */
515 /* ADAPTER_INIT_STRUCT_REVISION_5 begins here */
516 __le32 MaxNumAif; /* max number of aif */
517 /* ADAPTER_INIT_STRUCT_REVISION_6 begins here */
518 __le32 HostRRQ_AddrLow;
519 __le32 HostRRQ_AddrHigh; /* Host RRQ (response queue) for SRC */
520 };
521
522 enum aac_log_level {
523 LOG_AAC_INIT = 10,
524 LOG_AAC_INFORMATIONAL = 20,
525 LOG_AAC_WARNING = 30,
526 LOG_AAC_LOW_ERROR = 40,
527 LOG_AAC_MEDIUM_ERROR = 50,
528 LOG_AAC_HIGH_ERROR = 60,
529 LOG_AAC_PANIC = 70,
530 LOG_AAC_DEBUG = 80,
531 LOG_AAC_WINDBG_PRINT = 90
532 };
533
534 #define FSAFS_NTC_GET_ADAPTER_FIB_CONTEXT 0x030b
535 #define FSAFS_NTC_FIB_CONTEXT 0x030c
536
537 struct aac_dev;
538 struct fib;
539 struct scsi_cmnd;
540
541 struct adapter_ops
542 {
543 /* Low level operations */
544 void (*adapter_interrupt)(struct aac_dev *dev);
545 void (*adapter_notify)(struct aac_dev *dev, u32 event);
546 void (*adapter_disable_int)(struct aac_dev *dev);
547 void (*adapter_enable_int)(struct aac_dev *dev);
548 int (*adapter_sync_cmd)(struct aac_dev *dev, u32 command, u32 p1, u32 p2, u32 p3, u32 p4, u32 p5, u32 p6, u32 *status, u32 *r1, u32 *r2, u32 *r3, u32 *r4);
549 int (*adapter_check_health)(struct aac_dev *dev);
550 int (*adapter_restart)(struct aac_dev *dev, int bled);
551 /* Transport operations */
552 int (*adapter_ioremap)(struct aac_dev * dev, u32 size);
553 irq_handler_t adapter_intr;
554 /* Packet operations */
555 int (*adapter_deliver)(struct fib * fib);
556 int (*adapter_bounds)(struct aac_dev * dev, struct scsi_cmnd * cmd, u64 lba);
557 int (*adapter_read)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count);
558 int (*adapter_write)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count, int fua);
559 int (*adapter_scsi)(struct fib * fib, struct scsi_cmnd * cmd);
560 /* Administrative operations */
561 int (*adapter_comm)(struct aac_dev * dev, int comm);
562 };
563
564 /*
565 * Define which interrupt handler needs to be installed
566 */
567
568 struct aac_driver_ident
569 {
570 int (*init)(struct aac_dev *dev);
571 char * name;
572 char * vname;
573 char * model;
574 u16 channels;
575 int quirks;
576 };
577 /*
578 * Some adapter firmware needs communication memory
579 * below 2gig. This tells the init function to set the
580 * dma mask such that fib memory will be allocated where the
581 * adapter firmware can get to it.
582 */
583 #define AAC_QUIRK_31BIT 0x0001
584
585 /*
586 * Some adapter firmware, when the raid card's cache is turned off, can not
587 * split up scatter gathers in order to deal with the limits of the
588 * underlying CHIM. This limit is 34 scatter gather elements.
589 */
590 #define AAC_QUIRK_34SG 0x0002
591
592 /*
593 * This adapter is a slave (no Firmware)
594 */
595 #define AAC_QUIRK_SLAVE 0x0004
596
597 /*
598 * This adapter is a master.
599 */
600 #define AAC_QUIRK_MASTER 0x0008
601
602 /*
603 * Some adapter firmware perform poorly when it must split up scatter gathers
604 * in order to deal with the limits of the underlying CHIM. This limit in this
605 * class of adapters is 17 scatter gather elements.
606 */
607 #define AAC_QUIRK_17SG 0x0010
608
609 /*
610 * Some adapter firmware does not support 64 bit scsi passthrough
611 * commands.
612 */
613 #define AAC_QUIRK_SCSI_32 0x0020
614
615 /*
616 * The adapter interface specs all queues to be located in the same
617 * physically contiguous block. The host structure that defines the
618 * commuication queues will assume they are each a separate physically
619 * contiguous memory region that will support them all being one big
620 * contiguous block.
621 * There is a command and response queue for each level and direction of
622 * commuication. These regions are accessed by both the host and adapter.
623 */
624
625 struct aac_queue {
626 u64 logical; /*address we give the adapter */
627 struct aac_entry *base; /*system virtual address */
628 struct aac_qhdr headers; /*producer,consumer q headers*/
629 u32 entries; /*Number of queue entries */
630 wait_queue_head_t qfull; /*Event to wait on if q full */
631 wait_queue_head_t cmdready; /*Cmd ready from the adapter */
632 /* This is only valid for adapter to host command queues. */
633 spinlock_t *lock; /* Spinlock for this queue must take this lock before accessing the lock */
634 spinlock_t lockdata; /* Actual lock (used only on one side of the lock) */
635 struct list_head cmdq; /* A queue of FIBs which need to be prcessed by the FS thread. This is */
636 /* only valid for command queues which receive entries from the adapter. */
637 /* Number of entries on outstanding queue. */
638 atomic_t numpending;
639 struct aac_dev * dev; /* Back pointer to adapter structure */
640 };
641
642 /*
643 * Message queues. The order here is important, see also the
644 * queue type ordering
645 */
646
647 struct aac_queue_block
648 {
649 struct aac_queue queue[8];
650 };
651
652 /*
653 * SaP1 Message Unit Registers
654 */
655
656 struct sa_drawbridge_CSR {
657 /* Offset | Name */
658 __le32 reserved[10]; /* 00h-27h | Reserved */
659 u8 LUT_Offset; /* 28h | Lookup Table Offset */
660 u8 reserved1[3]; /* 29h-2bh | Reserved */
661 __le32 LUT_Data; /* 2ch | Looup Table Data */
662 __le32 reserved2[26]; /* 30h-97h | Reserved */
663 __le16 PRICLEARIRQ; /* 98h | Primary Clear Irq */
664 __le16 SECCLEARIRQ; /* 9ah | Secondary Clear Irq */
665 __le16 PRISETIRQ; /* 9ch | Primary Set Irq */
666 __le16 SECSETIRQ; /* 9eh | Secondary Set Irq */
667 __le16 PRICLEARIRQMASK;/* a0h | Primary Clear Irq Mask */
668 __le16 SECCLEARIRQMASK;/* a2h | Secondary Clear Irq Mask */
669 __le16 PRISETIRQMASK; /* a4h | Primary Set Irq Mask */
670 __le16 SECSETIRQMASK; /* a6h | Secondary Set Irq Mask */
671 __le32 MAILBOX0; /* a8h | Scratchpad 0 */
672 __le32 MAILBOX1; /* ach | Scratchpad 1 */
673 __le32 MAILBOX2; /* b0h | Scratchpad 2 */
674 __le32 MAILBOX3; /* b4h | Scratchpad 3 */
675 __le32 MAILBOX4; /* b8h | Scratchpad 4 */
676 __le32 MAILBOX5; /* bch | Scratchpad 5 */
677 __le32 MAILBOX6; /* c0h | Scratchpad 6 */
678 __le32 MAILBOX7; /* c4h | Scratchpad 7 */
679 __le32 ROM_Setup_Data; /* c8h | Rom Setup and Data */
680 __le32 ROM_Control_Addr;/* cch | Rom Control and Address */
681 __le32 reserved3[12]; /* d0h-ffh | reserved */
682 __le32 LUT[64]; /* 100h-1ffh | Lookup Table Entries */
683 };
684
685 #define Mailbox0 SaDbCSR.MAILBOX0
686 #define Mailbox1 SaDbCSR.MAILBOX1
687 #define Mailbox2 SaDbCSR.MAILBOX2
688 #define Mailbox3 SaDbCSR.MAILBOX3
689 #define Mailbox4 SaDbCSR.MAILBOX4
690 #define Mailbox5 SaDbCSR.MAILBOX5
691 #define Mailbox6 SaDbCSR.MAILBOX6
692 #define Mailbox7 SaDbCSR.MAILBOX7
693
694 #define DoorbellReg_p SaDbCSR.PRISETIRQ
695 #define DoorbellReg_s SaDbCSR.SECSETIRQ
696 #define DoorbellClrReg_p SaDbCSR.PRICLEARIRQ
697
698
699 #define DOORBELL_0 0x0001
700 #define DOORBELL_1 0x0002
701 #define DOORBELL_2 0x0004
702 #define DOORBELL_3 0x0008
703 #define DOORBELL_4 0x0010
704 #define DOORBELL_5 0x0020
705 #define DOORBELL_6 0x0040
706
707
708 #define PrintfReady DOORBELL_5
709 #define PrintfDone DOORBELL_5
710
711 struct sa_registers {
712 struct sa_drawbridge_CSR SaDbCSR; /* 98h - c4h */
713 };
714
715
716 #define Sa_MINIPORT_REVISION 1
717
718 #define sa_readw(AEP, CSR) readl(&((AEP)->regs.sa->CSR))
719 #define sa_readl(AEP, CSR) readl(&((AEP)->regs.sa->CSR))
720 #define sa_writew(AEP, CSR, value) writew(value, &((AEP)->regs.sa->CSR))
721 #define sa_writel(AEP, CSR, value) writel(value, &((AEP)->regs.sa->CSR))
722
723 /*
724 * Rx Message Unit Registers
725 */
726
727 struct rx_mu_registers {
728 /* Local | PCI*| Name */
729 __le32 ARSR; /* 1300h | 00h | APIC Register Select Register */
730 __le32 reserved0; /* 1304h | 04h | Reserved */
731 __le32 AWR; /* 1308h | 08h | APIC Window Register */
732 __le32 reserved1; /* 130Ch | 0Ch | Reserved */
733 __le32 IMRx[2]; /* 1310h | 10h | Inbound Message Registers */
734 __le32 OMRx[2]; /* 1318h | 18h | Outbound Message Registers */
735 __le32 IDR; /* 1320h | 20h | Inbound Doorbell Register */
736 __le32 IISR; /* 1324h | 24h | Inbound Interrupt
737 Status Register */
738 __le32 IIMR; /* 1328h | 28h | Inbound Interrupt
739 Mask Register */
740 __le32 ODR; /* 132Ch | 2Ch | Outbound Doorbell Register */
741 __le32 OISR; /* 1330h | 30h | Outbound Interrupt
742 Status Register */
743 __le32 OIMR; /* 1334h | 34h | Outbound Interrupt
744 Mask Register */
745 __le32 reserved2; /* 1338h | 38h | Reserved */
746 __le32 reserved3; /* 133Ch | 3Ch | Reserved */
747 __le32 InboundQueue;/* 1340h | 40h | Inbound Queue Port relative to firmware */
748 __le32 OutboundQueue;/*1344h | 44h | Outbound Queue Port relative to firmware */
749 /* * Must access through ATU Inbound
750 Translation Window */
751 };
752
753 struct rx_inbound {
754 __le32 Mailbox[8];
755 };
756
757 #define INBOUNDDOORBELL_0 0x00000001
758 #define INBOUNDDOORBELL_1 0x00000002
759 #define INBOUNDDOORBELL_2 0x00000004
760 #define INBOUNDDOORBELL_3 0x00000008
761 #define INBOUNDDOORBELL_4 0x00000010
762 #define INBOUNDDOORBELL_5 0x00000020
763 #define INBOUNDDOORBELL_6 0x00000040
764
765 #define OUTBOUNDDOORBELL_0 0x00000001
766 #define OUTBOUNDDOORBELL_1 0x00000002
767 #define OUTBOUNDDOORBELL_2 0x00000004
768 #define OUTBOUNDDOORBELL_3 0x00000008
769 #define OUTBOUNDDOORBELL_4 0x00000010
770
771 #define InboundDoorbellReg MUnit.IDR
772 #define OutboundDoorbellReg MUnit.ODR
773
774 struct rx_registers {
775 struct rx_mu_registers MUnit; /* 1300h - 1347h */
776 __le32 reserved1[2]; /* 1348h - 134ch */
777 struct rx_inbound IndexRegs;
778 };
779
780 #define rx_readb(AEP, CSR) readb(&((AEP)->regs.rx->CSR))
781 #define rx_readl(AEP, CSR) readl(&((AEP)->regs.rx->CSR))
782 #define rx_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rx->CSR))
783 #define rx_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rx->CSR))
784
785 /*
786 * Rkt Message Unit Registers (same as Rx, except a larger reserve region)
787 */
788
789 #define rkt_mu_registers rx_mu_registers
790 #define rkt_inbound rx_inbound
791
792 struct rkt_registers {
793 struct rkt_mu_registers MUnit; /* 1300h - 1347h */
794 __le32 reserved1[1006]; /* 1348h - 22fch */
795 struct rkt_inbound IndexRegs; /* 2300h - */
796 };
797
798 #define rkt_readb(AEP, CSR) readb(&((AEP)->regs.rkt->CSR))
799 #define rkt_readl(AEP, CSR) readl(&((AEP)->regs.rkt->CSR))
800 #define rkt_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rkt->CSR))
801 #define rkt_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rkt->CSR))
802
803 /*
804 * PMC SRC message unit registers
805 */
806
807 #define src_inbound rx_inbound
808
809 struct src_mu_registers {
810 /* PCI*| Name */
811 __le32 reserved0[6]; /* 00h | Reserved */
812 __le32 IOAR[2]; /* 18h | IOA->host interrupt register */
813 __le32 IDR; /* 20h | Inbound Doorbell Register */
814 __le32 IISR; /* 24h | Inbound Int. Status Register */
815 __le32 reserved1[3]; /* 28h | Reserved */
816 __le32 OIMR; /* 34h | Outbound Int. Mask Register */
817 __le32 reserved2[25]; /* 38h | Reserved */
818 __le32 ODR_R; /* 9ch | Outbound Doorbell Read */
819 __le32 ODR_C; /* a0h | Outbound Doorbell Clear */
820 __le32 reserved3[6]; /* a4h | Reserved */
821 __le32 OMR; /* bch | Outbound Message Register */
822 __le32 IQ_L; /* c0h | Inbound Queue (Low address) */
823 __le32 IQ_H; /* c4h | Inbound Queue (High address) */
824 __le32 ODR_MSI; /* c8h | MSI register for sync./AIF */
825 };
826
827 struct src_registers {
828 struct src_mu_registers MUnit; /* 00h - cbh */
829 union {
830 struct {
831 __le32 reserved1[130789]; /* cch - 7fc5fh */
832 struct src_inbound IndexRegs; /* 7fc60h */
833 } tupelo;
834 struct {
835 __le32 reserved1[973]; /* cch - fffh */
836 struct src_inbound IndexRegs; /* 1000h */
837 } denali;
838 } u;
839 };
840
841 #define src_readb(AEP, CSR) readb(&((AEP)->regs.src.bar0->CSR))
842 #define src_readl(AEP, CSR) readl(&((AEP)->regs.src.bar0->CSR))
843 #define src_writeb(AEP, CSR, value) writeb(value, \
844 &((AEP)->regs.src.bar0->CSR))
845 #define src_writel(AEP, CSR, value) writel(value, \
846 &((AEP)->regs.src.bar0->CSR))
847
848 #define SRC_ODR_SHIFT 12
849 #define SRC_IDR_SHIFT 9
850
851 typedef void (*fib_callback)(void *ctxt, struct fib *fibctx);
852
853 struct aac_fib_context {
854 s16 type; // used for verification of structure
855 s16 size;
856 u32 unique; // unique value representing this context
857 ulong jiffies; // used for cleanup - dmb changed to ulong
858 struct list_head next; // used to link context's into a linked list
859 struct semaphore wait_sem; // this is used to wait for the next fib to arrive.
860 int wait; // Set to true when thread is in WaitForSingleObject
861 unsigned long count; // total number of FIBs on FibList
862 struct list_head fib_list; // this holds fibs and their attachd hw_fibs
863 };
864
865 struct sense_data {
866 u8 error_code; /* 70h (current errors), 71h(deferred errors) */
867 u8 valid:1; /* A valid bit of one indicates that the information */
868 /* field contains valid information as defined in the
869 * SCSI-2 Standard.
870 */
871 u8 segment_number; /* Only used for COPY, COMPARE, or COPY AND VERIFY Commands */
872 u8 sense_key:4; /* Sense Key */
873 u8 reserved:1;
874 u8 ILI:1; /* Incorrect Length Indicator */
875 u8 EOM:1; /* End Of Medium - reserved for random access devices */
876 u8 filemark:1; /* Filemark - reserved for random access devices */
877
878 u8 information[4]; /* for direct-access devices, contains the unsigned
879 * logical block address or residue associated with
880 * the sense key
881 */
882 u8 add_sense_len; /* number of additional sense bytes to follow this field */
883 u8 cmnd_info[4]; /* not used */
884 u8 ASC; /* Additional Sense Code */
885 u8 ASCQ; /* Additional Sense Code Qualifier */
886 u8 FRUC; /* Field Replaceable Unit Code - not used */
887 u8 bit_ptr:3; /* indicates which byte of the CDB or parameter data
888 * was in error
889 */
890 u8 BPV:1; /* bit pointer valid (BPV): 1- indicates that
891 * the bit_ptr field has valid value
892 */
893 u8 reserved2:2;
894 u8 CD:1; /* command data bit: 1- illegal parameter in CDB.
895 * 0- illegal parameter in data.
896 */
897 u8 SKSV:1;
898 u8 field_ptr[2]; /* byte of the CDB or parameter data in error */
899 };
900
901 struct fsa_dev_info {
902 u64 last;
903 u64 size;
904 u32 type;
905 u32 config_waiting_on;
906 unsigned long config_waiting_stamp;
907 u16 queue_depth;
908 u8 config_needed;
909 u8 valid;
910 u8 ro;
911 u8 locked;
912 u8 deleted;
913 char devname[8];
914 struct sense_data sense_data;
915 u32 block_size;
916 };
917
918 struct fib {
919 void *next; /* this is used by the allocator */
920 s16 type;
921 s16 size;
922 /*
923 * The Adapter that this I/O is destined for.
924 */
925 struct aac_dev *dev;
926 /*
927 * This is the event the sendfib routine will wait on if the
928 * caller did not pass one and this is synch io.
929 */
930 struct semaphore event_wait;
931 spinlock_t event_lock;
932
933 u32 done; /* gets set to 1 when fib is complete */
934 fib_callback callback;
935 void *callback_data;
936 u32 flags; // u32 dmb was ulong
937 /*
938 * And for the internal issue/reply queues (we may be able
939 * to merge these two)
940 */
941 struct list_head fiblink;
942 void *data;
943 u32 vector_no;
944 struct hw_fib *hw_fib_va; /* Actual shared object */
945 dma_addr_t hw_fib_pa; /* physical address of hw_fib*/
946 };
947
948 /*
949 * Adapter Information Block
950 *
951 * This is returned by the RequestAdapterInfo block
952 */
953
954 struct aac_adapter_info
955 {
956 __le32 platform;
957 __le32 cpu;
958 __le32 subcpu;
959 __le32 clock;
960 __le32 execmem;
961 __le32 buffermem;
962 __le32 totalmem;
963 __le32 kernelrev;
964 __le32 kernelbuild;
965 __le32 monitorrev;
966 __le32 monitorbuild;
967 __le32 hwrev;
968 __le32 hwbuild;
969 __le32 biosrev;
970 __le32 biosbuild;
971 __le32 cluster;
972 __le32 clusterchannelmask;
973 __le32 serial[2];
974 __le32 battery;
975 __le32 options;
976 __le32 OEM;
977 };
978
979 struct aac_supplement_adapter_info
980 {
981 u8 AdapterTypeText[17+1];
982 u8 Pad[2];
983 __le32 FlashMemoryByteSize;
984 __le32 FlashImageId;
985 __le32 MaxNumberPorts;
986 __le32 Version;
987 __le32 FeatureBits;
988 u8 SlotNumber;
989 u8 ReservedPad0[3];
990 u8 BuildDate[12];
991 __le32 CurrentNumberPorts;
992 struct {
993 u8 AssemblyPn[8];
994 u8 FruPn[8];
995 u8 BatteryFruPn[8];
996 u8 EcVersionString[8];
997 u8 Tsid[12];
998 } VpdInfo;
999 __le32 FlashFirmwareRevision;
1000 __le32 FlashFirmwareBuild;
1001 __le32 RaidTypeMorphOptions;
1002 __le32 FlashFirmwareBootRevision;
1003 __le32 FlashFirmwareBootBuild;
1004 u8 MfgPcbaSerialNo[12];
1005 u8 MfgWWNName[8];
1006 __le32 SupportedOptions2;
1007 __le32 StructExpansion;
1008 /* StructExpansion == 1 */
1009 __le32 FeatureBits3;
1010 __le32 SupportedPerformanceModes;
1011 __le32 ReservedForFutureGrowth[80];
1012 };
1013 #define AAC_FEATURE_FALCON cpu_to_le32(0x00000010)
1014 #define AAC_FEATURE_JBOD cpu_to_le32(0x08000000)
1015 /* SupportedOptions2 */
1016 #define AAC_OPTION_MU_RESET cpu_to_le32(0x00000001)
1017 #define AAC_OPTION_IGNORE_RESET cpu_to_le32(0x00000002)
1018 #define AAC_OPTION_POWER_MANAGEMENT cpu_to_le32(0x00000004)
1019 #define AAC_OPTION_DOORBELL_RESET cpu_to_le32(0x00004000)
1020 /* 4KB sector size */
1021 #define AAC_OPTION_VARIABLE_BLOCK_SIZE cpu_to_le32(0x00040000)
1022 /* 240 simple volume support */
1023 #define AAC_OPTION_SUPPORTED_240_VOLUMES cpu_to_le32(0x10000000)
1024 #define AAC_SIS_VERSION_V3 3
1025 #define AAC_SIS_SLOT_UNKNOWN 0xFF
1026
1027 #define GetBusInfo 0x00000009
1028 struct aac_bus_info {
1029 __le32 Command; /* VM_Ioctl */
1030 __le32 ObjType; /* FT_DRIVE */
1031 __le32 MethodId; /* 1 = SCSI Layer */
1032 __le32 ObjectId; /* Handle */
1033 __le32 CtlCmd; /* GetBusInfo */
1034 };
1035
1036 struct aac_bus_info_response {
1037 __le32 Status; /* ST_OK */
1038 __le32 ObjType;
1039 __le32 MethodId; /* unused */
1040 __le32 ObjectId; /* unused */
1041 __le32 CtlCmd; /* unused */
1042 __le32 ProbeComplete;
1043 __le32 BusCount;
1044 __le32 TargetsPerBus;
1045 u8 InitiatorBusId[10];
1046 u8 BusValid[10];
1047 };
1048
1049 /*
1050 * Battery platforms
1051 */
1052 #define AAC_BAT_REQ_PRESENT (1)
1053 #define AAC_BAT_REQ_NOTPRESENT (2)
1054 #define AAC_BAT_OPT_PRESENT (3)
1055 #define AAC_BAT_OPT_NOTPRESENT (4)
1056 #define AAC_BAT_NOT_SUPPORTED (5)
1057 /*
1058 * cpu types
1059 */
1060 #define AAC_CPU_SIMULATOR (1)
1061 #define AAC_CPU_I960 (2)
1062 #define AAC_CPU_STRONGARM (3)
1063
1064 /*
1065 * Supported Options
1066 */
1067 #define AAC_OPT_SNAPSHOT cpu_to_le32(1)
1068 #define AAC_OPT_CLUSTERS cpu_to_le32(1<<1)
1069 #define AAC_OPT_WRITE_CACHE cpu_to_le32(1<<2)
1070 #define AAC_OPT_64BIT_DATA cpu_to_le32(1<<3)
1071 #define AAC_OPT_HOST_TIME_FIB cpu_to_le32(1<<4)
1072 #define AAC_OPT_RAID50 cpu_to_le32(1<<5)
1073 #define AAC_OPT_4GB_WINDOW cpu_to_le32(1<<6)
1074 #define AAC_OPT_SCSI_UPGRADEABLE cpu_to_le32(1<<7)
1075 #define AAC_OPT_SOFT_ERR_REPORT cpu_to_le32(1<<8)
1076 #define AAC_OPT_SUPPORTED_RECONDITION cpu_to_le32(1<<9)
1077 #define AAC_OPT_SGMAP_HOST64 cpu_to_le32(1<<10)
1078 #define AAC_OPT_ALARM cpu_to_le32(1<<11)
1079 #define AAC_OPT_NONDASD cpu_to_le32(1<<12)
1080 #define AAC_OPT_SCSI_MANAGED cpu_to_le32(1<<13)
1081 #define AAC_OPT_RAID_SCSI_MODE cpu_to_le32(1<<14)
1082 #define AAC_OPT_SUPPLEMENT_ADAPTER_INFO cpu_to_le32(1<<16)
1083 #define AAC_OPT_NEW_COMM cpu_to_le32(1<<17)
1084 #define AAC_OPT_NEW_COMM_64 cpu_to_le32(1<<18)
1085 #define AAC_OPT_NEW_COMM_TYPE1 cpu_to_le32(1<<28)
1086 #define AAC_OPT_NEW_COMM_TYPE2 cpu_to_le32(1<<29)
1087 #define AAC_OPT_NEW_COMM_TYPE3 cpu_to_le32(1<<30)
1088 #define AAC_OPT_NEW_COMM_TYPE4 cpu_to_le32(1<<31)
1089
1090 /* MSIX context */
1091 struct aac_msix_ctx {
1092 int vector_no;
1093 struct aac_dev *dev;
1094 };
1095
1096 struct aac_dev
1097 {
1098 struct list_head entry;
1099 const char *name;
1100 int id;
1101
1102 /*
1103 * negotiated FIB settings
1104 */
1105 unsigned max_fib_size;
1106 unsigned sg_tablesize;
1107 unsigned max_num_aif;
1108
1109 /*
1110 * Map for 128 fib objects (64k)
1111 */
1112 dma_addr_t hw_fib_pa;
1113 struct hw_fib *hw_fib_va;
1114 struct hw_fib *aif_base_va;
1115 /*
1116 * Fib Headers
1117 */
1118 struct fib *fibs;
1119
1120 struct fib *free_fib;
1121 spinlock_t fib_lock;
1122
1123 struct aac_queue_block *queues;
1124 /*
1125 * The user API will use an IOCTL to register itself to receive
1126 * FIBs from the adapter. The following list is used to keep
1127 * track of all the threads that have requested these FIBs. The
1128 * mutex is used to synchronize access to all data associated
1129 * with the adapter fibs.
1130 */
1131 struct list_head fib_list;
1132
1133 struct adapter_ops a_ops;
1134 unsigned long fsrev; /* Main driver's revision number */
1135
1136 resource_size_t base_start; /* main IO base */
1137 resource_size_t dbg_base; /* address of UART
1138 * debug buffer */
1139
1140 resource_size_t base_size, dbg_size; /* Size of
1141 * mapped in region */
1142
1143 struct aac_init *init; /* Holds initialization info to communicate with adapter */
1144 dma_addr_t init_pa; /* Holds physical address of the init struct */
1145
1146 u32 *host_rrq; /* response queue
1147 * if AAC_COMM_MESSAGE_TYPE1 */
1148
1149 dma_addr_t host_rrq_pa; /* phys. address */
1150 /* index into rrq buffer */
1151 u32 host_rrq_idx[AAC_MAX_MSIX];
1152 atomic_t rrq_outstanding[AAC_MAX_MSIX];
1153 u32 fibs_pushed_no;
1154 struct pci_dev *pdev; /* Our PCI interface */
1155 void * printfbuf; /* pointer to buffer used for printf's from the adapter */
1156 void * comm_addr; /* Base address of Comm area */
1157 dma_addr_t comm_phys; /* Physical Address of Comm area */
1158 size_t comm_size;
1159
1160 struct Scsi_Host *scsi_host_ptr;
1161 int maximum_num_containers;
1162 int maximum_num_physicals;
1163 int maximum_num_channels;
1164 struct fsa_dev_info *fsa_dev;
1165 struct task_struct *thread;
1166 int cardtype;
1167
1168 /*
1169 * The following is the device specific extension.
1170 */
1171 #ifndef AAC_MIN_FOOTPRINT_SIZE
1172 # define AAC_MIN_FOOTPRINT_SIZE 8192
1173 # define AAC_MIN_SRC_BAR0_SIZE 0x400000
1174 # define AAC_MIN_SRC_BAR1_SIZE 0x800
1175 # define AAC_MIN_SRCV_BAR0_SIZE 0x100000
1176 # define AAC_MIN_SRCV_BAR1_SIZE 0x400
1177 #endif
1178 union
1179 {
1180 struct sa_registers __iomem *sa;
1181 struct rx_registers __iomem *rx;
1182 struct rkt_registers __iomem *rkt;
1183 struct {
1184 struct src_registers __iomem *bar0;
1185 char __iomem *bar1;
1186 } src;
1187 } regs;
1188 volatile void __iomem *base, *dbg_base_mapped;
1189 volatile struct rx_inbound __iomem *IndexRegs;
1190 u32 OIMR; /* Mask Register Cache */
1191 /*
1192 * AIF thread states
1193 */
1194 u32 aif_thread;
1195 struct aac_adapter_info adapter_info;
1196 struct aac_supplement_adapter_info supplement_adapter_info;
1197 /* These are in adapter info but they are in the io flow so
1198 * lets break them out so we don't have to do an AND to check them
1199 */
1200 u8 nondasd_support;
1201 u8 jbod;
1202 u8 cache_protected;
1203 u8 dac_support;
1204 u8 needs_dac;
1205 u8 raid_scsi_mode;
1206 u8 comm_interface;
1207 # define AAC_COMM_PRODUCER 0
1208 # define AAC_COMM_MESSAGE 1
1209 # define AAC_COMM_MESSAGE_TYPE1 3
1210 # define AAC_COMM_MESSAGE_TYPE2 4
1211 u8 raw_io_interface;
1212 u8 raw_io_64;
1213 u8 printf_enabled;
1214 u8 in_reset;
1215 u8 msi;
1216 int management_fib_count;
1217 spinlock_t manage_lock;
1218 spinlock_t sync_lock;
1219 int sync_mode;
1220 struct fib *sync_fib;
1221 struct list_head sync_fib_list;
1222 u32 doorbell_mask;
1223 u32 max_msix; /* max. MSI-X vectors */
1224 u32 vector_cap; /* MSI-X vector capab.*/
1225 int msi_enabled; /* MSI/MSI-X enabled */
1226 struct msix_entry msixentry[AAC_MAX_MSIX];
1227 struct aac_msix_ctx aac_msix[AAC_MAX_MSIX]; /* context */
1228 u8 adapter_shutdown;
1229 };
1230
1231 #define aac_adapter_interrupt(dev) \
1232 (dev)->a_ops.adapter_interrupt(dev)
1233
1234 #define aac_adapter_notify(dev, event) \
1235 (dev)->a_ops.adapter_notify(dev, event)
1236
1237 #define aac_adapter_disable_int(dev) \
1238 (dev)->a_ops.adapter_disable_int(dev)
1239
1240 #define aac_adapter_enable_int(dev) \
1241 (dev)->a_ops.adapter_enable_int(dev)
1242
1243 #define aac_adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4) \
1244 (dev)->a_ops.adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4)
1245
1246 #define aac_adapter_check_health(dev) \
1247 (dev)->a_ops.adapter_check_health(dev)
1248
1249 #define aac_adapter_restart(dev,bled) \
1250 (dev)->a_ops.adapter_restart(dev,bled)
1251
1252 #define aac_adapter_ioremap(dev, size) \
1253 (dev)->a_ops.adapter_ioremap(dev, size)
1254
1255 #define aac_adapter_deliver(fib) \
1256 ((fib)->dev)->a_ops.adapter_deliver(fib)
1257
1258 #define aac_adapter_bounds(dev,cmd,lba) \
1259 dev->a_ops.adapter_bounds(dev,cmd,lba)
1260
1261 #define aac_adapter_read(fib,cmd,lba,count) \
1262 ((fib)->dev)->a_ops.adapter_read(fib,cmd,lba,count)
1263
1264 #define aac_adapter_write(fib,cmd,lba,count,fua) \
1265 ((fib)->dev)->a_ops.adapter_write(fib,cmd,lba,count,fua)
1266
1267 #define aac_adapter_scsi(fib,cmd) \
1268 ((fib)->dev)->a_ops.adapter_scsi(fib,cmd)
1269
1270 #define aac_adapter_comm(dev,comm) \
1271 (dev)->a_ops.adapter_comm(dev, comm)
1272
1273 #define FIB_CONTEXT_FLAG_TIMED_OUT (0x00000001)
1274 #define FIB_CONTEXT_FLAG (0x00000002)
1275 #define FIB_CONTEXT_FLAG_WAIT (0x00000004)
1276 #define FIB_CONTEXT_FLAG_FASTRESP (0x00000008)
1277
1278 /*
1279 * Define the command values
1280 */
1281
1282 #define Null 0
1283 #define GetAttributes 1
1284 #define SetAttributes 2
1285 #define Lookup 3
1286 #define ReadLink 4
1287 #define Read 5
1288 #define Write 6
1289 #define Create 7
1290 #define MakeDirectory 8
1291 #define SymbolicLink 9
1292 #define MakeNode 10
1293 #define Removex 11
1294 #define RemoveDirectoryx 12
1295 #define Rename 13
1296 #define Link 14
1297 #define ReadDirectory 15
1298 #define ReadDirectoryPlus 16
1299 #define FileSystemStatus 17
1300 #define FileSystemInfo 18
1301 #define PathConfigure 19
1302 #define Commit 20
1303 #define Mount 21
1304 #define UnMount 22
1305 #define Newfs 23
1306 #define FsCheck 24
1307 #define FsSync 25
1308 #define SimReadWrite 26
1309 #define SetFileSystemStatus 27
1310 #define BlockRead 28
1311 #define BlockWrite 29
1312 #define NvramIoctl 30
1313 #define FsSyncWait 31
1314 #define ClearArchiveBit 32
1315 #define SetAcl 33
1316 #define GetAcl 34
1317 #define AssignAcl 35
1318 #define FaultInsertion 36 /* Fault Insertion Command */
1319 #define CrazyCache 37 /* Crazycache */
1320
1321 #define MAX_FSACOMMAND_NUM 38
1322
1323
1324 /*
1325 * Define the status returns. These are very unixlike although
1326 * most are not in fact used
1327 */
1328
1329 #define ST_OK 0
1330 #define ST_PERM 1
1331 #define ST_NOENT 2
1332 #define ST_IO 5
1333 #define ST_NXIO 6
1334 #define ST_E2BIG 7
1335 #define ST_ACCES 13
1336 #define ST_EXIST 17
1337 #define ST_XDEV 18
1338 #define ST_NODEV 19
1339 #define ST_NOTDIR 20
1340 #define ST_ISDIR 21
1341 #define ST_INVAL 22
1342 #define ST_FBIG 27
1343 #define ST_NOSPC 28
1344 #define ST_ROFS 30
1345 #define ST_MLINK 31
1346 #define ST_WOULDBLOCK 35
1347 #define ST_NAMETOOLONG 63
1348 #define ST_NOTEMPTY 66
1349 #define ST_DQUOT 69
1350 #define ST_STALE 70
1351 #define ST_REMOTE 71
1352 #define ST_NOT_READY 72
1353 #define ST_BADHANDLE 10001
1354 #define ST_NOT_SYNC 10002
1355 #define ST_BAD_COOKIE 10003
1356 #define ST_NOTSUPP 10004
1357 #define ST_TOOSMALL 10005
1358 #define ST_SERVERFAULT 10006
1359 #define ST_BADTYPE 10007
1360 #define ST_JUKEBOX 10008
1361 #define ST_NOTMOUNTED 10009
1362 #define ST_MAINTMODE 10010
1363 #define ST_STALEACL 10011
1364
1365 /*
1366 * On writes how does the client want the data written.
1367 */
1368
1369 #define CACHE_CSTABLE 1
1370 #define CACHE_UNSTABLE 2
1371
1372 /*
1373 * Lets the client know at which level the data was committed on
1374 * a write request
1375 */
1376
1377 #define CMFILE_SYNCH_NVRAM 1
1378 #define CMDATA_SYNCH_NVRAM 2
1379 #define CMFILE_SYNCH 3
1380 #define CMDATA_SYNCH 4
1381 #define CMUNSTABLE 5
1382
1383 #define RIO_TYPE_WRITE 0x0000
1384 #define RIO_TYPE_READ 0x0001
1385 #define RIO_SUREWRITE 0x0008
1386
1387 #define RIO2_IO_TYPE 0x0003
1388 #define RIO2_IO_TYPE_WRITE 0x0000
1389 #define RIO2_IO_TYPE_READ 0x0001
1390 #define RIO2_IO_TYPE_VERIFY 0x0002
1391 #define RIO2_IO_ERROR 0x0004
1392 #define RIO2_IO_SUREWRITE 0x0008
1393 #define RIO2_SGL_CONFORMANT 0x0010
1394 #define RIO2_SG_FORMAT 0xF000
1395 #define RIO2_SG_FORMAT_ARC 0x0000
1396 #define RIO2_SG_FORMAT_SRL 0x1000
1397 #define RIO2_SG_FORMAT_IEEE1212 0x2000
1398
1399 struct aac_read
1400 {
1401 __le32 command;
1402 __le32 cid;
1403 __le32 block;
1404 __le32 count;
1405 struct sgmap sg; // Must be last in struct because it is variable
1406 };
1407
1408 struct aac_read64
1409 {
1410 __le32 command;
1411 __le16 cid;
1412 __le16 sector_count;
1413 __le32 block;
1414 __le16 pad;
1415 __le16 flags;
1416 struct sgmap64 sg; // Must be last in struct because it is variable
1417 };
1418
1419 struct aac_read_reply
1420 {
1421 __le32 status;
1422 __le32 count;
1423 };
1424
1425 struct aac_write
1426 {
1427 __le32 command;
1428 __le32 cid;
1429 __le32 block;
1430 __le32 count;
1431 __le32 stable; // Not used
1432 struct sgmap sg; // Must be last in struct because it is variable
1433 };
1434
1435 struct aac_write64
1436 {
1437 __le32 command;
1438 __le16 cid;
1439 __le16 sector_count;
1440 __le32 block;
1441 __le16 pad;
1442 __le16 flags;
1443 struct sgmap64 sg; // Must be last in struct because it is variable
1444 };
1445 struct aac_write_reply
1446 {
1447 __le32 status;
1448 __le32 count;
1449 __le32 committed;
1450 };
1451
1452 struct aac_raw_io
1453 {
1454 __le32 block[2];
1455 __le32 count;
1456 __le16 cid;
1457 __le16 flags; /* 00 W, 01 R */
1458 __le16 bpTotal; /* reserved for F/W use */
1459 __le16 bpComplete; /* reserved for F/W use */
1460 struct sgmapraw sg;
1461 };
1462
1463 struct aac_raw_io2 {
1464 __le32 blockLow;
1465 __le32 blockHigh;
1466 __le32 byteCount;
1467 __le16 cid;
1468 __le16 flags; /* RIO2 flags */
1469 __le32 sgeFirstSize; /* size of first sge el. */
1470 __le32 sgeNominalSize; /* size of 2nd sge el. (if conformant) */
1471 u8 sgeCnt; /* only 8 bits required */
1472 u8 bpTotal; /* reserved for F/W use */
1473 u8 bpComplete; /* reserved for F/W use */
1474 u8 sgeFirstIndex; /* reserved for F/W use */
1475 u8 unused[4];
1476 struct sge_ieee1212 sge[1];
1477 };
1478
1479 #define CT_FLUSH_CACHE 129
1480 struct aac_synchronize {
1481 __le32 command; /* VM_ContainerConfig */
1482 __le32 type; /* CT_FLUSH_CACHE */
1483 __le32 cid;
1484 __le32 parm1;
1485 __le32 parm2;
1486 __le32 parm3;
1487 __le32 parm4;
1488 __le32 count; /* sizeof(((struct aac_synchronize_reply *)NULL)->data) */
1489 };
1490
1491 struct aac_synchronize_reply {
1492 __le32 dummy0;
1493 __le32 dummy1;
1494 __le32 status; /* CT_OK */
1495 __le32 parm1;
1496 __le32 parm2;
1497 __le32 parm3;
1498 __le32 parm4;
1499 __le32 parm5;
1500 u8 data[16];
1501 };
1502
1503 #define CT_POWER_MANAGEMENT 245
1504 #define CT_PM_START_UNIT 2
1505 #define CT_PM_STOP_UNIT 3
1506 #define CT_PM_UNIT_IMMEDIATE 1
1507 struct aac_power_management {
1508 __le32 command; /* VM_ContainerConfig */
1509 __le32 type; /* CT_POWER_MANAGEMENT */
1510 __le32 sub; /* CT_PM_* */
1511 __le32 cid;
1512 __le32 parm; /* CT_PM_sub_* */
1513 };
1514
1515 #define CT_PAUSE_IO 65
1516 #define CT_RELEASE_IO 66
1517 struct aac_pause {
1518 __le32 command; /* VM_ContainerConfig */
1519 __le32 type; /* CT_PAUSE_IO */
1520 __le32 timeout; /* 10ms ticks */
1521 __le32 min;
1522 __le32 noRescan;
1523 __le32 parm3;
1524 __le32 parm4;
1525 __le32 count; /* sizeof(((struct aac_pause_reply *)NULL)->data) */
1526 };
1527
1528 struct aac_srb
1529 {
1530 __le32 function;
1531 __le32 channel;
1532 __le32 id;
1533 __le32 lun;
1534 __le32 timeout;
1535 __le32 flags;
1536 __le32 count; // Data xfer size
1537 __le32 retry_limit;
1538 __le32 cdb_size;
1539 u8 cdb[16];
1540 struct sgmap sg;
1541 };
1542
1543 /*
1544 * This and associated data structs are used by the
1545 * ioctl caller and are in cpu order.
1546 */
1547 struct user_aac_srb
1548 {
1549 u32 function;
1550 u32 channel;
1551 u32 id;
1552 u32 lun;
1553 u32 timeout;
1554 u32 flags;
1555 u32 count; // Data xfer size
1556 u32 retry_limit;
1557 u32 cdb_size;
1558 u8 cdb[16];
1559 struct user_sgmap sg;
1560 };
1561
1562 #define AAC_SENSE_BUFFERSIZE 30
1563
1564 struct aac_srb_reply
1565 {
1566 __le32 status;
1567 __le32 srb_status;
1568 __le32 scsi_status;
1569 __le32 data_xfer_length;
1570 __le32 sense_data_size;
1571 u8 sense_data[AAC_SENSE_BUFFERSIZE]; // Can this be SCSI_SENSE_BUFFERSIZE
1572 };
1573 /*
1574 * SRB Flags
1575 */
1576 #define SRB_NoDataXfer 0x0000
1577 #define SRB_DisableDisconnect 0x0004
1578 #define SRB_DisableSynchTransfer 0x0008
1579 #define SRB_BypassFrozenQueue 0x0010
1580 #define SRB_DisableAutosense 0x0020
1581 #define SRB_DataIn 0x0040
1582 #define SRB_DataOut 0x0080
1583
1584 /*
1585 * SRB Functions - set in aac_srb->function
1586 */
1587 #define SRBF_ExecuteScsi 0x0000
1588 #define SRBF_ClaimDevice 0x0001
1589 #define SRBF_IO_Control 0x0002
1590 #define SRBF_ReceiveEvent 0x0003
1591 #define SRBF_ReleaseQueue 0x0004
1592 #define SRBF_AttachDevice 0x0005
1593 #define SRBF_ReleaseDevice 0x0006
1594 #define SRBF_Shutdown 0x0007
1595 #define SRBF_Flush 0x0008
1596 #define SRBF_AbortCommand 0x0010
1597 #define SRBF_ReleaseRecovery 0x0011
1598 #define SRBF_ResetBus 0x0012
1599 #define SRBF_ResetDevice 0x0013
1600 #define SRBF_TerminateIO 0x0014
1601 #define SRBF_FlushQueue 0x0015
1602 #define SRBF_RemoveDevice 0x0016
1603 #define SRBF_DomainValidation 0x0017
1604
1605 /*
1606 * SRB SCSI Status - set in aac_srb->scsi_status
1607 */
1608 #define SRB_STATUS_PENDING 0x00
1609 #define SRB_STATUS_SUCCESS 0x01
1610 #define SRB_STATUS_ABORTED 0x02
1611 #define SRB_STATUS_ABORT_FAILED 0x03
1612 #define SRB_STATUS_ERROR 0x04
1613 #define SRB_STATUS_BUSY 0x05
1614 #define SRB_STATUS_INVALID_REQUEST 0x06
1615 #define SRB_STATUS_INVALID_PATH_ID 0x07
1616 #define SRB_STATUS_NO_DEVICE 0x08
1617 #define SRB_STATUS_TIMEOUT 0x09
1618 #define SRB_STATUS_SELECTION_TIMEOUT 0x0A
1619 #define SRB_STATUS_COMMAND_TIMEOUT 0x0B
1620 #define SRB_STATUS_MESSAGE_REJECTED 0x0D
1621 #define SRB_STATUS_BUS_RESET 0x0E
1622 #define SRB_STATUS_PARITY_ERROR 0x0F
1623 #define SRB_STATUS_REQUEST_SENSE_FAILED 0x10
1624 #define SRB_STATUS_NO_HBA 0x11
1625 #define SRB_STATUS_DATA_OVERRUN 0x12
1626 #define SRB_STATUS_UNEXPECTED_BUS_FREE 0x13
1627 #define SRB_STATUS_PHASE_SEQUENCE_FAILURE 0x14
1628 #define SRB_STATUS_BAD_SRB_BLOCK_LENGTH 0x15
1629 #define SRB_STATUS_REQUEST_FLUSHED 0x16
1630 #define SRB_STATUS_DELAYED_RETRY 0x17
1631 #define SRB_STATUS_INVALID_LUN 0x20
1632 #define SRB_STATUS_INVALID_TARGET_ID 0x21
1633 #define SRB_STATUS_BAD_FUNCTION 0x22
1634 #define SRB_STATUS_ERROR_RECOVERY 0x23
1635 #define SRB_STATUS_NOT_STARTED 0x24
1636 #define SRB_STATUS_NOT_IN_USE 0x30
1637 #define SRB_STATUS_FORCE_ABORT 0x31
1638 #define SRB_STATUS_DOMAIN_VALIDATION_FAIL 0x32
1639
1640 /*
1641 * Object-Server / Volume-Manager Dispatch Classes
1642 */
1643
1644 #define VM_Null 0
1645 #define VM_NameServe 1
1646 #define VM_ContainerConfig 2
1647 #define VM_Ioctl 3
1648 #define VM_FilesystemIoctl 4
1649 #define VM_CloseAll 5
1650 #define VM_CtBlockRead 6
1651 #define VM_CtBlockWrite 7
1652 #define VM_SliceBlockRead 8 /* raw access to configured "storage objects" */
1653 #define VM_SliceBlockWrite 9
1654 #define VM_DriveBlockRead 10 /* raw access to physical devices */
1655 #define VM_DriveBlockWrite 11
1656 #define VM_EnclosureMgt 12 /* enclosure management */
1657 #define VM_Unused 13 /* used to be diskset management */
1658 #define VM_CtBlockVerify 14
1659 #define VM_CtPerf 15 /* performance test */
1660 #define VM_CtBlockRead64 16
1661 #define VM_CtBlockWrite64 17
1662 #define VM_CtBlockVerify64 18
1663 #define VM_CtHostRead64 19
1664 #define VM_CtHostWrite64 20
1665 #define VM_DrvErrTblLog 21
1666 #define VM_NameServe64 22
1667 #define VM_NameServeAllBlk 30
1668
1669 #define MAX_VMCOMMAND_NUM 23 /* used for sizing stats array - leave last */
1670
1671 /*
1672 * Descriptive information (eg, vital stats)
1673 * that a content manager might report. The
1674 * FileArray filesystem component is one example
1675 * of a content manager. Raw mode might be
1676 * another.
1677 */
1678
1679 struct aac_fsinfo {
1680 __le32 fsTotalSize; /* Consumed by fs, incl. metadata */
1681 __le32 fsBlockSize;
1682 __le32 fsFragSize;
1683 __le32 fsMaxExtendSize;
1684 __le32 fsSpaceUnits;
1685 __le32 fsMaxNumFiles;
1686 __le32 fsNumFreeFiles;
1687 __le32 fsInodeDensity;
1688 }; /* valid iff ObjType == FT_FILESYS && !(ContentState & FSCS_NOTCLEAN) */
1689
1690 struct aac_blockdevinfo {
1691 __le32 block_size;
1692 };
1693
1694 union aac_contentinfo {
1695 struct aac_fsinfo filesys;
1696 struct aac_blockdevinfo bdevinfo;
1697 };
1698
1699 /*
1700 * Query for Container Configuration Status
1701 */
1702
1703 #define CT_GET_CONFIG_STATUS 147
1704 struct aac_get_config_status {
1705 __le32 command; /* VM_ContainerConfig */
1706 __le32 type; /* CT_GET_CONFIG_STATUS */
1707 __le32 parm1;
1708 __le32 parm2;
1709 __le32 parm3;
1710 __le32 parm4;
1711 __le32 parm5;
1712 __le32 count; /* sizeof(((struct aac_get_config_status_resp *)NULL)->data) */
1713 };
1714
1715 #define CFACT_CONTINUE 0
1716 #define CFACT_PAUSE 1
1717 #define CFACT_ABORT 2
1718 struct aac_get_config_status_resp {
1719 __le32 response; /* ST_OK */
1720 __le32 dummy0;
1721 __le32 status; /* CT_OK */
1722 __le32 parm1;
1723 __le32 parm2;
1724 __le32 parm3;
1725 __le32 parm4;
1726 __le32 parm5;
1727 struct {
1728 __le32 action; /* CFACT_CONTINUE, CFACT_PAUSE or CFACT_ABORT */
1729 __le16 flags;
1730 __le16 count;
1731 } data;
1732 };
1733
1734 /*
1735 * Accept the configuration as-is
1736 */
1737
1738 #define CT_COMMIT_CONFIG 152
1739
1740 struct aac_commit_config {
1741 __le32 command; /* VM_ContainerConfig */
1742 __le32 type; /* CT_COMMIT_CONFIG */
1743 };
1744
1745 /*
1746 * Query for Container Configuration Status
1747 */
1748
1749 #define CT_GET_CONTAINER_COUNT 4
1750 struct aac_get_container_count {
1751 __le32 command; /* VM_ContainerConfig */
1752 __le32 type; /* CT_GET_CONTAINER_COUNT */
1753 };
1754
1755 struct aac_get_container_count_resp {
1756 __le32 response; /* ST_OK */
1757 __le32 dummy0;
1758 __le32 MaxContainers;
1759 __le32 ContainerSwitchEntries;
1760 __le32 MaxPartitions;
1761 __le32 MaxSimpleVolumes;
1762 };
1763
1764
1765 /*
1766 * Query for "mountable" objects, ie, objects that are typically
1767 * associated with a drive letter on the client (host) side.
1768 */
1769
1770 struct aac_mntent {
1771 __le32 oid;
1772 u8 name[16]; /* if applicable */
1773 struct creation_info create_info; /* if applicable */
1774 __le32 capacity;
1775 __le32 vol; /* substrate structure */
1776 __le32 obj; /* FT_FILESYS, etc. */
1777 __le32 state; /* unready for mounting,
1778 readonly, etc. */
1779 union aac_contentinfo fileinfo; /* Info specific to content
1780 manager (eg, filesystem) */
1781 __le32 altoid; /* != oid <==> snapshot or
1782 broken mirror exists */
1783 __le32 capacityhigh;
1784 };
1785
1786 #define FSCS_NOTCLEAN 0x0001 /* fsck is necessary before mounting */
1787 #define FSCS_READONLY 0x0002 /* possible result of broken mirror */
1788 #define FSCS_HIDDEN 0x0004 /* should be ignored - set during a clear */
1789 #define FSCS_NOT_READY 0x0008 /* Array spinning up to fulfil request */
1790
1791 struct aac_query_mount {
1792 __le32 command;
1793 __le32 type;
1794 __le32 count;
1795 };
1796
1797 struct aac_mount {
1798 __le32 status;
1799 __le32 type; /* should be same as that requested */
1800 __le32 count;
1801 struct aac_mntent mnt[1];
1802 };
1803
1804 #define CT_READ_NAME 130
1805 struct aac_get_name {
1806 __le32 command; /* VM_ContainerConfig */
1807 __le32 type; /* CT_READ_NAME */
1808 __le32 cid;
1809 __le32 parm1;
1810 __le32 parm2;
1811 __le32 parm3;
1812 __le32 parm4;
1813 __le32 count; /* sizeof(((struct aac_get_name_resp *)NULL)->data) */
1814 };
1815
1816 struct aac_get_name_resp {
1817 __le32 dummy0;
1818 __le32 dummy1;
1819 __le32 status; /* CT_OK */
1820 __le32 parm1;
1821 __le32 parm2;
1822 __le32 parm3;
1823 __le32 parm4;
1824 __le32 parm5;
1825 u8 data[16];
1826 };
1827
1828 #define CT_CID_TO_32BITS_UID 165
1829 struct aac_get_serial {
1830 __le32 command; /* VM_ContainerConfig */
1831 __le32 type; /* CT_CID_TO_32BITS_UID */
1832 __le32 cid;
1833 };
1834
1835 struct aac_get_serial_resp {
1836 __le32 dummy0;
1837 __le32 dummy1;
1838 __le32 status; /* CT_OK */
1839 __le32 uid;
1840 };
1841
1842 /*
1843 * The following command is sent to shut down each container.
1844 */
1845
1846 struct aac_close {
1847 __le32 command;
1848 __le32 cid;
1849 };
1850
1851 struct aac_query_disk
1852 {
1853 s32 cnum;
1854 s32 bus;
1855 s32 id;
1856 s32 lun;
1857 u32 valid;
1858 u32 locked;
1859 u32 deleted;
1860 s32 instance;
1861 s8 name[10];
1862 u32 unmapped;
1863 };
1864
1865 struct aac_delete_disk {
1866 u32 disknum;
1867 u32 cnum;
1868 };
1869
1870 struct fib_ioctl
1871 {
1872 u32 fibctx;
1873 s32 wait;
1874 char __user *fib;
1875 };
1876
1877 struct revision
1878 {
1879 u32 compat;
1880 __le32 version;
1881 __le32 build;
1882 };
1883
1884
1885 /*
1886 * Ugly - non Linux like ioctl coding for back compat.
1887 */
1888
1889 #define CTL_CODE(function, method) ( \
1890 (4<< 16) | ((function) << 2) | (method) \
1891 )
1892
1893 /*
1894 * Define the method codes for how buffers are passed for I/O and FS
1895 * controls
1896 */
1897
1898 #define METHOD_BUFFERED 0
1899 #define METHOD_NEITHER 3
1900
1901 /*
1902 * Filesystem ioctls
1903 */
1904
1905 #define FSACTL_SENDFIB CTL_CODE(2050, METHOD_BUFFERED)
1906 #define FSACTL_SEND_RAW_SRB CTL_CODE(2067, METHOD_BUFFERED)
1907 #define FSACTL_DELETE_DISK 0x163
1908 #define FSACTL_QUERY_DISK 0x173
1909 #define FSACTL_OPEN_GET_ADAPTER_FIB CTL_CODE(2100, METHOD_BUFFERED)
1910 #define FSACTL_GET_NEXT_ADAPTER_FIB CTL_CODE(2101, METHOD_BUFFERED)
1911 #define FSACTL_CLOSE_GET_ADAPTER_FIB CTL_CODE(2102, METHOD_BUFFERED)
1912 #define FSACTL_MINIPORT_REV_CHECK CTL_CODE(2107, METHOD_BUFFERED)
1913 #define FSACTL_GET_PCI_INFO CTL_CODE(2119, METHOD_BUFFERED)
1914 #define FSACTL_FORCE_DELETE_DISK CTL_CODE(2120, METHOD_NEITHER)
1915 #define FSACTL_GET_CONTAINERS 2131
1916 #define FSACTL_SEND_LARGE_FIB CTL_CODE(2138, METHOD_BUFFERED)
1917
1918
1919 struct aac_common
1920 {
1921 /*
1922 * If this value is set to 1 then interrupt moderation will occur
1923 * in the base commuication support.
1924 */
1925 u32 irq_mod;
1926 u32 peak_fibs;
1927 u32 zero_fibs;
1928 u32 fib_timeouts;
1929 /*
1930 * Statistical counters in debug mode
1931 */
1932 #ifdef DBG
1933 u32 FibsSent;
1934 u32 FibRecved;
1935 u32 NoResponseSent;
1936 u32 NoResponseRecved;
1937 u32 AsyncSent;
1938 u32 AsyncRecved;
1939 u32 NormalSent;
1940 u32 NormalRecved;
1941 #endif
1942 };
1943
1944 extern struct aac_common aac_config;
1945
1946
1947 /*
1948 * The following macro is used when sending and receiving FIBs. It is
1949 * only used for debugging.
1950 */
1951
1952 #ifdef DBG
1953 #define FIB_COUNTER_INCREMENT(counter) (counter)++
1954 #else
1955 #define FIB_COUNTER_INCREMENT(counter)
1956 #endif
1957
1958 /*
1959 * Adapter direct commands
1960 * Monitor/Kernel API
1961 */
1962
1963 #define BREAKPOINT_REQUEST 0x00000004
1964 #define INIT_STRUCT_BASE_ADDRESS 0x00000005
1965 #define READ_PERMANENT_PARAMETERS 0x0000000a
1966 #define WRITE_PERMANENT_PARAMETERS 0x0000000b
1967 #define HOST_CRASHING 0x0000000d
1968 #define SEND_SYNCHRONOUS_FIB 0x0000000c
1969 #define COMMAND_POST_RESULTS 0x00000014
1970 #define GET_ADAPTER_PROPERTIES 0x00000019
1971 #define GET_DRIVER_BUFFER_PROPERTIES 0x00000023
1972 #define RCV_TEMP_READINGS 0x00000025
1973 #define GET_COMM_PREFERRED_SETTINGS 0x00000026
1974 #define IOP_RESET 0x00001000
1975 #define IOP_RESET_ALWAYS 0x00001001
1976 #define RE_INIT_ADAPTER 0x000000ee
1977
1978 /*
1979 * Adapter Status Register
1980 *
1981 * Phase Staus mailbox is 32bits:
1982 * <31:16> = Phase Status
1983 * <15:0> = Phase
1984 *
1985 * The adapter reports is present state through the phase. Only
1986 * a single phase should be ever be set. Each phase can have multiple
1987 * phase status bits to provide more detailed information about the
1988 * state of the board. Care should be taken to ensure that any phase
1989 * status bits that are set when changing the phase are also valid
1990 * for the new phase or be cleared out. Adapter software (monitor,
1991 * iflash, kernel) is responsible for properly maintining the phase
1992 * status mailbox when it is running.
1993 *
1994 * MONKER_API Phases
1995 *
1996 * Phases are bit oriented. It is NOT valid to have multiple bits set
1997 */
1998
1999 #define SELF_TEST_FAILED 0x00000004
2000 #define MONITOR_PANIC 0x00000020
2001 #define KERNEL_UP_AND_RUNNING 0x00000080
2002 #define KERNEL_PANIC 0x00000100
2003 #define FLASH_UPD_PENDING 0x00002000
2004 #define FLASH_UPD_SUCCESS 0x00004000
2005 #define FLASH_UPD_FAILED 0x00008000
2006 #define FWUPD_TIMEOUT (5 * 60)
2007
2008 /*
2009 * Doorbell bit defines
2010 */
2011
2012 #define DoorBellSyncCmdAvailable (1<<0) /* Host -> Adapter */
2013 #define DoorBellPrintfDone (1<<5) /* Host -> Adapter */
2014 #define DoorBellAdapterNormCmdReady (1<<1) /* Adapter -> Host */
2015 #define DoorBellAdapterNormRespReady (1<<2) /* Adapter -> Host */
2016 #define DoorBellAdapterNormCmdNotFull (1<<3) /* Adapter -> Host */
2017 #define DoorBellAdapterNormRespNotFull (1<<4) /* Adapter -> Host */
2018 #define DoorBellPrintfReady (1<<5) /* Adapter -> Host */
2019 #define DoorBellAifPending (1<<6) /* Adapter -> Host */
2020
2021 /* PMC specific outbound doorbell bits */
2022 #define PmDoorBellResponseSent (1<<1) /* Adapter -> Host */
2023
2024 /*
2025 * For FIB communication, we need all of the following things
2026 * to send back to the user.
2027 */
2028
2029 #define AifCmdEventNotify 1 /* Notify of event */
2030 #define AifEnConfigChange 3 /* Adapter configuration change */
2031 #define AifEnContainerChange 4 /* Container configuration change */
2032 #define AifEnDeviceFailure 5 /* SCSI device failed */
2033 #define AifEnEnclosureManagement 13 /* EM_DRIVE_* */
2034 #define EM_DRIVE_INSERTION 31
2035 #define EM_DRIVE_REMOVAL 32
2036 #define EM_SES_DRIVE_INSERTION 33
2037 #define EM_SES_DRIVE_REMOVAL 26
2038 #define AifEnBatteryEvent 14 /* Change in Battery State */
2039 #define AifEnAddContainer 15 /* A new array was created */
2040 #define AifEnDeleteContainer 16 /* A container was deleted */
2041 #define AifEnExpEvent 23 /* Firmware Event Log */
2042 #define AifExeFirmwarePanic 3 /* Firmware Event Panic */
2043 #define AifHighPriority 3 /* Highest Priority Event */
2044 #define AifEnAddJBOD 30 /* JBOD created */
2045 #define AifEnDeleteJBOD 31 /* JBOD deleted */
2046
2047 #define AifCmdJobProgress 2 /* Progress report */
2048 #define AifJobCtrZero 101 /* Array Zero progress */
2049 #define AifJobStsSuccess 1 /* Job completes */
2050 #define AifJobStsRunning 102 /* Job running */
2051 #define AifCmdAPIReport 3 /* Report from other user of API */
2052 #define AifCmdDriverNotify 4 /* Notify host driver of event */
2053 #define AifDenMorphComplete 200 /* A morph operation completed */
2054 #define AifDenVolumeExtendComplete 201 /* A volume extend completed */
2055 #define AifReqJobList 100 /* Gets back complete job list */
2056 #define AifReqJobsForCtr 101 /* Gets back jobs for specific container */
2057 #define AifReqJobsForScsi 102 /* Gets back jobs for specific SCSI device */
2058 #define AifReqJobReport 103 /* Gets back a specific job report or list of them */
2059 #define AifReqTerminateJob 104 /* Terminates job */
2060 #define AifReqSuspendJob 105 /* Suspends a job */
2061 #define AifReqResumeJob 106 /* Resumes a job */
2062 #define AifReqSendAPIReport 107 /* API generic report requests */
2063 #define AifReqAPIJobStart 108 /* Start a job from the API */
2064 #define AifReqAPIJobUpdate 109 /* Update a job report from the API */
2065 #define AifReqAPIJobFinish 110 /* Finish a job from the API */
2066
2067 /* PMC NEW COMM: Request the event data */
2068 #define AifReqEvent 200
2069
2070 /* RAW device deleted */
2071 #define AifRawDeviceRemove 203
2072
2073 /*
2074 * Adapter Initiated FIB command structures. Start with the adapter
2075 * initiated FIBs that really come from the adapter, and get responded
2076 * to by the host.
2077 */
2078
2079 struct aac_aifcmd {
2080 __le32 command; /* Tell host what type of notify this is */
2081 __le32 seqnum; /* To allow ordering of reports (if necessary) */
2082 u8 data[1]; /* Undefined length (from kernel viewpoint) */
2083 };
2084
2085 /**
2086 * Convert capacity to cylinders
2087 * accounting for the fact capacity could be a 64 bit value
2088 *
2089 */
cap_to_cyls(sector_t capacity,unsigned divisor)2090 static inline unsigned int cap_to_cyls(sector_t capacity, unsigned divisor)
2091 {
2092 sector_div(capacity, divisor);
2093 return capacity;
2094 }
2095
2096 /* SCp.phase values */
2097 #define AAC_OWNER_MIDLEVEL 0x101
2098 #define AAC_OWNER_LOWLEVEL 0x102
2099 #define AAC_OWNER_ERROR_HANDLER 0x103
2100 #define AAC_OWNER_FIRMWARE 0x106
2101
2102 const char *aac_driverinfo(struct Scsi_Host *);
2103 void aac_fib_vector_assign(struct aac_dev *dev);
2104 struct fib *aac_fib_alloc(struct aac_dev *dev);
2105 int aac_fib_setup(struct aac_dev *dev);
2106 void aac_fib_map_free(struct aac_dev *dev);
2107 void aac_fib_free(struct fib * context);
2108 void aac_fib_init(struct fib * context);
2109 void aac_printf(struct aac_dev *dev, u32 val);
2110 int aac_fib_send(u16 command, struct fib * context, unsigned long size, int priority, int wait, int reply, fib_callback callback, void *ctxt);
2111 int aac_consumer_get(struct aac_dev * dev, struct aac_queue * q, struct aac_entry **entry);
2112 void aac_consumer_free(struct aac_dev * dev, struct aac_queue * q, u32 qnum);
2113 int aac_fib_complete(struct fib * context);
2114 #define fib_data(fibctx) ((void *)(fibctx)->hw_fib_va->data)
2115 struct aac_dev *aac_init_adapter(struct aac_dev *dev);
2116 void aac_src_access_devreg(struct aac_dev *dev, int mode);
2117 int aac_get_config_status(struct aac_dev *dev, int commit_flag);
2118 int aac_get_containers(struct aac_dev *dev);
2119 int aac_scsi_cmd(struct scsi_cmnd *cmd);
2120 int aac_dev_ioctl(struct aac_dev *dev, int cmd, void __user *arg);
2121 #ifndef shost_to_class
2122 #define shost_to_class(shost) &shost->shost_dev
2123 #endif
2124 ssize_t aac_get_serial_number(struct device *dev, char *buf);
2125 int aac_do_ioctl(struct aac_dev * dev, int cmd, void __user *arg);
2126 int aac_rx_init(struct aac_dev *dev);
2127 int aac_rkt_init(struct aac_dev *dev);
2128 int aac_nark_init(struct aac_dev *dev);
2129 int aac_sa_init(struct aac_dev *dev);
2130 int aac_src_init(struct aac_dev *dev);
2131 int aac_srcv_init(struct aac_dev *dev);
2132 int aac_queue_get(struct aac_dev * dev, u32 * index, u32 qid, struct hw_fib * hw_fib, int wait, struct fib * fibptr, unsigned long *nonotify);
2133 unsigned int aac_response_normal(struct aac_queue * q);
2134 unsigned int aac_command_normal(struct aac_queue * q);
2135 unsigned int aac_intr_normal(struct aac_dev *dev, u32 Index,
2136 int isAif, int isFastResponse,
2137 struct hw_fib *aif_fib);
2138 int aac_reset_adapter(struct aac_dev * dev, int forced);
2139 int aac_check_health(struct aac_dev * dev);
2140 int aac_command_thread(void *data);
2141 int aac_close_fib_context(struct aac_dev * dev, struct aac_fib_context *fibctx);
2142 int aac_fib_adapter_complete(struct fib * fibptr, unsigned short size);
2143 struct aac_driver_ident* aac_get_driver_ident(int devtype);
2144 int aac_get_adapter_info(struct aac_dev* dev);
2145 int aac_send_shutdown(struct aac_dev *dev);
2146 int aac_probe_container(struct aac_dev *dev, int cid);
2147 int _aac_rx_init(struct aac_dev *dev);
2148 int aac_rx_select_comm(struct aac_dev *dev, int comm);
2149 int aac_rx_deliver_producer(struct fib * fib);
2150 char * get_container_type(unsigned type);
2151 extern int numacb;
2152 extern int acbsize;
2153 extern char aac_driver_version[];
2154 extern int startup_timeout;
2155 extern int aif_timeout;
2156 extern int expose_physicals;
2157 extern int aac_reset_devices;
2158 extern int aac_msi;
2159 extern int aac_commit;
2160 extern int update_interval;
2161 extern int check_interval;
2162 extern int aac_check_reset;
2163