1/*
2 * Copyright (C) 2014 Free Electrons
3 * Copyright (C) 2014 Atmel
4 *
5 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program.  If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include <linux/clk.h>
21#include <linux/delay.h>
22#include <linux/mfd/atmel-hlcdc.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/pwm.h>
26#include <linux/regmap.h>
27
28#define ATMEL_HLCDC_PWMCVAL_MASK	GENMASK(15, 8)
29#define ATMEL_HLCDC_PWMCVAL(x)		(((x) << 8) & ATMEL_HLCDC_PWMCVAL_MASK)
30#define ATMEL_HLCDC_PWMPOL		BIT(4)
31#define ATMEL_HLCDC_PWMPS_MASK		GENMASK(2, 0)
32#define ATMEL_HLCDC_PWMPS_MAX		0x6
33#define ATMEL_HLCDC_PWMPS(x)		((x) & ATMEL_HLCDC_PWMPS_MASK)
34
35struct atmel_hlcdc_pwm_errata {
36	bool slow_clk_erratum;
37	bool div1_clk_erratum;
38};
39
40struct atmel_hlcdc_pwm {
41	struct pwm_chip chip;
42	struct atmel_hlcdc *hlcdc;
43	struct clk *cur_clk;
44	const struct atmel_hlcdc_pwm_errata *errata;
45};
46
47static inline struct atmel_hlcdc_pwm *to_atmel_hlcdc_pwm(struct pwm_chip *chip)
48{
49	return container_of(chip, struct atmel_hlcdc_pwm, chip);
50}
51
52static int atmel_hlcdc_pwm_config(struct pwm_chip *c,
53				  struct pwm_device *pwm,
54				  int duty_ns, int period_ns)
55{
56	struct atmel_hlcdc_pwm *chip = to_atmel_hlcdc_pwm(c);
57	struct atmel_hlcdc *hlcdc = chip->hlcdc;
58	struct clk *new_clk = hlcdc->slow_clk;
59	u64 pwmcval = duty_ns * 256;
60	unsigned long clk_freq;
61	u64 clk_period_ns;
62	u32 pwmcfg;
63	int pres;
64
65	if (!chip->errata || !chip->errata->slow_clk_erratum) {
66		clk_freq = clk_get_rate(new_clk);
67		if (!clk_freq)
68			return -EINVAL;
69
70		clk_period_ns = (u64)NSEC_PER_SEC * 256;
71		do_div(clk_period_ns, clk_freq);
72	}
73
74	/* Errata: cannot use slow clk on some IP revisions */
75	if ((chip->errata && chip->errata->slow_clk_erratum) ||
76	    clk_period_ns > period_ns) {
77		new_clk = hlcdc->sys_clk;
78		clk_freq = clk_get_rate(new_clk);
79		if (!clk_freq)
80			return -EINVAL;
81
82		clk_period_ns = (u64)NSEC_PER_SEC * 256;
83		do_div(clk_period_ns, clk_freq);
84	}
85
86	for (pres = 0; pres <= ATMEL_HLCDC_PWMPS_MAX; pres++) {
87		/* Errata: cannot divide by 1 on some IP revisions */
88		if (!pres && chip->errata && chip->errata->div1_clk_erratum)
89			continue;
90
91		if ((clk_period_ns << pres) >= period_ns)
92			break;
93	}
94
95	if (pres > ATMEL_HLCDC_PWMPS_MAX)
96		return -EINVAL;
97
98	pwmcfg = ATMEL_HLCDC_PWMPS(pres);
99
100	if (new_clk != chip->cur_clk) {
101		u32 gencfg = 0;
102		int ret;
103
104		ret = clk_prepare_enable(new_clk);
105		if (ret)
106			return ret;
107
108		clk_disable_unprepare(chip->cur_clk);
109		chip->cur_clk = new_clk;
110
111		if (new_clk == hlcdc->sys_clk)
112			gencfg = ATMEL_HLCDC_CLKPWMSEL;
113
114		ret = regmap_update_bits(hlcdc->regmap, ATMEL_HLCDC_CFG(0),
115					 ATMEL_HLCDC_CLKPWMSEL, gencfg);
116		if (ret)
117			return ret;
118	}
119
120	do_div(pwmcval, period_ns);
121
122	/*
123	 * The PWM duty cycle is configurable from 0/256 to 255/256 of the
124	 * period cycle. Hence we can't set a duty cycle occupying the
125	 * whole period cycle if we're asked to.
126	 * Set it to 255 if pwmcval is greater than 256.
127	 */
128	if (pwmcval > 255)
129		pwmcval = 255;
130
131	pwmcfg |= ATMEL_HLCDC_PWMCVAL(pwmcval);
132
133	return regmap_update_bits(hlcdc->regmap, ATMEL_HLCDC_CFG(6),
134				  ATMEL_HLCDC_PWMCVAL_MASK |
135				  ATMEL_HLCDC_PWMPS_MASK,
136				  pwmcfg);
137}
138
139static int atmel_hlcdc_pwm_set_polarity(struct pwm_chip *c,
140					struct pwm_device *pwm,
141					enum pwm_polarity polarity)
142{
143	struct atmel_hlcdc_pwm *chip = to_atmel_hlcdc_pwm(c);
144	struct atmel_hlcdc *hlcdc = chip->hlcdc;
145	u32 cfg = 0;
146
147	if (polarity == PWM_POLARITY_NORMAL)
148		cfg = ATMEL_HLCDC_PWMPOL;
149
150	return regmap_update_bits(hlcdc->regmap, ATMEL_HLCDC_CFG(6),
151				  ATMEL_HLCDC_PWMPOL, cfg);
152}
153
154static int atmel_hlcdc_pwm_enable(struct pwm_chip *c, struct pwm_device *pwm)
155{
156	struct atmel_hlcdc_pwm *chip = to_atmel_hlcdc_pwm(c);
157	struct atmel_hlcdc *hlcdc = chip->hlcdc;
158	u32 status;
159	int ret;
160
161	ret = regmap_write(hlcdc->regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_PWM);
162	if (ret)
163		return ret;
164
165	while (true) {
166		ret = regmap_read(hlcdc->regmap, ATMEL_HLCDC_SR, &status);
167		if (ret)
168			return ret;
169
170		if ((status & ATMEL_HLCDC_PWM) != 0)
171			break;
172
173		usleep_range(1, 10);
174	}
175
176	return 0;
177}
178
179static void atmel_hlcdc_pwm_disable(struct pwm_chip *c,
180				    struct pwm_device *pwm)
181{
182	struct atmel_hlcdc_pwm *chip = to_atmel_hlcdc_pwm(c);
183	struct atmel_hlcdc *hlcdc = chip->hlcdc;
184	u32 status;
185	int ret;
186
187	ret = regmap_write(hlcdc->regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_PWM);
188	if (ret)
189		return;
190
191	while (true) {
192		ret = regmap_read(hlcdc->regmap, ATMEL_HLCDC_SR, &status);
193		if (ret)
194			return;
195
196		if ((status & ATMEL_HLCDC_PWM) == 0)
197			break;
198
199		usleep_range(1, 10);
200	}
201}
202
203static const struct pwm_ops atmel_hlcdc_pwm_ops = {
204	.config = atmel_hlcdc_pwm_config,
205	.set_polarity = atmel_hlcdc_pwm_set_polarity,
206	.enable = atmel_hlcdc_pwm_enable,
207	.disable = atmel_hlcdc_pwm_disable,
208	.owner = THIS_MODULE,
209};
210
211static const struct atmel_hlcdc_pwm_errata atmel_hlcdc_pwm_at91sam9x5_errata = {
212	.slow_clk_erratum = true,
213};
214
215static const struct atmel_hlcdc_pwm_errata atmel_hlcdc_pwm_sama5d3_errata = {
216	.div1_clk_erratum = true,
217};
218
219static const struct of_device_id atmel_hlcdc_dt_ids[] = {
220	{
221		.compatible = "atmel,at91sam9x5-hlcdc",
222		.data = &atmel_hlcdc_pwm_at91sam9x5_errata,
223	},
224	{
225		.compatible = "atmel,sama5d3-hlcdc",
226		.data = &atmel_hlcdc_pwm_sama5d3_errata,
227	},
228	{
229		.compatible = "atmel,sama5d4-hlcdc",
230		.data = &atmel_hlcdc_pwm_sama5d3_errata,
231	},
232	{ /* sentinel */ },
233};
234
235static int atmel_hlcdc_pwm_probe(struct platform_device *pdev)
236{
237	const struct of_device_id *match;
238	struct device *dev = &pdev->dev;
239	struct atmel_hlcdc_pwm *chip;
240	struct atmel_hlcdc *hlcdc;
241	int ret;
242
243	hlcdc = dev_get_drvdata(dev->parent);
244
245	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
246	if (!chip)
247		return -ENOMEM;
248
249	ret = clk_prepare_enable(hlcdc->periph_clk);
250	if (ret)
251		return ret;
252
253	match = of_match_node(atmel_hlcdc_dt_ids, dev->parent->of_node);
254	if (match)
255		chip->errata = match->data;
256
257	chip->hlcdc = hlcdc;
258	chip->chip.ops = &atmel_hlcdc_pwm_ops;
259	chip->chip.dev = dev;
260	chip->chip.base = -1;
261	chip->chip.npwm = 1;
262	chip->chip.of_xlate = of_pwm_xlate_with_flags;
263	chip->chip.of_pwm_n_cells = 3;
264	chip->chip.can_sleep = 1;
265
266	ret = pwmchip_add(&chip->chip);
267	if (ret) {
268		clk_disable_unprepare(hlcdc->periph_clk);
269		return ret;
270	}
271
272	platform_set_drvdata(pdev, chip);
273
274	return 0;
275}
276
277static int atmel_hlcdc_pwm_remove(struct platform_device *pdev)
278{
279	struct atmel_hlcdc_pwm *chip = platform_get_drvdata(pdev);
280	int ret;
281
282	ret = pwmchip_remove(&chip->chip);
283	if (ret)
284		return ret;
285
286	clk_disable_unprepare(chip->hlcdc->periph_clk);
287
288	return 0;
289}
290
291static const struct of_device_id atmel_hlcdc_pwm_dt_ids[] = {
292	{ .compatible = "atmel,hlcdc-pwm" },
293	{ /* sentinel */ },
294};
295
296static struct platform_driver atmel_hlcdc_pwm_driver = {
297	.driver = {
298		.name = "atmel-hlcdc-pwm",
299		.of_match_table = atmel_hlcdc_pwm_dt_ids,
300	},
301	.probe = atmel_hlcdc_pwm_probe,
302	.remove = atmel_hlcdc_pwm_remove,
303};
304module_platform_driver(atmel_hlcdc_pwm_driver);
305
306MODULE_ALIAS("platform:atmel-hlcdc-pwm");
307MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
308MODULE_DESCRIPTION("Atmel HLCDC PWM driver");
309MODULE_LICENSE("GPL v2");
310