1 /* 2 * r8a7791 processor support - PFC hardware block. 3 * 4 * Copyright (C) 2013 Renesas Electronics Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 8 * as published by the Free Software Foundation. 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/platform_data/gpio-rcar.h> 13 14 #include "core.h" 15 #include "sh_pfc.h" 16 17 #define CPU_ALL_PORT(fn, sfx) \ 18 PORT_GP_32(0, fn, sfx), \ 19 PORT_GP_32(1, fn, sfx), \ 20 PORT_GP_32(2, fn, sfx), \ 21 PORT_GP_32(3, fn, sfx), \ 22 PORT_GP_32(4, fn, sfx), \ 23 PORT_GP_32(5, fn, sfx), \ 24 PORT_GP_32(6, fn, sfx), \ 25 PORT_GP_32(7, fn, sfx) 26 27 enum { 28 PINMUX_RESERVED = 0, 29 30 PINMUX_DATA_BEGIN, 31 GP_ALL(DATA), 32 PINMUX_DATA_END, 33 34 PINMUX_FUNCTION_BEGIN, 35 GP_ALL(FN), 36 37 /* GPSR0 */ 38 FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5, 39 FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11, 40 FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19, 41 FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29, 42 FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8, 43 FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20, 44 45 /* GPSR1 */ 46 FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3, 47 FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16, 48 FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25, 49 FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N, 50 FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18, 51 FN_IP3_21_20, 52 53 /* GPSR2 */ 54 FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5, 55 FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19, 56 FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26, 57 FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9, 58 FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22, 59 FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0, 60 FN_IP6_5_3, FN_IP6_7_6, 61 62 /* GPSR3 */ 63 FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13, 64 FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24, 65 FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9, 66 FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24, 67 FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7, 68 FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16, 69 FN_IP9_18_17, 70 71 /* GPSR4 */ 72 FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25, 73 FN_VI0_DATA0_VI0_B0, FN_VI0_DATA1_VI0_B1, FN_VI0_DATA2_VI0_B2, 74 FN_IP9_28_27, FN_VI0_DATA4_VI0_B4, FN_VI0_DATA5_VI0_B5, 75 FN_VI0_DATA6_VI0_B6, FN_VI0_DATA7_VI0_B7, FN_IP9_31_29, FN_IP10_2_0, 76 FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15, 77 FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25, 78 FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6, 79 FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4, 80 81 /* GPSR5 */ 82 FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19, 83 FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24, 84 FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30, 85 FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10, 86 FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20, 87 FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3, 88 FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22, 89 90 /* GPSR6 */ 91 FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14, 92 FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19, 93 FN_IP13_22, FN_IP13_24_23, FN_SD1_CLK, 94 FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0, 95 FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7, 96 FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17, 97 FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29, 98 FN_USB1_OVC, FN_DU0_DOTCLKIN, 99 100 /* GPSR7 */ 101 FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24, 102 FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8, 103 FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, 104 FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27, 105 FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12, 106 FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, 107 108 /* IPSR0 */ 109 FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7, FN_D8, 110 FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15, 111 FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_SCL0_C, FN_PWM2_B, 112 FN_A1, FN_MSIOF0_SYNC_B, FN_A2, FN_MSIOF0_SS1_B, 113 FN_A3, FN_MSIOF0_SS2_B, FN_A4, FN_MSIOF0_TXD_B, 114 FN_A5, FN_MSIOF0_RXD_B, FN_A6, FN_MSIOF1_SCK, 115 116 /* IPSR1 */ 117 FN_A7, FN_MSIOF1_SYNC, FN_A8, FN_MSIOF1_SS1, FN_SCL0, 118 FN_A9, FN_MSIOF1_SS2, FN_SDA0, 119 FN_A10, FN_MSIOF1_TXD, FN_MSIOF1_TXD_D, 120 FN_A11, FN_MSIOF1_RXD, FN_SCL3_D, FN_MSIOF1_RXD_D, 121 FN_A12, FN_FMCLK, FN_SDA3_D, FN_MSIOF1_SCK_D, 122 FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D, 123 FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D, 124 FN_A15, FN_BPFCLK_C, 125 FN_A16, FN_DREQ2_B, FN_FMCLK_C, FN_SCIFA1_SCK_B, 126 FN_A17, FN_DACK2_B, FN_SDA0_C, 127 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, FN_SCIFB1_RXD_C, 128 129 /* IPSR2 */ 130 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, FN_SCIFB1_TXD_C, FN_SCIFB1_SCK_B, 131 FN_A20, FN_SPCLK, 132 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 133 FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD, 134 FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD, 135 FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD, 136 FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD, 137 FN_CS0_N, FN_ATAG0_N_B, FN_SCL1, 138 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_SDA1, 139 FN_EX_CS1_N, FN_MSIOF2_SCK, 140 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 141 FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, FN_ATAG0_N, FN_EX_WAIT1, 142 143 /* IPSR3 */ 144 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, FN_EX_WAIT2, 145 FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B, 146 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 147 FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B, 148 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 149 FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D, 150 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 151 FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B, 152 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 153 FN_DREQ0, FN_PWM3, FN_TPU_TO3, 154 FN_DACK0, FN_DRACK0, FN_REMOCON, 155 FN_SPEEDIN, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B, 156 FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D, 157 FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C, 158 FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C, 159 160 /* IPSR4 */ 161 FN_SSI_SDATA0, FN_SCL0_B, FN_SCL7_B, FN_MSIOF2_SCK_C, 162 FN_SSI_SCK1, FN_SDA0_B, FN_SDA7_B, FN_MSIOF2_SYNC_C, FN_GLO_I0_D, 163 FN_SSI_WS1, FN_SCL1_B, FN_SCL8_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D, 164 FN_SSI_SDATA1, FN_SDA1_B, FN_SDA8_B, FN_MSIOF2_RXD_C, 165 FN_SSI_SCK2, FN_SCL2, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E, 166 FN_SSI_WS2, FN_SDA2, FN_GPS_SIGN_B, FN_RX2_E, 167 FN_GLO_Q1_D, FN_HCTS1_N_E, 168 FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E, 169 FN_SSI_SCK34, FN_SSI_WS34, FN_SSI_SDATA3, 170 FN_SSI_SCK4, FN_GLO_SS_D, 171 FN_SSI_WS4, FN_GLO_RFON_D, 172 FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 173 FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0, 174 FN_MSIOF2_SYNC_D, FN_VI1_R2_B, 175 176 /* IPSR5 */ 177 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1, 178 FN_MSIOF2_TXD_D, FN_VI1_R3_B, 179 FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0, 180 FN_MSIOF2_SS1_D, FN_VI1_R4_B, 181 FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1, 182 FN_MSIOF2_RXD_D, FN_VI1_R5_B, 183 FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B, 184 FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B, 185 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 186 FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON, 187 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 188 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 189 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 190 FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D, 191 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D, 192 193 /* IPSR6 */ 194 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B, 195 FN_SCIF_CLK, FN_BPFCLK_E, 196 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2, 197 FN_SCIFA2_RXD, FN_FMIN_E, 198 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD, 199 FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 200 FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 201 FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 202 FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N, 203 FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N, 204 FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E, 205 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_SDA1_E, FN_MSIOF2_SYNC_E, 206 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D, 207 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D, 208 209 /* IPSR7 */ 210 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C, 211 FN_SCIF_CLK_B, FN_GPS_MAG_D, 212 FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B, 213 FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B, 214 FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B, 215 FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B, 216 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 217 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 218 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 219 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 220 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 221 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 222 FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B, 223 FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B, 224 FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B, 225 FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B, 226 FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B, 227 FN_SCIFA1_SCK, FN_SSI_SCK78_B, 228 229 /* IPSR8 */ 230 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, FN_SSI_WS78_B, 231 FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B, 232 FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B, 233 FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B, 234 FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B, 235 FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B, 236 FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B, 237 FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B, 238 FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B, 239 FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B, 240 FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B, 241 FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B, 242 FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B, 243 FN_SCIFA2_SCK, FN_SSI_SDATA9_B, 244 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 245 FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX, 246 FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX, 247 248 /* IPSR9 */ 249 FN_DU1_DB6, FN_LCDOUT22, FN_SCL3_C, FN_RX3, FN_SCIFA3_RXD, 250 FN_DU1_DB7, FN_LCDOUT23, FN_SDA3_C, FN_SCIF3_SCK, FN_SCIFA3_SCK, 251 FN_DU1_DOTCLKIN, FN_QSTVA_QVS, 252 FN_DU1_DOTCLKOUT0, FN_QCLK, 253 FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX, 254 FN_TX3_B, FN_SCL2_B, FN_PWM4, 255 FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS, 256 FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE, 257 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE, 258 FN_CAN0_RX, FN_RX3_B, FN_SDA2_B, 259 FN_DU1_DISP, FN_QPOLA, 260 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 261 FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D, 262 FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D, 263 FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D, 264 FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D, 265 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 266 FN_VI0_G0, FN_SCL8, FN_STP_IVCXO27_0_C, FN_SCL4, 267 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 268 269 /* IPSR10 */ 270 FN_VI0_G1, FN_SDA8, FN_STP_ISCLK_0_C, FN_SDA4, 271 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 272 FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_SCL3_B, 273 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 274 FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_SDA3_B, 275 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 276 FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C, 277 FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D, 278 FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D, 279 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 280 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 281 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 282 FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B, 283 FN_TS_SDATA0_C, FN_ATACS11_N, 284 FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, 285 FN_TS_SCK0_C, FN_ATAG1_N, 286 FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C, 287 FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C, 288 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_SCL1_D, 289 290 /* IPSR11 */ 291 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D, 292 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B, 293 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E, 294 FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 295 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B, 296 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B, 297 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 298 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 299 FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5, 300 FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7, 301 FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO, 302 FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC, 303 FN_VI1_DATA7, FN_AVB_MDC, 304 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, 305 FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, 306 307 /* IPSR12 */ 308 FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, 309 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7, 310 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C, 311 FN_SCL2_D, FN_MSIOF1_RXD_E, 312 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_SDA2_D, FN_MSIOF1_SCK_E, 313 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B, 314 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E, 315 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B, 316 FN_CAN1_TX_C, FN_MSIOF1_TXD_E, 317 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B, 318 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 319 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 320 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 321 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D, 322 FN_ADIDATA_B, FN_MSIOF0_SYNC_C, 323 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D, 324 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C, 325 326 /* IPSR13 */ 327 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C, 328 FN_ADICLK_B, FN_MSIOF0_SS1_C, 329 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C, 330 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C, 331 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B, 332 FN_ADICHS2_B, FN_MSIOF0_TXD_C, 333 FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B, 334 FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B, 335 FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B, 336 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F, 337 FN_SCIFA5_TXD_B, FN_TX3_C, 338 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F, 339 FN_SCIFA5_RXD_B, FN_RX3_C, 340 FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B, 341 FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B, 342 FN_SD1_DATA3, FN_IERX_B, 343 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C, 344 345 /* IPSR14 */ 346 FN_SD1_WP, FN_PWM1_B, FN_SDA1_C, 347 FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD, 348 FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1, 349 FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3, 350 FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C, 351 FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C, 352 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B, 353 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B, 354 FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B, 355 FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B, 356 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E, 357 FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B, 358 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E, 359 FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B, 360 361 /* IPSR15 */ 362 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 363 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 364 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 365 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B, 366 FN_PWM5_B, FN_SCIFA3_TXD_C, 367 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5, 368 FN_VI1_G6_B, FN_SCIFA3_RXD_C, 369 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6, 370 FN_VI1_G7_B, FN_SCIFA3_SCK_C, 371 FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C, 372 FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C, 373 FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK, 374 FN_TCLK2, FN_VI1_DATA3_C, 375 FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C, 376 FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C, 377 378 /* IPSR16 */ 379 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C, 380 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C, 381 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C, 382 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B, 383 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B, 384 385 /* MOD_SEL */ 386 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, 387 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3, 388 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3, 389 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, 390 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 391 FN_SEL_SSI9_0, FN_SEL_SSI9_1, 392 FN_SEL_SCFA_0, FN_SEL_SCFA_1, 393 FN_SEL_QSP_0, FN_SEL_QSP_1, 394 FN_SEL_SSI7_0, FN_SEL_SSI7_1, 395 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3, 396 FN_SEL_HSCIF1_4, 397 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 398 FN_SEL_TMU1_0, FN_SEL_TMU1_1, 399 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3, 400 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, 401 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 402 403 /* MOD_SEL2 */ 404 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, 405 FN_SEL_SCIF0_4, 406 FN_SEL_SCIF_0, FN_SEL_SCIF_1, 407 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, 408 FN_SEL_CAN0_4, FN_SEL_CAN0_5, 409 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, 410 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, 411 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 412 FN_SEL_ADG_0, FN_SEL_ADG_1, 413 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4, 414 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 415 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, 416 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 417 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 418 FN_SEL_SIM_0, FN_SEL_SIM_1, 419 FN_SEL_SSI8_0, FN_SEL_SSI8_1, 420 421 /* MOD_SEL3 */ 422 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3, 423 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3, 424 FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, 425 FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, 426 FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, 427 FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3, 428 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, 429 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 430 FN_SEL_MMC_0, FN_SEL_MMC_1, 431 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, 432 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, 433 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3, 434 FN_SEL_IIC1_4, 435 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 436 437 /* MOD_SEL4 */ 438 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3, 439 FN_SEL_SOF1_4, 440 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 441 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 442 FN_SEL_RAD_0, FN_SEL_RAD_1, 443 FN_SEL_RCN_0, FN_SEL_RCN_1, 444 FN_SEL_RSP_0, FN_SEL_RSP_1, 445 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3, 446 FN_SEL_SCIF2_4, 447 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3, 448 FN_SEL_SOF2_4, 449 FN_SEL_SSI1_0, FN_SEL_SSI1_1, 450 FN_SEL_SSI0_0, FN_SEL_SSI0_1, 451 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 452 PINMUX_FUNCTION_END, 453 454 PINMUX_MARK_BEGIN, 455 456 EX_CS0_N_MARK, RD_N_MARK, 457 458 AUDIO_CLKA_MARK, 459 460 VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, 461 VI0_DATA2_VI0_B2_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, 462 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, 463 464 SD1_CLK_MARK, 465 466 USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK, 467 DU0_DOTCLKIN_MARK, 468 469 /* IPSR0 */ 470 D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK, 471 D6_MARK, D7_MARK, D8_MARK, 472 D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK, D14_MARK, D15_MARK, 473 A0_MARK, ATAWR0_N_C_MARK, MSIOF0_SCK_B_MARK, SCL0_C_MARK, PWM2_B_MARK, 474 A1_MARK, MSIOF0_SYNC_B_MARK, A2_MARK, MSIOF0_SS1_B_MARK, 475 A3_MARK, MSIOF0_SS2_B_MARK, A4_MARK, MSIOF0_TXD_B_MARK, 476 A5_MARK, MSIOF0_RXD_B_MARK, A6_MARK, MSIOF1_SCK_MARK, 477 478 /* IPSR1 */ 479 A7_MARK, MSIOF1_SYNC_MARK, A8_MARK, MSIOF1_SS1_MARK, SCL0_MARK, 480 A9_MARK, MSIOF1_SS2_MARK, SDA0_MARK, 481 A10_MARK, MSIOF1_TXD_MARK, MSIOF1_TXD_D_MARK, 482 A11_MARK, MSIOF1_RXD_MARK, SCL3_D_MARK, MSIOF1_RXD_D_MARK, 483 A12_MARK, FMCLK_MARK, SDA3_D_MARK, MSIOF1_SCK_D_MARK, 484 A13_MARK, ATAG0_N_C_MARK, BPFCLK_MARK, MSIOF1_SS1_D_MARK, 485 A14_MARK, ATADIR0_N_C_MARK, FMIN_MARK, FMIN_C_MARK, MSIOF1_SYNC_D_MARK, 486 A15_MARK, BPFCLK_C_MARK, 487 A16_MARK, DREQ2_B_MARK, FMCLK_C_MARK, SCIFA1_SCK_B_MARK, 488 A17_MARK, DACK2_B_MARK, SDA0_C_MARK, 489 A18_MARK, DREQ1_MARK, SCIFA1_RXD_C_MARK, SCIFB1_RXD_C_MARK, 490 491 /* IPSR2 */ 492 A19_MARK, DACK1_MARK, SCIFA1_TXD_C_MARK, 493 SCIFB1_TXD_C_MARK, SCIFB1_SCK_B_MARK, 494 A20_MARK, SPCLK_MARK, 495 A21_MARK, ATAWR0_N_B_MARK, MOSI_IO0_MARK, 496 A22_MARK, MISO_IO1_MARK, FMCLK_B_MARK, TX0_MARK, SCIFA0_TXD_MARK, 497 A23_MARK, IO2_MARK, BPFCLK_B_MARK, RX0_MARK, SCIFA0_RXD_MARK, 498 A24_MARK, DREQ2_MARK, IO3_MARK, TX1_MARK, SCIFA1_TXD_MARK, 499 A25_MARK, DACK2_MARK, SSL_MARK, DREQ1_C_MARK, 500 RX1_MARK, SCIFA1_RXD_MARK, 501 CS0_N_MARK, ATAG0_N_B_MARK, SCL1_MARK, 502 CS1_N_A26_MARK, ATADIR0_N_B_MARK, SDA1_MARK, 503 EX_CS1_N_MARK, MSIOF2_SCK_MARK, 504 EX_CS2_N_MARK, ATAWR0_N_MARK, MSIOF2_SYNC_MARK, 505 EX_CS3_N_MARK, ATADIR0_N_MARK, MSIOF2_TXD_MARK, 506 ATAG0_N_MARK, EX_WAIT1_MARK, 507 508 /* IPSR3 */ 509 EX_CS4_N_MARK, ATARD0_N_MARK, MSIOF2_RXD_MARK, EX_WAIT2_MARK, 510 EX_CS5_N_MARK, ATACS00_N_MARK, MSIOF2_SS1_MARK, HRX1_B_MARK, 511 SCIFB1_RXD_B_MARK, PWM1_MARK, TPU_TO1_MARK, 512 BS_N_MARK, ATACS10_N_MARK, MSIOF2_SS2_MARK, HTX1_B_MARK, 513 SCIFB1_TXD_B_MARK, PWM2_MARK, TPU_TO2_MARK, 514 RD_WR_N_MARK, HRX2_B_MARK, FMIN_B_MARK, 515 SCIFB0_RXD_B_MARK, DREQ1_D_MARK, 516 WE0_N_MARK, HCTS2_N_B_MARK, SCIFB0_TXD_B_MARK, 517 WE1_N_MARK, ATARD0_N_B_MARK, HTX2_B_MARK, SCIFB0_RTS_N_B_MARK, 518 EX_WAIT0_MARK, HRTS2_N_B_MARK, SCIFB0_CTS_N_B_MARK, 519 DREQ0_MARK, PWM3_MARK, TPU_TO3_MARK, 520 DACK0_MARK, DRACK0_MARK, REMOCON_MARK, 521 SPEEDIN_MARK, HSCK0_C_MARK, HSCK2_C_MARK, SCIFB0_SCK_B_MARK, 522 SCIFB2_SCK_B_MARK, DREQ2_C_MARK, HTX2_D_MARK, 523 SSI_SCK0129_MARK, HRX0_C_MARK, HRX2_C_MARK, 524 SCIFB0_RXD_C_MARK, SCIFB2_RXD_C_MARK, 525 SSI_WS0129_MARK, HTX0_C_MARK, HTX2_C_MARK, 526 SCIFB0_TXD_C_MARK, SCIFB2_TXD_C_MARK, 527 528 /* IPSR4 */ 529 SSI_SDATA0_MARK, SCL0_B_MARK, SCL7_B_MARK, MSIOF2_SCK_C_MARK, 530 SSI_SCK1_MARK, SDA0_B_MARK, SDA7_B_MARK, 531 MSIOF2_SYNC_C_MARK, GLO_I0_D_MARK, 532 SSI_WS1_MARK, SCL1_B_MARK, SCL8_B_MARK, 533 MSIOF2_TXD_C_MARK, GLO_I1_D_MARK, 534 SSI_SDATA1_MARK, SDA1_B_MARK, SDA8_B_MARK, MSIOF2_RXD_C_MARK, 535 SSI_SCK2_MARK, SCL2_MARK, GPS_CLK_B_MARK, GLO_Q0_D_MARK, HSCK1_E_MARK, 536 SSI_WS2_MARK, SDA2_MARK, GPS_SIGN_B_MARK, RX2_E_MARK, 537 GLO_Q1_D_MARK, HCTS1_N_E_MARK, 538 SSI_SDATA2_MARK, GPS_MAG_B_MARK, TX2_E_MARK, HRTS1_N_E_MARK, 539 SSI_SCK34_MARK, SSI_WS34_MARK, SSI_SDATA3_MARK, 540 SSI_SCK4_MARK, GLO_SS_D_MARK, 541 SSI_WS4_MARK, GLO_RFON_D_MARK, 542 SSI_SDATA4_MARK, MSIOF2_SCK_D_MARK, 543 SSI_SCK5_MARK, MSIOF1_SCK_C_MARK, TS_SDATA0_MARK, GLO_I0_MARK, 544 MSIOF2_SYNC_D_MARK, VI1_R2_B_MARK, 545 546 /* IPSR5 */ 547 SSI_WS5_MARK, MSIOF1_SYNC_C_MARK, TS_SCK0_MARK, GLO_I1_MARK, 548 MSIOF2_TXD_D_MARK, VI1_R3_B_MARK, 549 SSI_SDATA5_MARK, MSIOF1_TXD_C_MARK, TS_SDEN0_MARK, GLO_Q0_MARK, 550 MSIOF2_SS1_D_MARK, VI1_R4_B_MARK, 551 SSI_SCK6_MARK, MSIOF1_RXD_C_MARK, TS_SPSYNC0_MARK, GLO_Q1_MARK, 552 MSIOF2_RXD_D_MARK, VI1_R5_B_MARK, 553 SSI_WS6_MARK, GLO_SCLK_MARK, MSIOF2_SS2_D_MARK, VI1_R6_B_MARK, 554 SSI_SDATA6_MARK, STP_IVCXO27_0_B_MARK, GLO_SDATA_MARK, VI1_R7_B_MARK, 555 SSI_SCK78_MARK, STP_ISCLK_0_B_MARK, GLO_SS_MARK, 556 SSI_WS78_MARK, TX0_D_MARK, STP_ISD_0_B_MARK, GLO_RFON_MARK, 557 SSI_SDATA7_MARK, RX0_D_MARK, STP_ISEN_0_B_MARK, 558 SSI_SDATA8_MARK, TX1_D_MARK, STP_ISSYNC_0_B_MARK, 559 SSI_SCK9_MARK, RX1_D_MARK, GLO_SCLK_D_MARK, 560 SSI_WS9_MARK, TX3_D_MARK, CAN0_TX_D_MARK, GLO_SDATA_D_MARK, 561 SSI_SDATA9_MARK, RX3_D_MARK, CAN0_RX_D_MARK, 562 563 /* IPSR6 */ 564 AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK, 565 SCIF_CLK_MARK, BPFCLK_E_MARK, 566 AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK, 567 SCIFA2_RXD_MARK, FMIN_E_MARK, 568 AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK, 569 IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK, 570 IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK, 571 IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK, 572 IRQ3_MARK, SCL4_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK, 573 IRQ4_MARK, HRX1_C_MARK, SDA4_C_MARK, 574 MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK, 575 IRQ5_MARK, HTX1_C_MARK, SCL1_E_MARK, MSIOF2_SCK_E_MARK, 576 IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK, 577 SDA1_E_MARK, MSIOF2_SYNC_E_MARK, 578 IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK, 579 GPS_CLK_C_MARK, GPS_CLK_D_MARK, 580 IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK, 581 GPS_SIGN_C_MARK, GPS_SIGN_D_MARK, 582 583 /* IPSR7 */ 584 IRQ9_MARK, DU1_DOTCLKIN_B_MARK, CAN_CLK_D_MARK, GPS_MAG_C_MARK, 585 SCIF_CLK_B_MARK, GPS_MAG_D_MARK, 586 DU1_DR0_MARK, LCDOUT0_MARK, VI1_DATA0_B_MARK, TX0_B_MARK, 587 SCIFA0_TXD_B_MARK, MSIOF2_SCK_B_MARK, 588 DU1_DR1_MARK, LCDOUT1_MARK, VI1_DATA1_B_MARK, RX0_B_MARK, 589 SCIFA0_RXD_B_MARK, MSIOF2_SYNC_B_MARK, 590 DU1_DR2_MARK, LCDOUT2_MARK, SSI_SCK0129_B_MARK, 591 DU1_DR3_MARK, LCDOUT3_MARK, SSI_WS0129_B_MARK, 592 DU1_DR4_MARK, LCDOUT4_MARK, SSI_SDATA0_B_MARK, 593 DU1_DR5_MARK, LCDOUT5_MARK, SSI_SCK1_B_MARK, 594 DU1_DR6_MARK, LCDOUT6_MARK, SSI_WS1_B_MARK, 595 DU1_DR7_MARK, LCDOUT7_MARK, SSI_SDATA1_B_MARK, 596 DU1_DG0_MARK, LCDOUT8_MARK, VI1_DATA2_B_MARK, TX1_B_MARK, 597 SCIFA1_TXD_B_MARK, MSIOF2_SS1_B_MARK, 598 DU1_DG1_MARK, LCDOUT9_MARK, VI1_DATA3_B_MARK, RX1_B_MARK, 599 SCIFA1_RXD_B_MARK, MSIOF2_SS2_B_MARK, 600 DU1_DG2_MARK, LCDOUT10_MARK, VI1_DATA4_B_MARK, SCIF1_SCK_B_MARK, 601 SCIFA1_SCK_MARK, SSI_SCK78_B_MARK, 602 603 /* IPSR8 */ 604 DU1_DG3_MARK, LCDOUT11_MARK, VI1_DATA5_B_MARK, SSI_WS78_B_MARK, 605 DU1_DG4_MARK, LCDOUT12_MARK, VI1_DATA6_B_MARK, HRX0_B_MARK, 606 SCIFB2_RXD_B_MARK, SSI_SDATA7_B_MARK, 607 DU1_DG5_MARK, LCDOUT13_MARK, VI1_DATA7_B_MARK, HCTS0_N_B_MARK, 608 SCIFB2_TXD_B_MARK, SSI_SDATA8_B_MARK, 609 DU1_DG6_MARK, LCDOUT14_MARK, HRTS0_N_B_MARK, 610 SCIFB2_CTS_N_B_MARK, SSI_SCK9_B_MARK, 611 DU1_DG7_MARK, LCDOUT15_MARK, HTX0_B_MARK, 612 SCIFB2_RTS_N_B_MARK, SSI_WS9_B_MARK, 613 DU1_DB0_MARK, LCDOUT16_MARK, VI1_CLK_B_MARK, TX2_B_MARK, 614 SCIFA2_TXD_B_MARK, MSIOF2_TXD_B_MARK, 615 DU1_DB1_MARK, LCDOUT17_MARK, VI1_HSYNC_N_B_MARK, RX2_B_MARK, 616 SCIFA2_RXD_B_MARK, MSIOF2_RXD_B_MARK, 617 DU1_DB2_MARK, LCDOUT18_MARK, VI1_VSYNC_N_B_MARK, SCIF2_SCK_B_MARK, 618 SCIFA2_SCK_MARK, SSI_SDATA9_B_MARK, 619 DU1_DB3_MARK, LCDOUT19_MARK, VI1_CLKENB_B_MARK, 620 DU1_DB4_MARK, LCDOUT20_MARK, VI1_FIELD_B_MARK, CAN1_RX_MARK, 621 DU1_DB5_MARK, LCDOUT21_MARK, TX3_MARK, SCIFA3_TXD_MARK, CAN1_TX_MARK, 622 623 /* IPSR9 */ 624 DU1_DB6_MARK, LCDOUT22_MARK, SCL3_C_MARK, RX3_MARK, SCIFA3_RXD_MARK, 625 DU1_DB7_MARK, LCDOUT23_MARK, SDA3_C_MARK, 626 SCIF3_SCK_MARK, SCIFA3_SCK_MARK, 627 DU1_DOTCLKIN_MARK, QSTVA_QVS_MARK, 628 DU1_DOTCLKOUT0_MARK, QCLK_MARK, 629 DU1_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, CAN0_TX_MARK, 630 TX3_B_MARK, SCL2_B_MARK, PWM4_MARK, 631 DU1_EXHSYNC_DU1_HSYNC_MARK, QSTH_QHS_MARK, 632 DU1_EXVSYNC_DU1_VSYNC_MARK, QSTB_QHE_MARK, 633 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, 634 CAN0_RX_MARK, RX3_B_MARK, SDA2_B_MARK, 635 DU1_DISP_MARK, QPOLA_MARK, 636 DU1_CDE_MARK, QPOLB_MARK, PWM4_B_MARK, 637 VI0_CLKENB_MARK, TX4_MARK, SCIFA4_TXD_MARK, TS_SDATA0_D_MARK, 638 VI0_FIELD_MARK, RX4_MARK, SCIFA4_RXD_MARK, TS_SCK0_D_MARK, 639 VI0_HSYNC_N_MARK, TX5_MARK, SCIFA5_TXD_MARK, TS_SDEN0_D_MARK, 640 VI0_VSYNC_N_MARK, RX5_MARK, SCIFA5_RXD_MARK, TS_SPSYNC0_D_MARK, 641 VI0_DATA3_VI0_B3_MARK, SCIF3_SCK_B_MARK, SCIFA3_SCK_B_MARK, 642 VI0_G0_MARK, SCL8_MARK, STP_IVCXO27_0_C_MARK, SCL4_MARK, 643 HCTS2_N_MARK, SCIFB2_CTS_N_MARK, ATAWR1_N_MARK, 644 645 /* IPSR10 */ 646 VI0_G1_MARK, SDA8_MARK, STP_ISCLK_0_C_MARK, SDA4_MARK, 647 HRTS2_N_MARK, SCIFB2_RTS_N_MARK, ATADIR1_N_MARK, 648 VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK, SCL3_B_MARK, 649 HSCK2_MARK, SCIFB2_SCK_MARK, ATARD1_N_MARK, 650 VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK, SDA3_B_MARK, 651 HRX2_MARK, SCIFB2_RXD_MARK, ATACS01_N_MARK, 652 VI0_G4_MARK, VI2_CLKENB_MARK, STP_ISSYNC_0_C_MARK, 653 HTX2_MARK, SCIFB2_TXD_MARK, SCIFB0_SCK_D_MARK, 654 VI0_G5_MARK, VI2_FIELD_MARK, STP_OPWM_0_C_MARK, FMCLK_D_MARK, 655 CAN0_TX_E_MARK, HTX1_D_MARK, SCIFB0_TXD_D_MARK, 656 VI0_G6_MARK, VI2_CLK_MARK, BPFCLK_D_MARK, 657 VI0_G7_MARK, VI2_DATA0_MARK, FMIN_D_MARK, 658 VI0_R0_MARK, VI2_DATA1_MARK, GLO_I0_B_MARK, 659 TS_SDATA0_C_MARK, ATACS11_N_MARK, 660 VI0_R1_MARK, VI2_DATA2_MARK, GLO_I1_B_MARK, 661 TS_SCK0_C_MARK, ATAG1_N_MARK, 662 VI0_R2_MARK, VI2_DATA3_MARK, GLO_Q0_B_MARK, TS_SDEN0_C_MARK, 663 VI0_R3_MARK, VI2_DATA4_MARK, GLO_Q1_B_MARK, TS_SPSYNC0_C_MARK, 664 VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK, TX0_C_MARK, SCL1_D_MARK, 665 666 /* IPSR11 */ 667 VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, SDA1_D_MARK, 668 VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, SCL4_B_MARK, 669 VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK, 670 SDA4_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK, 671 VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK, 672 TX4_B_MARK, SCIFA4_TXD_B_MARK, 673 VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK, 674 RX4_B_MARK, SCIFA4_RXD_B_MARK, 675 VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK, 676 VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK, 677 VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK, 678 VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK, 679 VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK, 680 VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK, 681 VI1_DATA7_MARK, AVB_MDC_MARK, 682 ETH_MDIO_MARK, AVB_RX_CLK_MARK, SCL2_C_MARK, 683 ETH_CRS_DV_MARK, AVB_LINK_MARK, SDA2_C_MARK, 684 685 /* IPSR12 */ 686 ETH_RX_ER_MARK, AVB_CRS_MARK, SCL3_MARK, SCL7_MARK, 687 ETH_RXD0_MARK, AVB_PHY_INT_MARK, SDA3_MARK, SDA7_MARK, 688 ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK, 689 SCL2_D_MARK, MSIOF1_RXD_E_MARK, 690 ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK, 691 SDA2_D_MARK, MSIOF1_SCK_E_MARK, 692 ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK, 693 CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK, 694 ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK, 695 CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK, 696 ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK, 697 ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK, 698 ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK, 699 ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK, 700 STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK, 701 ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK, 702 STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK, 703 ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK, 704 705 /* IPSR13 */ 706 STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK, 707 ADICLK_B_MARK, MSIOF0_SS1_C_MARK, 708 STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK, 709 STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK, 710 STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK, 711 ADICHS2_B_MARK, MSIOF0_TXD_C_MARK, 712 SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK, 713 SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK, 714 SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK, 715 SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK, 716 SCIFA5_TXD_B_MARK, TX3_C_MARK, 717 SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK, 718 SCIFA5_RXD_B_MARK, RX3_C_MARK, 719 SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK, 720 SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK, 721 SD1_DATA3_MARK, IERX_B_MARK, 722 SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, SCL1_C_MARK, 723 724 /* IPSR14 */ 725 SD1_WP_MARK, PWM1_B_MARK, SDA1_C_MARK, 726 SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK, 727 SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK, 728 SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK, 729 SD2_CD_MARK, MMC_D4_MARK, SCL8_C_MARK, TX5_B_MARK, SCIFA5_TXD_C_MARK, 730 SD2_WP_MARK, MMC_D5_MARK, SDA8_C_MARK, RX5_B_MARK, SCIFA5_RXD_C_MARK, 731 MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK, 732 VI1_CLK_C_MARK, VI1_G0_B_MARK, 733 MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK, 734 VI1_CLKENB_C_MARK, VI1_G1_B_MARK, 735 MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK, 736 MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK, 737 MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK, 738 VI1_HSYNC_N_C_MARK, SCL7_C_MARK, VI1_G4_B_MARK, 739 MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK, 740 VI1_VSYNC_N_C_MARK, SDA7_C_MARK, VI1_G5_B_MARK, 741 742 /* IPSR15 */ 743 SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK, 744 SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK, 745 SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK, 746 GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK, 747 PWM5_B_MARK, SCIFA3_TXD_C_MARK, 748 GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK, 749 VI1_G6_B_MARK, SCIFA3_RXD_C_MARK, 750 GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK, 751 VI1_G7_B_MARK, SCIFA3_SCK_C_MARK, 752 HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK, 753 TCLK1_MARK, VI1_DATA1_C_MARK, 754 HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK, 755 HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK, 756 TCLK2_MARK, VI1_DATA3_C_MARK, 757 HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK, 758 CAN0_RX_B_MARK, VI1_DATA4_C_MARK, 759 HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK, 760 CAN0_TX_B_MARK, VI1_DATA5_C_MARK, 761 762 /* IPSR16 */ 763 HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK, 764 GLO_SDATA_C_MARK, VI1_DATA6_C_MARK, 765 HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK, 766 GLO_SS_C_MARK, VI1_DATA7_C_MARK, 767 HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CLK_MARK, GLO_RFON_C_MARK, 768 HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK, 769 HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK, 770 PINMUX_MARK_END, 771 }; 772 773 static const u16 pinmux_data[] = { 774 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ 775 776 PINMUX_DATA(EX_CS0_N_MARK, FN_EX_CS0_N), 777 PINMUX_DATA(RD_N_MARK, FN_RD_N), 778 PINMUX_DATA(AUDIO_CLKA_MARK, FN_AUDIO_CLKA), 779 PINMUX_DATA(VI0_CLK_MARK, FN_VI0_CLK), 780 PINMUX_DATA(VI0_DATA0_VI0_B0_MARK, FN_VI0_DATA0_VI0_B0), 781 PINMUX_DATA(VI0_DATA1_VI0_B1_MARK, FN_VI0_DATA1_VI0_B1), 782 PINMUX_DATA(VI0_DATA2_VI0_B2_MARK, FN_VI0_DATA2_VI0_B2), 783 PINMUX_DATA(VI0_DATA4_VI0_B4_MARK, FN_VI0_DATA4_VI0_B4), 784 PINMUX_DATA(VI0_DATA5_VI0_B5_MARK, FN_VI0_DATA5_VI0_B5), 785 PINMUX_DATA(VI0_DATA6_VI0_B6_MARK, FN_VI0_DATA6_VI0_B6), 786 PINMUX_DATA(VI0_DATA7_VI0_B7_MARK, FN_VI0_DATA7_VI0_B7), 787 PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN), 788 PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC), 789 PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN), 790 PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC), 791 PINMUX_DATA(DU0_DOTCLKIN_MARK, FN_DU0_DOTCLKIN), 792 PINMUX_DATA(SD1_CLK_MARK, FN_SD1_CLK), 793 794 /* IPSR0 */ 795 PINMUX_IPSR_DATA(IP0_0, D0), 796 PINMUX_IPSR_DATA(IP0_1, D1), 797 PINMUX_IPSR_DATA(IP0_2, D2), 798 PINMUX_IPSR_DATA(IP0_3, D3), 799 PINMUX_IPSR_DATA(IP0_4, D4), 800 PINMUX_IPSR_DATA(IP0_5, D5), 801 PINMUX_IPSR_DATA(IP0_6, D6), 802 PINMUX_IPSR_DATA(IP0_7, D7), 803 PINMUX_IPSR_DATA(IP0_8, D8), 804 PINMUX_IPSR_DATA(IP0_9, D9), 805 PINMUX_IPSR_DATA(IP0_10, D10), 806 PINMUX_IPSR_DATA(IP0_11, D11), 807 PINMUX_IPSR_DATA(IP0_12, D12), 808 PINMUX_IPSR_DATA(IP0_13, D13), 809 PINMUX_IPSR_DATA(IP0_14, D14), 810 PINMUX_IPSR_DATA(IP0_15, D15), 811 PINMUX_IPSR_DATA(IP0_18_16, A0), 812 PINMUX_IPSR_MODSEL_DATA(IP0_18_16, ATAWR0_N_C, SEL_LBS_2), 813 PINMUX_IPSR_MODSEL_DATA(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1), 814 PINMUX_IPSR_MODSEL_DATA(IP0_18_16, SCL0_C, SEL_IIC0_2), 815 PINMUX_IPSR_DATA(IP0_18_16, PWM2_B), 816 PINMUX_IPSR_DATA(IP0_20_19, A1), 817 PINMUX_IPSR_MODSEL_DATA(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1), 818 PINMUX_IPSR_DATA(IP0_22_21, A2), 819 PINMUX_IPSR_MODSEL_DATA(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1), 820 PINMUX_IPSR_DATA(IP0_24_23, A3), 821 PINMUX_IPSR_MODSEL_DATA(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1), 822 PINMUX_IPSR_DATA(IP0_26_25, A4), 823 PINMUX_IPSR_MODSEL_DATA(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1), 824 PINMUX_IPSR_DATA(IP0_28_27, A5), 825 PINMUX_IPSR_MODSEL_DATA(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1), 826 PINMUX_IPSR_DATA(IP0_30_29, A6), 827 PINMUX_IPSR_MODSEL_DATA(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0), 828 829 /* IPSR1 */ 830 PINMUX_IPSR_DATA(IP1_1_0, A7), 831 PINMUX_IPSR_MODSEL_DATA(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0), 832 PINMUX_IPSR_DATA(IP1_3_2, A8), 833 PINMUX_IPSR_MODSEL_DATA(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0), 834 PINMUX_IPSR_MODSEL_DATA(IP1_3_2, SCL0, SEL_IIC0_0), 835 PINMUX_IPSR_DATA(IP1_5_4, A9), 836 PINMUX_IPSR_MODSEL_DATA(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0), 837 PINMUX_IPSR_MODSEL_DATA(IP1_5_4, SDA0, SEL_IIC0_0), 838 PINMUX_IPSR_DATA(IP1_7_6, A10), 839 PINMUX_IPSR_MODSEL_DATA(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0), 840 PINMUX_IPSR_MODSEL_DATA(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3), 841 PINMUX_IPSR_DATA(IP1_10_8, A11), 842 PINMUX_IPSR_MODSEL_DATA(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0), 843 PINMUX_IPSR_MODSEL_DATA(IP1_10_8, SCL3_D, SEL_IIC3_3), 844 PINMUX_IPSR_MODSEL_DATA(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3), 845 PINMUX_IPSR_DATA(IP1_13_11, A12), 846 PINMUX_IPSR_MODSEL_DATA(IP1_13_11, FMCLK, SEL_FM_0), 847 PINMUX_IPSR_MODSEL_DATA(IP1_13_11, SDA3_D, SEL_IIC3_3), 848 PINMUX_IPSR_MODSEL_DATA(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3), 849 PINMUX_IPSR_DATA(IP1_16_14, A13), 850 PINMUX_IPSR_MODSEL_DATA(IP1_16_14, ATAG0_N_C, SEL_LBS_2), 851 PINMUX_IPSR_MODSEL_DATA(IP1_16_14, BPFCLK, SEL_FM_0), 852 PINMUX_IPSR_MODSEL_DATA(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3), 853 PINMUX_IPSR_DATA(IP1_19_17, A14), 854 PINMUX_IPSR_MODSEL_DATA(IP1_19_17, ATADIR0_N_C, SEL_LBS_2), 855 PINMUX_IPSR_MODSEL_DATA(IP1_19_17, FMIN, SEL_FM_0), 856 PINMUX_IPSR_MODSEL_DATA(IP1_19_17, FMIN_C, SEL_FM_2), 857 PINMUX_IPSR_MODSEL_DATA(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3), 858 PINMUX_IPSR_DATA(IP1_22_20, A15), 859 PINMUX_IPSR_MODSEL_DATA(IP1_22_20, BPFCLK_C, SEL_FM_2), 860 PINMUX_IPSR_DATA(IP1_25_23, A16), 861 PINMUX_IPSR_MODSEL_DATA(IP1_25_23, DREQ2_B, SEL_LBS_1), 862 PINMUX_IPSR_MODSEL_DATA(IP1_25_23, FMCLK_C, SEL_FM_2), 863 PINMUX_IPSR_MODSEL_DATA(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1), 864 PINMUX_IPSR_DATA(IP1_28_26, A17), 865 PINMUX_IPSR_MODSEL_DATA(IP1_28_26, DACK2_B, SEL_LBS_1), 866 PINMUX_IPSR_MODSEL_DATA(IP1_28_26, SDA0_C, SEL_IIC0_2), 867 PINMUX_IPSR_DATA(IP1_31_29, A18), 868 PINMUX_IPSR_MODSEL_DATA(IP1_31_29, DREQ1, SEL_LBS_0), 869 PINMUX_IPSR_MODSEL_DATA(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2), 870 PINMUX_IPSR_MODSEL_DATA(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2), 871 872 /* IPSR2 */ 873 PINMUX_IPSR_DATA(IP2_2_0, A19), 874 PINMUX_IPSR_DATA(IP2_2_0, DACK1), 875 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2), 876 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2), 877 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_0), 878 PINMUX_IPSR_DATA(IP2_2_0, A20), 879 PINMUX_IPSR_MODSEL_DATA(IP2_4_3, SPCLK, SEL_QSP_0), 880 PINMUX_IPSR_DATA(IP2_6_5, A21), 881 PINMUX_IPSR_MODSEL_DATA(IP2_6_5, ATAWR0_N_B, SEL_LBS_1), 882 PINMUX_IPSR_MODSEL_DATA(IP2_6_5, MOSI_IO0, SEL_QSP_0), 883 PINMUX_IPSR_DATA(IP2_9_7, A22), 884 PINMUX_IPSR_MODSEL_DATA(IP2_9_7, MISO_IO1, SEL_QSP_0), 885 PINMUX_IPSR_MODSEL_DATA(IP2_9_7, FMCLK_B, SEL_FM_1), 886 PINMUX_IPSR_MODSEL_DATA(IP2_9_7, TX0, SEL_SCIF0_0), 887 PINMUX_IPSR_MODSEL_DATA(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0), 888 PINMUX_IPSR_DATA(IP2_12_10, A23), 889 PINMUX_IPSR_MODSEL_DATA(IP2_12_10, IO2, SEL_QSP_0), 890 PINMUX_IPSR_MODSEL_DATA(IP2_12_10, BPFCLK_B, SEL_FM_1), 891 PINMUX_IPSR_MODSEL_DATA(IP2_12_10, RX0, SEL_SCIF0_0), 892 PINMUX_IPSR_MODSEL_DATA(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0), 893 PINMUX_IPSR_DATA(IP2_15_13, A24), 894 PINMUX_IPSR_MODSEL_DATA(IP2_15_13, DREQ2, SEL_LBS_0), 895 PINMUX_IPSR_MODSEL_DATA(IP2_15_13, IO3, SEL_QSP_0), 896 PINMUX_IPSR_MODSEL_DATA(IP2_15_13, TX1, SEL_SCIF1_0), 897 PINMUX_IPSR_MODSEL_DATA(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0), 898 PINMUX_IPSR_DATA(IP2_18_16, A25), 899 PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DACK2, SEL_LBS_0), 900 PINMUX_IPSR_MODSEL_DATA(IP2_18_16, SSL, SEL_QSP_0), 901 PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DREQ1_C, SEL_LBS_2), 902 PINMUX_IPSR_MODSEL_DATA(IP2_18_16, RX1, SEL_SCIF1_0), 903 PINMUX_IPSR_MODSEL_DATA(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0), 904 PINMUX_IPSR_DATA(IP2_20_19, CS0_N), 905 PINMUX_IPSR_MODSEL_DATA(IP2_20_19, ATAG0_N_B, SEL_LBS_1), 906 PINMUX_IPSR_MODSEL_DATA(IP2_20_19, SCL1, SEL_IIC1_0), 907 PINMUX_IPSR_DATA(IP2_22_21, CS1_N_A26), 908 PINMUX_IPSR_MODSEL_DATA(IP2_22_21, ATADIR0_N_B, SEL_LBS_1), 909 PINMUX_IPSR_MODSEL_DATA(IP2_22_21, SDA1, SEL_IIC1_0), 910 PINMUX_IPSR_DATA(IP2_24_23, EX_CS1_N), 911 PINMUX_IPSR_MODSEL_DATA(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0), 912 PINMUX_IPSR_DATA(IP2_26_25, EX_CS2_N), 913 PINMUX_IPSR_MODSEL_DATA(IP2_26_25, ATAWR0_N, SEL_LBS_0), 914 PINMUX_IPSR_MODSEL_DATA(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0), 915 PINMUX_IPSR_DATA(IP2_29_27, EX_CS3_N), 916 PINMUX_IPSR_MODSEL_DATA(IP2_29_27, ATADIR0_N, SEL_LBS_0), 917 PINMUX_IPSR_MODSEL_DATA(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0), 918 PINMUX_IPSR_MODSEL_DATA(IP2_29_27, ATAG0_N, SEL_LBS_0), 919 PINMUX_IPSR_DATA(IP2_29_27, EX_WAIT1), 920 921 /* IPSR3 */ 922 PINMUX_IPSR_DATA(IP3_2_0, EX_CS4_N), 923 PINMUX_IPSR_MODSEL_DATA(IP3_2_0, ATARD0_N, SEL_LBS_0), 924 PINMUX_IPSR_MODSEL_DATA(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0), 925 PINMUX_IPSR_DATA(IP3_2_0, EX_WAIT2), 926 PINMUX_IPSR_DATA(IP3_5_3, EX_CS5_N), 927 PINMUX_IPSR_DATA(IP3_5_3, ATACS00_N), 928 PINMUX_IPSR_MODSEL_DATA(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0), 929 PINMUX_IPSR_MODSEL_DATA(IP3_5_3, HRX1_B, SEL_HSCIF1_1), 930 PINMUX_IPSR_MODSEL_DATA(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1), 931 PINMUX_IPSR_DATA(IP3_5_3, PWM1), 932 PINMUX_IPSR_DATA(IP3_5_3, TPU_TO1), 933 PINMUX_IPSR_DATA(IP3_8_6, BS_N), 934 PINMUX_IPSR_DATA(IP3_8_6, ATACS10_N), 935 PINMUX_IPSR_MODSEL_DATA(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0), 936 PINMUX_IPSR_MODSEL_DATA(IP3_8_6, HTX1_B, SEL_HSCIF1_1), 937 PINMUX_IPSR_MODSEL_DATA(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1), 938 PINMUX_IPSR_DATA(IP3_8_6, PWM2), 939 PINMUX_IPSR_DATA(IP3_8_6, TPU_TO2), 940 PINMUX_IPSR_DATA(IP3_11_9, RD_WR_N), 941 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, HRX2_B, SEL_HSCIF2_1), 942 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, FMIN_B, SEL_FM_1), 943 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1), 944 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, DREQ1_D, SEL_LBS_1), 945 PINMUX_IPSR_DATA(IP3_13_12, WE0_N), 946 PINMUX_IPSR_MODSEL_DATA(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1), 947 PINMUX_IPSR_MODSEL_DATA(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1), 948 PINMUX_IPSR_DATA(IP3_15_14, WE1_N), 949 PINMUX_IPSR_MODSEL_DATA(IP3_15_14, ATARD0_N_B, SEL_LBS_1), 950 PINMUX_IPSR_MODSEL_DATA(IP3_15_14, HTX2_B, SEL_HSCIF2_1), 951 PINMUX_IPSR_MODSEL_DATA(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1), 952 PINMUX_IPSR_DATA(IP3_17_16, EX_WAIT0), 953 PINMUX_IPSR_MODSEL_DATA(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1), 954 PINMUX_IPSR_MODSEL_DATA(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1), 955 PINMUX_IPSR_DATA(IP3_19_18, DREQ0), 956 PINMUX_IPSR_DATA(IP3_19_18, PWM3), 957 PINMUX_IPSR_DATA(IP3_19_18, TPU_TO3), 958 PINMUX_IPSR_DATA(IP3_21_20, DACK0), 959 PINMUX_IPSR_DATA(IP3_21_20, DRACK0), 960 PINMUX_IPSR_MODSEL_DATA(IP3_21_20, REMOCON, SEL_RCN_0), 961 PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SPEEDIN, SEL_RSP_0), 962 PINMUX_IPSR_MODSEL_DATA(IP3_24_22, HSCK0_C, SEL_HSCIF0_2), 963 PINMUX_IPSR_MODSEL_DATA(IP3_24_22, HSCK2_C, SEL_HSCIF2_2), 964 PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1), 965 PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1), 966 PINMUX_IPSR_MODSEL_DATA(IP3_24_22, DREQ2_C, SEL_LBS_2), 967 PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX2_C, SEL_HSCIF2_2), 968 PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SSI_SCK0129, SEL_SSI0_0), 969 PINMUX_IPSR_MODSEL_DATA(IP3_27_25, HRX0_C, SEL_HSCIF0_2), 970 PINMUX_IPSR_MODSEL_DATA(IP3_27_25, HRX2_C, SEL_HSCIF2_2), 971 PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2), 972 PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2), 973 PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SSI_WS0129, SEL_SSI0_0), 974 PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX0_C, SEL_HSCIF0_2), 975 PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX2_C, SEL_HSCIF2_2), 976 PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2), 977 PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2), 978 979 /* IPSR4 */ 980 PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SSI_SDATA0, SEL_SSI0_0), 981 PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCL0_B, SEL_IIC0_1), 982 PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCL7_B, SEL_IIC7_1), 983 PINMUX_IPSR_MODSEL_DATA(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2), 984 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SSI_SCK1, SEL_SSI1_0), 985 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SDA0_B, SEL_IIC0_1), 986 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SDA7_B, SEL_IIC7_1), 987 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2), 988 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, GLO_I0_D, SEL_GPS_3), 989 PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SSI_WS1, SEL_SSI1_0), 990 PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SCL1_B, SEL_IIC1_1), 991 PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SCL8_B, SEL_IIC8_1), 992 PINMUX_IPSR_MODSEL_DATA(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2), 993 PINMUX_IPSR_MODSEL_DATA(IP4_7_5, GLO_I1_D, SEL_GPS_3), 994 PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SSI_SDATA1, SEL_SSI1_0), 995 PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SDA1_B, SEL_IIC1_1), 996 PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SDA8_B, SEL_IIC8_1), 997 PINMUX_IPSR_MODSEL_DATA(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2), 998 PINMUX_IPSR_DATA(IP4_12_10, SSI_SCK2), 999 PINMUX_IPSR_MODSEL_DATA(IP4_12_10, SCL2, SEL_IIC2_0), 1000 PINMUX_IPSR_MODSEL_DATA(IP4_12_10, GPS_CLK_B, SEL_GPS_1), 1001 PINMUX_IPSR_MODSEL_DATA(IP4_12_10, GLO_Q0_D, SEL_GPS_3), 1002 PINMUX_IPSR_DATA(IP4_15_13, SSI_WS2), 1003 PINMUX_IPSR_MODSEL_DATA(IP4_15_13, SDA2, SEL_IIC2_0), 1004 PINMUX_IPSR_MODSEL_DATA(IP4_15_13, GPS_SIGN_B, SEL_GPS_1), 1005 PINMUX_IPSR_MODSEL_DATA(IP4_15_13, RX2_E, SEL_SCIF2_4), 1006 PINMUX_IPSR_MODSEL_DATA(IP4_15_13, GLO_Q1_D, SEL_GPS_3), 1007 PINMUX_IPSR_DATA(IP4_18_16, SSI_SDATA2), 1008 PINMUX_IPSR_MODSEL_DATA(IP4_18_16, GPS_MAG_B, SEL_GPS_1), 1009 PINMUX_IPSR_MODSEL_DATA(IP4_18_16, TX2_E, SEL_SCIF2_4), 1010 PINMUX_IPSR_DATA(IP4_19, SSI_SCK34), 1011 PINMUX_IPSR_DATA(IP4_20, SSI_WS34), 1012 PINMUX_IPSR_DATA(IP4_21, SSI_SDATA3), 1013 PINMUX_IPSR_DATA(IP4_23_22, SSI_SCK4), 1014 PINMUX_IPSR_MODSEL_DATA(IP4_23_22, GLO_SS_D, SEL_GPS_3), 1015 PINMUX_IPSR_DATA(IP4_25_24, SSI_WS4), 1016 PINMUX_IPSR_MODSEL_DATA(IP4_25_24, GLO_RFON_D, SEL_GPS_3), 1017 PINMUX_IPSR_DATA(IP4_27_26, SSI_SDATA4), 1018 PINMUX_IPSR_MODSEL_DATA(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3), 1019 PINMUX_IPSR_DATA(IP4_30_28, SSI_SCK5), 1020 PINMUX_IPSR_MODSEL_DATA(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2), 1021 PINMUX_IPSR_MODSEL_DATA(IP4_30_28, TS_SDATA0, SEL_TSIF0_0), 1022 PINMUX_IPSR_MODSEL_DATA(IP4_30_28, GLO_I0, SEL_GPS_0), 1023 PINMUX_IPSR_MODSEL_DATA(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3), 1024 PINMUX_IPSR_DATA(IP4_30_28, VI1_R2_B), 1025 1026 /* IPSR5 */ 1027 PINMUX_IPSR_DATA(IP5_2_0, SSI_WS5), 1028 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2), 1029 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, TS_SCK0, SEL_TSIF0_0), 1030 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, GLO_I1, SEL_GPS_0), 1031 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3), 1032 PINMUX_IPSR_DATA(IP5_2_0, VI1_R3_B), 1033 PINMUX_IPSR_DATA(IP5_5_3, SSI_SDATA5), 1034 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2), 1035 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, TS_SDEN0, SEL_TSIF0_0), 1036 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, GLO_Q0, SEL_GPS_0), 1037 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3), 1038 PINMUX_IPSR_DATA(IP5_5_3, VI1_R4_B), 1039 PINMUX_IPSR_DATA(IP5_8_6, SSI_SCK6), 1040 PINMUX_IPSR_MODSEL_DATA(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2), 1041 PINMUX_IPSR_MODSEL_DATA(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0), 1042 PINMUX_IPSR_MODSEL_DATA(IP5_8_6, GLO_Q1, SEL_GPS_0), 1043 PINMUX_IPSR_MODSEL_DATA(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3), 1044 PINMUX_IPSR_DATA(IP5_8_6, VI1_R5_B), 1045 PINMUX_IPSR_DATA(IP5_11_9, SSI_WS6), 1046 PINMUX_IPSR_MODSEL_DATA(IP5_11_9, GLO_SCLK, SEL_GPS_0), 1047 PINMUX_IPSR_MODSEL_DATA(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3), 1048 PINMUX_IPSR_DATA(IP5_11_9, VI1_R6_B), 1049 PINMUX_IPSR_DATA(IP5_14_12, SSI_SDATA6), 1050 PINMUX_IPSR_MODSEL_DATA(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1), 1051 PINMUX_IPSR_MODSEL_DATA(IP5_14_12, GLO_SDATA, SEL_GPS_0), 1052 PINMUX_IPSR_DATA(IP5_14_12, VI1_R7_B), 1053 PINMUX_IPSR_MODSEL_DATA(IP5_16_15, SSI_SCK78, SEL_SSI7_0), 1054 PINMUX_IPSR_MODSEL_DATA(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1), 1055 PINMUX_IPSR_MODSEL_DATA(IP5_16_15, GLO_SS, SEL_GPS_0), 1056 PINMUX_IPSR_MODSEL_DATA(IP5_19_17, SSI_WS78, SEL_SSI7_0), 1057 PINMUX_IPSR_MODSEL_DATA(IP5_19_17, TX0_D, SEL_SCIF0_3), 1058 PINMUX_IPSR_MODSEL_DATA(IP5_19_17, STP_ISD_0_B, SEL_SSP_1), 1059 PINMUX_IPSR_MODSEL_DATA(IP5_19_17, GLO_RFON, SEL_GPS_0), 1060 PINMUX_IPSR_MODSEL_DATA(IP5_21_20, SSI_SDATA7, SEL_SSI7_0), 1061 PINMUX_IPSR_MODSEL_DATA(IP5_21_20, RX0_D, SEL_SCIF0_3), 1062 PINMUX_IPSR_MODSEL_DATA(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1), 1063 PINMUX_IPSR_MODSEL_DATA(IP5_23_22, SSI_SDATA8, SEL_SSI8_0), 1064 PINMUX_IPSR_MODSEL_DATA(IP5_23_22, TX1_D, SEL_SCIF1_3), 1065 PINMUX_IPSR_MODSEL_DATA(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1), 1066 PINMUX_IPSR_MODSEL_DATA(IP5_25_24, SSI_SCK9, SEL_SSI9_0), 1067 PINMUX_IPSR_MODSEL_DATA(IP5_25_24, RX1_D, SEL_SCIF1_3), 1068 PINMUX_IPSR_MODSEL_DATA(IP5_25_24, GLO_SCLK_D, SEL_GPS_3), 1069 PINMUX_IPSR_MODSEL_DATA(IP5_28_26, SSI_WS9, SEL_SSI9_0), 1070 PINMUX_IPSR_MODSEL_DATA(IP5_28_26, TX3_D, SEL_SCIF3_3), 1071 PINMUX_IPSR_MODSEL_DATA(IP5_28_26, CAN0_TX_D, SEL_CAN0_3), 1072 PINMUX_IPSR_MODSEL_DATA(IP5_28_26, GLO_SDATA_D, SEL_GPS_3), 1073 PINMUX_IPSR_MODSEL_DATA(IP5_31_29, SSI_SDATA9, SEL_SSI9_0), 1074 PINMUX_IPSR_MODSEL_DATA(IP5_31_29, RX3_D, SEL_SCIF3_3), 1075 PINMUX_IPSR_MODSEL_DATA(IP5_31_29, CAN0_RX_D, SEL_CAN0_3), 1076 1077 /* IPSR6 */ 1078 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, AUDIO_CLKB, SEL_ADG_0), 1079 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1), 1080 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1), 1081 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SCIF_CLK, SEL_SCIF_0), 1082 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, BPFCLK_E, SEL_FM_4), 1083 PINMUX_IPSR_DATA(IP6_5_3, AUDIO_CLKC), 1084 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2), 1085 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1), 1086 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, RX2, SEL_SCIF2_0), 1087 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0), 1088 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, FMIN_E, SEL_FM_4), 1089 PINMUX_IPSR_DATA(IP6_7_6, AUDIO_CLKOUT), 1090 PINMUX_IPSR_MODSEL_DATA(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1), 1091 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, TX2, SEL_SCIF2_0), 1092 PINMUX_IPSR_MODSEL_DATA(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0), 1093 PINMUX_IPSR_DATA(IP6_9_8, IRQ0), 1094 PINMUX_IPSR_MODSEL_DATA(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3), 1095 PINMUX_IPSR_DATA(IP6_9_8, INTC_IRQ0_N), 1096 PINMUX_IPSR_DATA(IP6_11_10, IRQ1), 1097 PINMUX_IPSR_MODSEL_DATA(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2), 1098 PINMUX_IPSR_DATA(IP6_11_10, INTC_IRQ1_N), 1099 PINMUX_IPSR_DATA(IP6_13_12, IRQ2), 1100 PINMUX_IPSR_MODSEL_DATA(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3), 1101 PINMUX_IPSR_DATA(IP6_13_12, INTC_IRQ2_N), 1102 PINMUX_IPSR_DATA(IP6_15_14, IRQ3), 1103 PINMUX_IPSR_MODSEL_DATA(IP6_15_14, SCL4_C, SEL_IIC4_2), 1104 PINMUX_IPSR_MODSEL_DATA(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4), 1105 PINMUX_IPSR_DATA(IP6_15_14, INTC_IRQ4_N), 1106 PINMUX_IPSR_DATA(IP6_18_16, IRQ4), 1107 PINMUX_IPSR_MODSEL_DATA(IP6_18_16, HRX1_C, SEL_HSCIF1_2), 1108 PINMUX_IPSR_MODSEL_DATA(IP6_18_16, SDA4_C, SEL_IIC4_2), 1109 PINMUX_IPSR_MODSEL_DATA(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4), 1110 PINMUX_IPSR_DATA(IP6_18_16, INTC_IRQ4_N), 1111 PINMUX_IPSR_DATA(IP6_20_19, IRQ5), 1112 PINMUX_IPSR_MODSEL_DATA(IP6_20_19, HTX1_C, SEL_HSCIF1_2), 1113 PINMUX_IPSR_MODSEL_DATA(IP6_20_19, SCL1_E, SEL_IIC1_4), 1114 PINMUX_IPSR_MODSEL_DATA(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4), 1115 PINMUX_IPSR_DATA(IP6_23_21, IRQ6), 1116 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, HSCK1_C, SEL_HSCIF1_2), 1117 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1), 1118 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, SDA1_E, SEL_IIC1_4), 1119 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4), 1120 PINMUX_IPSR_DATA(IP6_26_24, IRQ7), 1121 PINMUX_IPSR_MODSEL_DATA(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2), 1122 PINMUX_IPSR_MODSEL_DATA(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1), 1123 PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_C, SEL_GPS_2), 1124 PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_D, SEL_GPS_3), 1125 PINMUX_IPSR_DATA(IP6_29_27, IRQ8), 1126 PINMUX_IPSR_MODSEL_DATA(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2), 1127 PINMUX_IPSR_MODSEL_DATA(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1), 1128 PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_C, SEL_GPS_2), 1129 PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_D, SEL_GPS_3), 1130 1131 /* IPSR7 */ 1132 PINMUX_IPSR_DATA(IP7_2_0, IRQ9), 1133 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1), 1134 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3), 1135 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, GPS_MAG_C, SEL_GPS_2), 1136 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1), 1137 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, GPS_MAG_D, SEL_GPS_3), 1138 PINMUX_IPSR_DATA(IP7_5_3, DU1_DR0), 1139 PINMUX_IPSR_DATA(IP7_5_3, LCDOUT0), 1140 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, VI1_DATA0_B, SEL_VI1_1), 1141 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, TX0_B, SEL_SCIF0_1), 1142 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1), 1143 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1), 1144 PINMUX_IPSR_DATA(IP7_8_6, DU1_DR1), 1145 PINMUX_IPSR_DATA(IP7_8_6, LCDOUT1), 1146 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, VI1_DATA1_B, SEL_VI1_1), 1147 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, RX0_B, SEL_SCIF0_1), 1148 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1), 1149 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1), 1150 PINMUX_IPSR_DATA(IP7_10_9, DU1_DR2), 1151 PINMUX_IPSR_DATA(IP7_10_9, LCDOUT2), 1152 PINMUX_IPSR_MODSEL_DATA(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1), 1153 PINMUX_IPSR_DATA(IP7_12_11, DU1_DR3), 1154 PINMUX_IPSR_DATA(IP7_12_11, LCDOUT3), 1155 PINMUX_IPSR_MODSEL_DATA(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1), 1156 PINMUX_IPSR_DATA(IP7_14_13, DU1_DR4), 1157 PINMUX_IPSR_DATA(IP7_14_13, LCDOUT4), 1158 PINMUX_IPSR_MODSEL_DATA(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1), 1159 PINMUX_IPSR_DATA(IP7_16_15, DU1_DR5), 1160 PINMUX_IPSR_DATA(IP7_16_15, LCDOUT5), 1161 PINMUX_IPSR_MODSEL_DATA(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1), 1162 PINMUX_IPSR_DATA(IP7_18_17, DU1_DR6), 1163 PINMUX_IPSR_DATA(IP7_18_17, LCDOUT6), 1164 PINMUX_IPSR_MODSEL_DATA(IP7_18_17, SSI_WS1_B, SEL_SSI1_1), 1165 PINMUX_IPSR_DATA(IP7_20_19, DU1_DR7), 1166 PINMUX_IPSR_DATA(IP7_20_19, LCDOUT7), 1167 PINMUX_IPSR_MODSEL_DATA(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1), 1168 PINMUX_IPSR_DATA(IP7_23_21, DU1_DG0), 1169 PINMUX_IPSR_DATA(IP7_23_21, LCDOUT8), 1170 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, VI1_DATA2_B, SEL_VI1_1), 1171 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, TX1_B, SEL_SCIF1_1), 1172 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1), 1173 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1), 1174 PINMUX_IPSR_DATA(IP7_26_24, DU1_DG1), 1175 PINMUX_IPSR_DATA(IP7_26_24, LCDOUT9), 1176 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, VI1_DATA3_B, SEL_VI1_1), 1177 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, RX1_B, SEL_SCIF1_1), 1178 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1), 1179 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1), 1180 PINMUX_IPSR_DATA(IP7_29_27, DU1_DG2), 1181 PINMUX_IPSR_DATA(IP7_29_27, LCDOUT10), 1182 PINMUX_IPSR_MODSEL_DATA(IP7_29_27, VI1_DATA4_B, SEL_VI1_1), 1183 PINMUX_IPSR_DATA(IP7_29_27, SCIF1_SCK_B), 1184 PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0), 1185 PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1), 1186 1187 /* IPSR8 */ 1188 PINMUX_IPSR_DATA(IP8_2_0, DU1_DG3), 1189 PINMUX_IPSR_DATA(IP8_2_0, LCDOUT11), 1190 PINMUX_IPSR_MODSEL_DATA(IP8_2_0, VI1_DATA5_B, SEL_VI1_1), 1191 PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SSI_WS78_B, SEL_SSI7_1), 1192 PINMUX_IPSR_DATA(IP8_5_3, DU1_DG4), 1193 PINMUX_IPSR_DATA(IP8_5_3, LCDOUT12), 1194 PINMUX_IPSR_MODSEL_DATA(IP8_5_3, VI1_DATA6_B, SEL_VI1_1), 1195 PINMUX_IPSR_MODSEL_DATA(IP8_5_3, HRX0_B, SEL_HSCIF0_1), 1196 PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1), 1197 PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1), 1198 PINMUX_IPSR_DATA(IP8_8_6, DU1_DG5), 1199 PINMUX_IPSR_DATA(IP8_8_6, LCDOUT13), 1200 PINMUX_IPSR_MODSEL_DATA(IP8_8_6, VI1_DATA7_B, SEL_VI1_1), 1201 PINMUX_IPSR_MODSEL_DATA(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1), 1202 PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1), 1203 PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1), 1204 PINMUX_IPSR_DATA(IP8_11_9, DU1_DG6), 1205 PINMUX_IPSR_DATA(IP8_11_9, LCDOUT14), 1206 PINMUX_IPSR_MODSEL_DATA(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1), 1207 PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1), 1208 PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1), 1209 PINMUX_IPSR_DATA(IP8_14_12, DU1_DG7), 1210 PINMUX_IPSR_DATA(IP8_14_12, LCDOUT15), 1211 PINMUX_IPSR_MODSEL_DATA(IP8_14_12, HTX0_B, SEL_HSCIF0_1), 1212 PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1), 1213 PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SSI_WS9_B, SEL_SSI9_1), 1214 PINMUX_IPSR_DATA(IP8_17_15, DU1_DB0), 1215 PINMUX_IPSR_DATA(IP8_17_15, LCDOUT16), 1216 PINMUX_IPSR_MODSEL_DATA(IP8_17_15, VI1_CLK_B, SEL_VI1_1), 1217 PINMUX_IPSR_MODSEL_DATA(IP8_17_15, TX2_B, SEL_SCIF2_1), 1218 PINMUX_IPSR_MODSEL_DATA(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1), 1219 PINMUX_IPSR_MODSEL_DATA(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1), 1220 PINMUX_IPSR_DATA(IP8_20_18, DU1_DB1), 1221 PINMUX_IPSR_DATA(IP8_20_18, LCDOUT17), 1222 PINMUX_IPSR_MODSEL_DATA(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1), 1223 PINMUX_IPSR_MODSEL_DATA(IP8_20_18, RX2_B, SEL_SCIF2_1), 1224 PINMUX_IPSR_MODSEL_DATA(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1), 1225 PINMUX_IPSR_MODSEL_DATA(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1), 1226 PINMUX_IPSR_DATA(IP8_23_21, DU1_DB2), 1227 PINMUX_IPSR_DATA(IP8_23_21, LCDOUT18), 1228 PINMUX_IPSR_MODSEL_DATA(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1), 1229 PINMUX_IPSR_DATA(IP8_23_21, SCIF2_SCK_B), 1230 PINMUX_IPSR_MODSEL_DATA(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1), 1231 PINMUX_IPSR_MODSEL_DATA(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1), 1232 PINMUX_IPSR_DATA(IP8_25_24, DU1_DB3), 1233 PINMUX_IPSR_DATA(IP8_25_24, LCDOUT19), 1234 PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1), 1235 PINMUX_IPSR_DATA(IP8_27_26, DU1_DB4), 1236 PINMUX_IPSR_DATA(IP8_27_26, LCDOUT20), 1237 PINMUX_IPSR_MODSEL_DATA(IP8_27_26, VI1_FIELD_B, SEL_VI1_1), 1238 PINMUX_IPSR_MODSEL_DATA(IP8_27_26, CAN1_RX, SEL_CAN1_0), 1239 PINMUX_IPSR_DATA(IP8_30_28, DU1_DB5), 1240 PINMUX_IPSR_DATA(IP8_30_28, LCDOUT21), 1241 PINMUX_IPSR_MODSEL_DATA(IP8_30_28, TX3, SEL_SCIF3_0), 1242 PINMUX_IPSR_MODSEL_DATA(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0), 1243 PINMUX_IPSR_MODSEL_DATA(IP8_30_28, CAN1_TX, SEL_CAN1_0), 1244 1245 /* IPSR9 */ 1246 PINMUX_IPSR_DATA(IP9_2_0, DU1_DB6), 1247 PINMUX_IPSR_DATA(IP9_2_0, LCDOUT22), 1248 PINMUX_IPSR_MODSEL_DATA(IP9_2_0, SCL3_C, SEL_IIC3_2), 1249 PINMUX_IPSR_MODSEL_DATA(IP9_2_0, RX3, SEL_SCIF3_0), 1250 PINMUX_IPSR_MODSEL_DATA(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0), 1251 PINMUX_IPSR_DATA(IP9_5_3, DU1_DB7), 1252 PINMUX_IPSR_DATA(IP9_5_3, LCDOUT23), 1253 PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SDA3_C, SEL_IIC3_2), 1254 PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0), 1255 PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0), 1256 PINMUX_IPSR_MODSEL_DATA(IP9_6, DU1_DOTCLKIN, SEL_DIS_0), 1257 PINMUX_IPSR_DATA(IP9_6, QSTVA_QVS), 1258 PINMUX_IPSR_DATA(IP9_7, DU1_DOTCLKOUT0), 1259 PINMUX_IPSR_DATA(IP9_7, QCLK), 1260 PINMUX_IPSR_DATA(IP9_10_8, DU1_DOTCLKOUT1), 1261 PINMUX_IPSR_DATA(IP9_10_8, QSTVB_QVE), 1262 PINMUX_IPSR_MODSEL_DATA(IP9_10_8, CAN0_TX, SEL_CAN0_0), 1263 PINMUX_IPSR_MODSEL_DATA(IP9_10_8, TX3_B, SEL_SCIF3_1), 1264 PINMUX_IPSR_MODSEL_DATA(IP9_10_8, SCL2_B, SEL_IIC2_1), 1265 PINMUX_IPSR_DATA(IP9_10_8, PWM4), 1266 PINMUX_IPSR_DATA(IP9_11, DU1_EXHSYNC_DU1_HSYNC), 1267 PINMUX_IPSR_DATA(IP9_11, QSTH_QHS), 1268 PINMUX_IPSR_DATA(IP9_12, DU1_EXVSYNC_DU1_VSYNC), 1269 PINMUX_IPSR_DATA(IP9_12, QSTB_QHE), 1270 PINMUX_IPSR_DATA(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE), 1271 PINMUX_IPSR_DATA(IP9_15_13, QCPV_QDE), 1272 PINMUX_IPSR_MODSEL_DATA(IP9_15_13, CAN0_RX, SEL_CAN0_0), 1273 PINMUX_IPSR_MODSEL_DATA(IP9_15_13, RX3_B, SEL_SCIF3_1), 1274 PINMUX_IPSR_MODSEL_DATA(IP9_15_13, SDA2_B, SEL_IIC2_1), 1275 PINMUX_IPSR_DATA(IP9_16, DU1_DISP), 1276 PINMUX_IPSR_DATA(IP9_16, QPOLA), 1277 PINMUX_IPSR_DATA(IP9_18_17, DU1_CDE), 1278 PINMUX_IPSR_DATA(IP9_18_17, QPOLB), 1279 PINMUX_IPSR_DATA(IP9_18_17, PWM4_B), 1280 PINMUX_IPSR_DATA(IP9_20_19, VI0_CLKENB), 1281 PINMUX_IPSR_MODSEL_DATA(IP9_20_19, TX4, SEL_SCIF4_0), 1282 PINMUX_IPSR_MODSEL_DATA(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0), 1283 PINMUX_IPSR_MODSEL_DATA(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3), 1284 PINMUX_IPSR_DATA(IP9_22_21, VI0_FIELD), 1285 PINMUX_IPSR_MODSEL_DATA(IP9_22_21, RX4, SEL_SCIF4_0), 1286 PINMUX_IPSR_MODSEL_DATA(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0), 1287 PINMUX_IPSR_MODSEL_DATA(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3), 1288 PINMUX_IPSR_DATA(IP9_24_23, VI0_HSYNC_N), 1289 PINMUX_IPSR_MODSEL_DATA(IP9_24_23, TX5, SEL_SCIF5_0), 1290 PINMUX_IPSR_MODSEL_DATA(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0), 1291 PINMUX_IPSR_MODSEL_DATA(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3), 1292 PINMUX_IPSR_DATA(IP9_26_25, VI0_VSYNC_N), 1293 PINMUX_IPSR_MODSEL_DATA(IP9_26_25, RX5, SEL_SCIF5_0), 1294 PINMUX_IPSR_MODSEL_DATA(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0), 1295 PINMUX_IPSR_MODSEL_DATA(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3), 1296 PINMUX_IPSR_DATA(IP9_28_27, VI0_DATA3_VI0_B3), 1297 PINMUX_IPSR_MODSEL_DATA(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1), 1298 PINMUX_IPSR_MODSEL_DATA(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1), 1299 PINMUX_IPSR_DATA(IP9_31_29, VI0_G0), 1300 PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCL8, SEL_IIC8_0), 1301 PINMUX_IPSR_MODSEL_DATA(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2), 1302 PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCL4, SEL_IIC4_0), 1303 PINMUX_IPSR_MODSEL_DATA(IP9_31_29, HCTS2_N, SEL_HSCIF2_0), 1304 PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0), 1305 PINMUX_IPSR_DATA(IP9_31_29, ATAWR1_N), 1306 1307 /* IPSR10 */ 1308 PINMUX_IPSR_DATA(IP10_2_0, VI0_G1), 1309 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SDA8, SEL_IIC8_0), 1310 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2), 1311 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SDA4, SEL_IIC4_0), 1312 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, HRTS2_N, SEL_HSCIF2_0), 1313 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0), 1314 PINMUX_IPSR_DATA(IP10_2_0, ATADIR1_N), 1315 PINMUX_IPSR_DATA(IP10_5_3, VI0_G2), 1316 PINMUX_IPSR_DATA(IP10_5_3, VI2_HSYNC_N), 1317 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, STP_ISD_0_C, SEL_SSP_2), 1318 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SCL3_B, SEL_IIC3_1), 1319 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, HSCK2, SEL_HSCIF2_0), 1320 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0), 1321 PINMUX_IPSR_DATA(IP10_5_3, ATARD1_N), 1322 PINMUX_IPSR_DATA(IP10_8_6, VI0_G3), 1323 PINMUX_IPSR_DATA(IP10_8_6, VI2_VSYNC_N), 1324 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2), 1325 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SDA3_B, SEL_IIC3_1), 1326 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, HRX2, SEL_HSCIF2_0), 1327 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0), 1328 PINMUX_IPSR_DATA(IP10_8_6, ATACS01_N), 1329 PINMUX_IPSR_DATA(IP10_11_9, VI0_G4), 1330 PINMUX_IPSR_DATA(IP10_11_9, VI2_CLKENB), 1331 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2), 1332 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, HTX2, SEL_HSCIF2_0), 1333 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0), 1334 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3), 1335 PINMUX_IPSR_DATA(IP10_14_12, VI0_G5), 1336 PINMUX_IPSR_DATA(IP10_14_12, VI2_FIELD), 1337 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2), 1338 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, FMCLK_D, SEL_FM_3), 1339 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, CAN0_TX_E, SEL_CAN0_4), 1340 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, HTX1_D, SEL_HSCIF1_3), 1341 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3), 1342 PINMUX_IPSR_DATA(IP10_16_15, VI0_G6), 1343 PINMUX_IPSR_DATA(IP10_16_15, VI2_CLK), 1344 PINMUX_IPSR_MODSEL_DATA(IP10_16_15, BPFCLK_D, SEL_FM_3), 1345 PINMUX_IPSR_DATA(IP10_18_17, VI0_G7), 1346 PINMUX_IPSR_DATA(IP10_18_17, VI2_DATA0), 1347 PINMUX_IPSR_MODSEL_DATA(IP10_18_17, FMIN_D, SEL_FM_3), 1348 PINMUX_IPSR_DATA(IP10_21_19, VI0_R0), 1349 PINMUX_IPSR_DATA(IP10_21_19, VI2_DATA1), 1350 PINMUX_IPSR_MODSEL_DATA(IP10_21_19, GLO_I0_B, SEL_GPS_1), 1351 PINMUX_IPSR_MODSEL_DATA(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2), 1352 PINMUX_IPSR_DATA(IP10_21_19, ATACS11_N), 1353 PINMUX_IPSR_DATA(IP10_24_22, VI0_R1), 1354 PINMUX_IPSR_DATA(IP10_24_22, VI2_DATA2), 1355 PINMUX_IPSR_MODSEL_DATA(IP10_24_22, GLO_I1_B, SEL_GPS_1), 1356 PINMUX_IPSR_MODSEL_DATA(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2), 1357 PINMUX_IPSR_DATA(IP10_24_22, ATAG1_N), 1358 PINMUX_IPSR_DATA(IP10_26_25, VI0_R2), 1359 PINMUX_IPSR_DATA(IP10_26_25, VI2_DATA3), 1360 PINMUX_IPSR_MODSEL_DATA(IP10_26_25, GLO_Q0_B, SEL_GPS_1), 1361 PINMUX_IPSR_MODSEL_DATA(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2), 1362 PINMUX_IPSR_DATA(IP10_28_27, VI0_R3), 1363 PINMUX_IPSR_DATA(IP10_28_27, VI2_DATA4), 1364 PINMUX_IPSR_MODSEL_DATA(IP10_28_27, GLO_Q1_B, SEL_GPS_1), 1365 PINMUX_IPSR_MODSEL_DATA(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2), 1366 PINMUX_IPSR_DATA(IP10_31_29, VI0_R4), 1367 PINMUX_IPSR_DATA(IP10_31_29, VI2_DATA5), 1368 PINMUX_IPSR_MODSEL_DATA(IP10_31_29, GLO_SCLK_B, SEL_GPS_1), 1369 PINMUX_IPSR_MODSEL_DATA(IP10_31_29, TX0_C, SEL_SCIF0_2), 1370 PINMUX_IPSR_MODSEL_DATA(IP10_31_29, SCL1_D, SEL_IIC1_3), 1371 1372 /* IPSR11 */ 1373 PINMUX_IPSR_DATA(IP11_2_0, VI0_R5), 1374 PINMUX_IPSR_DATA(IP11_2_0, VI2_DATA6), 1375 PINMUX_IPSR_MODSEL_DATA(IP11_2_0, GLO_SDATA_B, SEL_GPS_1), 1376 PINMUX_IPSR_MODSEL_DATA(IP11_2_0, RX0_C, SEL_SCIF0_2), 1377 PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SDA1_D, SEL_IIC1_3), 1378 PINMUX_IPSR_DATA(IP11_5_3, VI0_R6), 1379 PINMUX_IPSR_DATA(IP11_5_3, VI2_DATA7), 1380 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, GLO_SS_B, SEL_GPS_1), 1381 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, TX1_C, SEL_SCIF1_2), 1382 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCL4_B, SEL_IIC4_1), 1383 PINMUX_IPSR_DATA(IP11_8_6, VI0_R7), 1384 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, GLO_RFON_B, SEL_GPS_1), 1385 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, RX1_C, SEL_SCIF1_2), 1386 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, CAN0_RX_E, SEL_CAN0_4), 1387 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SDA4_B, SEL_IIC4_1), 1388 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, HRX1_D, SEL_HSCIF1_3), 1389 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3), 1390 PINMUX_IPSR_MODSEL_DATA(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0), 1391 PINMUX_IPSR_DATA(IP11_11_9, AVB_RXD0), 1392 PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1), 1393 PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TX4_B, SEL_SCIF4_1), 1394 PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1), 1395 PINMUX_IPSR_MODSEL_DATA(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0), 1396 PINMUX_IPSR_DATA(IP11_14_12, AVB_RXD1), 1397 PINMUX_IPSR_MODSEL_DATA(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1), 1398 PINMUX_IPSR_MODSEL_DATA(IP11_14_12, RX4_B, SEL_SCIF4_1), 1399 PINMUX_IPSR_MODSEL_DATA(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1), 1400 PINMUX_IPSR_MODSEL_DATA(IP11_16_15, VI1_CLKENB, SEL_VI1_0), 1401 PINMUX_IPSR_DATA(IP11_16_15, AVB_RXD2), 1402 PINMUX_IPSR_MODSEL_DATA(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1), 1403 PINMUX_IPSR_MODSEL_DATA(IP11_18_17, VI1_FIELD, SEL_VI1_0), 1404 PINMUX_IPSR_DATA(IP11_18_17, AVB_RXD3), 1405 PINMUX_IPSR_MODSEL_DATA(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1), 1406 PINMUX_IPSR_MODSEL_DATA(IP11_19, VI1_CLK, SEL_VI1_0), 1407 PINMUX_IPSR_DATA(IP11_19, AVB_RXD4), 1408 PINMUX_IPSR_MODSEL_DATA(IP11_20, VI1_DATA0, SEL_VI1_0), 1409 PINMUX_IPSR_DATA(IP11_20, AVB_RXD5), 1410 PINMUX_IPSR_MODSEL_DATA(IP11_21, VI1_DATA1, SEL_VI1_0), 1411 PINMUX_IPSR_DATA(IP11_21, AVB_RXD6), 1412 PINMUX_IPSR_MODSEL_DATA(IP11_22, VI1_DATA2, SEL_VI1_0), 1413 PINMUX_IPSR_DATA(IP11_22, AVB_RXD7), 1414 PINMUX_IPSR_MODSEL_DATA(IP11_23, VI1_DATA3, SEL_VI1_0), 1415 PINMUX_IPSR_DATA(IP11_23, AVB_RX_ER), 1416 PINMUX_IPSR_MODSEL_DATA(IP11_24, VI1_DATA4, SEL_VI1_0), 1417 PINMUX_IPSR_DATA(IP11_24, AVB_MDIO), 1418 PINMUX_IPSR_MODSEL_DATA(IP11_25, VI1_DATA5, SEL_VI1_0), 1419 PINMUX_IPSR_DATA(IP11_25, AVB_RX_DV), 1420 PINMUX_IPSR_MODSEL_DATA(IP11_26, VI1_DATA6, SEL_VI1_0), 1421 PINMUX_IPSR_DATA(IP11_26, AVB_MAGIC), 1422 PINMUX_IPSR_MODSEL_DATA(IP11_27, VI1_DATA7, SEL_VI1_0), 1423 PINMUX_IPSR_DATA(IP11_27, AVB_MDC), 1424 PINMUX_IPSR_DATA(IP11_29_28, ETH_MDIO), 1425 PINMUX_IPSR_DATA(IP11_29_28, AVB_RX_CLK), 1426 PINMUX_IPSR_MODSEL_DATA(IP11_29_28, SCL2_C, SEL_IIC2_2), 1427 PINMUX_IPSR_DATA(IP11_31_30, ETH_CRS_DV), 1428 PINMUX_IPSR_DATA(IP11_31_30, AVB_LINK), 1429 PINMUX_IPSR_MODSEL_DATA(IP11_31_30, SDA2_C, SEL_IIC2_2), 1430 1431 /* IPSR12 */ 1432 PINMUX_IPSR_DATA(IP12_1_0, ETH_RX_ER), 1433 PINMUX_IPSR_DATA(IP12_1_0, AVB_CRS), 1434 PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL3, SEL_IIC3_0), 1435 PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL7, SEL_IIC7_0), 1436 PINMUX_IPSR_DATA(IP12_3_2, ETH_RXD0), 1437 PINMUX_IPSR_DATA(IP12_3_2, AVB_PHY_INT), 1438 PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA3, SEL_IIC3_0), 1439 PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA7, SEL_IIC7_0), 1440 PINMUX_IPSR_DATA(IP12_6_4, ETH_RXD1), 1441 PINMUX_IPSR_DATA(IP12_6_4, AVB_GTXREFCLK), 1442 PINMUX_IPSR_MODSEL_DATA(IP12_6_4, CAN0_TX_C, SEL_CAN0_2), 1443 PINMUX_IPSR_MODSEL_DATA(IP12_6_4, SCL2_D, SEL_IIC2_3), 1444 PINMUX_IPSR_MODSEL_DATA(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4), 1445 PINMUX_IPSR_DATA(IP12_9_7, ETH_LINK), 1446 PINMUX_IPSR_DATA(IP12_9_7, AVB_TXD0), 1447 PINMUX_IPSR_MODSEL_DATA(IP12_9_7, CAN0_RX_C, SEL_CAN0_2), 1448 PINMUX_IPSR_MODSEL_DATA(IP12_9_7, SDA2_D, SEL_IIC2_3), 1449 PINMUX_IPSR_MODSEL_DATA(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4), 1450 PINMUX_IPSR_DATA(IP12_12_10, ETH_REFCLK), 1451 PINMUX_IPSR_DATA(IP12_12_10, AVB_TXD1), 1452 PINMUX_IPSR_MODSEL_DATA(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1), 1453 PINMUX_IPSR_MODSEL_DATA(IP12_12_10, CAN1_RX_C, SEL_CAN1_2), 1454 PINMUX_IPSR_MODSEL_DATA(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4), 1455 PINMUX_IPSR_DATA(IP12_15_13, ETH_TXD1), 1456 PINMUX_IPSR_DATA(IP12_15_13, AVB_TXD2), 1457 PINMUX_IPSR_MODSEL_DATA(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1), 1458 PINMUX_IPSR_MODSEL_DATA(IP12_15_13, CAN1_TX_C, SEL_CAN1_2), 1459 PINMUX_IPSR_MODSEL_DATA(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4), 1460 PINMUX_IPSR_DATA(IP12_17_16, ETH_TX_EN), 1461 PINMUX_IPSR_DATA(IP12_17_16, AVB_TXD3), 1462 PINMUX_IPSR_MODSEL_DATA(IP12_17_16, TCLK1_B, SEL_TMU1_0), 1463 PINMUX_IPSR_MODSEL_DATA(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1), 1464 PINMUX_IPSR_DATA(IP12_19_18, ETH_MAGIC), 1465 PINMUX_IPSR_DATA(IP12_19_18, AVB_TXD4), 1466 PINMUX_IPSR_MODSEL_DATA(IP12_19_18, IETX_C, SEL_IEB_2), 1467 PINMUX_IPSR_DATA(IP12_21_20, ETH_TXD0), 1468 PINMUX_IPSR_DATA(IP12_21_20, AVB_TXD5), 1469 PINMUX_IPSR_MODSEL_DATA(IP12_21_20, IECLK_C, SEL_IEB_2), 1470 PINMUX_IPSR_DATA(IP12_23_22, ETH_MDC), 1471 PINMUX_IPSR_DATA(IP12_23_22, AVB_TXD6), 1472 PINMUX_IPSR_MODSEL_DATA(IP12_23_22, IERX_C, SEL_IEB_2), 1473 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0), 1474 PINMUX_IPSR_DATA(IP12_26_24, AVB_TXD7), 1475 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3), 1476 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ADIDATA_B, SEL_RAD_1), 1477 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2), 1478 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, STP_ISCLK_0, SEL_SSP_0), 1479 PINMUX_IPSR_DATA(IP12_29_27, AVB_TX_EN), 1480 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3), 1481 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1), 1482 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2), 1483 1484 /* IPSR13 */ 1485 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, STP_ISD_0, SEL_SSP_0), 1486 PINMUX_IPSR_DATA(IP13_2_0, AVB_TX_ER), 1487 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2), 1488 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, ADICLK_B, SEL_RAD_1), 1489 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2), 1490 PINMUX_IPSR_MODSEL_DATA(IP13_4_3, STP_ISEN_0, SEL_SSP_0), 1491 PINMUX_IPSR_DATA(IP13_4_3, AVB_TX_CLK), 1492 PINMUX_IPSR_MODSEL_DATA(IP13_4_3, ADICHS0_B, SEL_RAD_1), 1493 PINMUX_IPSR_MODSEL_DATA(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2), 1494 PINMUX_IPSR_MODSEL_DATA(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0), 1495 PINMUX_IPSR_DATA(IP13_6_5, AVB_COL), 1496 PINMUX_IPSR_MODSEL_DATA(IP13_6_5, ADICHS1_B, SEL_RAD_1), 1497 PINMUX_IPSR_MODSEL_DATA(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2), 1498 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, STP_OPWM_0, SEL_SSP_0), 1499 PINMUX_IPSR_DATA(IP13_9_7, AVB_GTX_CLK), 1500 PINMUX_IPSR_DATA(IP13_9_7, PWM0_B), 1501 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, ADICHS2_B, SEL_RAD_1), 1502 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2), 1503 PINMUX_IPSR_DATA(IP13_10, SD0_CLK), 1504 PINMUX_IPSR_MODSEL_DATA(IP13_10, SPCLK_B, SEL_QSP_1), 1505 PINMUX_IPSR_DATA(IP13_11, SD0_CMD), 1506 PINMUX_IPSR_MODSEL_DATA(IP13_11, MOSI_IO0_B, SEL_QSP_1), 1507 PINMUX_IPSR_DATA(IP13_12, SD0_DATA0), 1508 PINMUX_IPSR_MODSEL_DATA(IP13_12, MISO_IO1_B, SEL_QSP_1), 1509 PINMUX_IPSR_DATA(IP13_13, SD0_DATA1), 1510 PINMUX_IPSR_MODSEL_DATA(IP13_13, IO2_B, SEL_QSP_1), 1511 PINMUX_IPSR_DATA(IP13_14, SD0_DATA2), 1512 PINMUX_IPSR_MODSEL_DATA(IP13_14, IO3_B, SEL_QSP_1), 1513 PINMUX_IPSR_DATA(IP13_15, SD0_DATA3), 1514 PINMUX_IPSR_MODSEL_DATA(IP13_15, SSL_B, SEL_QSP_1), 1515 PINMUX_IPSR_DATA(IP13_18_16, SD0_CD), 1516 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, MMC_D6_B, SEL_MMC_1), 1517 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SIM0_RST_B, SEL_SIM_1), 1518 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, CAN0_RX_F, SEL_CAN0_5), 1519 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1), 1520 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, TX3_C, SEL_SCIF3_2), 1521 PINMUX_IPSR_DATA(IP13_21_19, SD0_WP), 1522 PINMUX_IPSR_MODSEL_DATA(IP13_21_19, MMC_D7_B, SEL_MMC_1), 1523 PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SIM0_D_B, SEL_SIM_1), 1524 PINMUX_IPSR_MODSEL_DATA(IP13_21_19, CAN0_TX_F, SEL_CAN0_5), 1525 PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1), 1526 PINMUX_IPSR_MODSEL_DATA(IP13_21_19, RX3_C, SEL_SCIF3_2), 1527 PINMUX_IPSR_DATA(IP13_22, SD1_CMD), 1528 PINMUX_IPSR_MODSEL_DATA(IP13_22, REMOCON_B, SEL_RCN_1), 1529 PINMUX_IPSR_DATA(IP13_24_23, SD1_DATA0), 1530 PINMUX_IPSR_MODSEL_DATA(IP13_24_23, SPEEDIN_B, SEL_RSP_1), 1531 PINMUX_IPSR_DATA(IP13_25, SD1_DATA1), 1532 PINMUX_IPSR_MODSEL_DATA(IP13_25, IETX_B, SEL_IEB_1), 1533 PINMUX_IPSR_DATA(IP13_26, SD1_DATA2), 1534 PINMUX_IPSR_MODSEL_DATA(IP13_26, IECLK_B, SEL_IEB_1), 1535 PINMUX_IPSR_DATA(IP13_27, SD1_DATA3), 1536 PINMUX_IPSR_MODSEL_DATA(IP13_27, IERX_B, SEL_IEB_1), 1537 PINMUX_IPSR_DATA(IP13_30_28, SD1_CD), 1538 PINMUX_IPSR_DATA(IP13_30_28, PWM0), 1539 PINMUX_IPSR_DATA(IP13_30_28, TPU_TO0), 1540 PINMUX_IPSR_MODSEL_DATA(IP13_30_28, SCL1_C, SEL_IIC1_2), 1541 1542 /* IPSR14 */ 1543 PINMUX_IPSR_DATA(IP14_1_0, SD1_WP), 1544 PINMUX_IPSR_DATA(IP14_1_0, PWM1_B), 1545 PINMUX_IPSR_MODSEL_DATA(IP14_1_0, SDA1_C, SEL_IIC1_2), 1546 PINMUX_IPSR_DATA(IP14_2, SD2_CLK), 1547 PINMUX_IPSR_DATA(IP14_2, MMC_CLK), 1548 PINMUX_IPSR_DATA(IP14_3, SD2_CMD), 1549 PINMUX_IPSR_DATA(IP14_3, MMC_CMD), 1550 PINMUX_IPSR_DATA(IP14_4, SD2_DATA0), 1551 PINMUX_IPSR_DATA(IP14_4, MMC_D0), 1552 PINMUX_IPSR_DATA(IP14_5, SD2_DATA1), 1553 PINMUX_IPSR_DATA(IP14_5, MMC_D1), 1554 PINMUX_IPSR_DATA(IP14_6, SD2_DATA2), 1555 PINMUX_IPSR_DATA(IP14_6, MMC_D2), 1556 PINMUX_IPSR_DATA(IP14_7, SD2_DATA3), 1557 PINMUX_IPSR_DATA(IP14_7, MMC_D3), 1558 PINMUX_IPSR_DATA(IP14_10_8, SD2_CD), 1559 PINMUX_IPSR_DATA(IP14_10_8, MMC_D4), 1560 PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCL8_C, SEL_IIC8_2), 1561 PINMUX_IPSR_MODSEL_DATA(IP14_10_8, TX5_B, SEL_SCIF5_1), 1562 PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2), 1563 PINMUX_IPSR_DATA(IP14_13_11, SD2_WP), 1564 PINMUX_IPSR_DATA(IP14_13_11, MMC_D5), 1565 PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SDA8_C, SEL_IIC8_2), 1566 PINMUX_IPSR_MODSEL_DATA(IP14_13_11, RX5_B, SEL_SCIF5_1), 1567 PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2), 1568 PINMUX_IPSR_MODSEL_DATA(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0), 1569 PINMUX_IPSR_MODSEL_DATA(IP14_16_14, RX2_C, SEL_SCIF2_2), 1570 PINMUX_IPSR_MODSEL_DATA(IP14_16_14, ADIDATA, SEL_RAD_0), 1571 PINMUX_IPSR_MODSEL_DATA(IP14_16_14, VI1_CLK_C, SEL_VI1_2), 1572 PINMUX_IPSR_DATA(IP14_16_14, VI1_G0_B), 1573 PINMUX_IPSR_MODSEL_DATA(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0), 1574 PINMUX_IPSR_MODSEL_DATA(IP14_19_17, TX2_C, SEL_SCIF2_2), 1575 PINMUX_IPSR_MODSEL_DATA(IP14_19_17, ADICS_SAMP, SEL_RAD_0), 1576 PINMUX_IPSR_MODSEL_DATA(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2), 1577 PINMUX_IPSR_DATA(IP14_19_17, VI1_G1_B), 1578 PINMUX_IPSR_MODSEL_DATA(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0), 1579 PINMUX_IPSR_MODSEL_DATA(IP14_22_20, ADICLK, SEL_RAD_0), 1580 PINMUX_IPSR_MODSEL_DATA(IP14_22_20, VI1_FIELD_C, SEL_VI1_2), 1581 PINMUX_IPSR_DATA(IP14_22_20, VI1_G2_B), 1582 PINMUX_IPSR_MODSEL_DATA(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0), 1583 PINMUX_IPSR_MODSEL_DATA(IP14_25_23, ADICHS0, SEL_RAD_0), 1584 PINMUX_IPSR_MODSEL_DATA(IP14_25_23, VI1_DATA0_C, SEL_VI1_2), 1585 PINMUX_IPSR_DATA(IP14_25_23, VI1_G3_B), 1586 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0), 1587 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MMC_D6, SEL_MMC_0), 1588 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, ADICHS1, SEL_RAD_0), 1589 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, TX0_E, SEL_SCIF0_4), 1590 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2), 1591 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, SCL7_C, SEL_IIC7_2), 1592 PINMUX_IPSR_DATA(IP14_28_26, VI1_G4_B), 1593 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0), 1594 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MMC_D7, SEL_MMC_0), 1595 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, ADICHS2, SEL_RAD_0), 1596 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, RX0_E, SEL_SCIF0_4), 1597 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2), 1598 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, SDA7_C, SEL_IIC7_2), 1599 PINMUX_IPSR_DATA(IP14_31_29, VI1_G5_B), 1600 1601 /* IPSR15 */ 1602 PINMUX_IPSR_MODSEL_DATA(IP15_1_0, SIM0_RST, SEL_SIM_0), 1603 PINMUX_IPSR_MODSEL_DATA(IP15_1_0, IETX, SEL_IEB_0), 1604 PINMUX_IPSR_MODSEL_DATA(IP15_1_0, CAN1_TX_D, SEL_CAN1_3), 1605 PINMUX_IPSR_DATA(IP15_3_2, SIM0_CLK), 1606 PINMUX_IPSR_MODSEL_DATA(IP15_3_2, IECLK, SEL_IEB_0), 1607 PINMUX_IPSR_MODSEL_DATA(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2), 1608 PINMUX_IPSR_MODSEL_DATA(IP15_5_4, SIM0_D, SEL_SIM_0), 1609 PINMUX_IPSR_MODSEL_DATA(IP15_5_4, IERX, SEL_IEB_0), 1610 PINMUX_IPSR_MODSEL_DATA(IP15_5_4, CAN1_RX_D, SEL_CAN1_3), 1611 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, GPS_CLK, SEL_GPS_0), 1612 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2), 1613 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1), 1614 PINMUX_IPSR_DATA(IP15_8_6, PWM5_B), 1615 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2), 1616 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, GPS_SIGN, SEL_GPS_0), 1617 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TX4_C, SEL_SCIF4_2), 1618 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2), 1619 PINMUX_IPSR_DATA(IP15_11_9, PWM5), 1620 PINMUX_IPSR_DATA(IP15_11_9, VI1_G6_B), 1621 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2), 1622 PINMUX_IPSR_MODSEL_DATA(IP15_14_12, GPS_MAG, SEL_GPS_0), 1623 PINMUX_IPSR_MODSEL_DATA(IP15_14_12, RX4_C, SEL_SCIF4_2), 1624 PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2), 1625 PINMUX_IPSR_DATA(IP15_14_12, PWM6), 1626 PINMUX_IPSR_DATA(IP15_14_12, VI1_G7_B), 1627 PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2), 1628 PINMUX_IPSR_MODSEL_DATA(IP15_17_15, HCTS0_N, SEL_HSCIF0_0), 1629 PINMUX_IPSR_MODSEL_DATA(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0), 1630 PINMUX_IPSR_MODSEL_DATA(IP15_17_15, GLO_I0_C, SEL_GPS_2), 1631 PINMUX_IPSR_MODSEL_DATA(IP15_17_15, TCLK1, SEL_TMU1_0), 1632 PINMUX_IPSR_MODSEL_DATA(IP15_17_15, VI1_DATA1_C, SEL_VI1_2), 1633 PINMUX_IPSR_MODSEL_DATA(IP15_20_18, HRTS0_N, SEL_HSCIF0_0), 1634 PINMUX_IPSR_MODSEL_DATA(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0), 1635 PINMUX_IPSR_MODSEL_DATA(IP15_20_18, GLO_I1_C, SEL_GPS_2), 1636 PINMUX_IPSR_MODSEL_DATA(IP15_20_18, VI1_DATA2_C, SEL_VI1_2), 1637 PINMUX_IPSR_MODSEL_DATA(IP15_23_21, HSCK0, SEL_HSCIF0_0), 1638 PINMUX_IPSR_MODSEL_DATA(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0), 1639 PINMUX_IPSR_MODSEL_DATA(IP15_23_21, GLO_Q0_C, SEL_GPS_2), 1640 PINMUX_IPSR_MODSEL_DATA(IP15_23_21, CAN_CLK, SEL_CANCLK_0), 1641 PINMUX_IPSR_DATA(IP15_23_21, TCLK2), 1642 PINMUX_IPSR_MODSEL_DATA(IP15_23_21, VI1_DATA3_C, SEL_VI1_2), 1643 PINMUX_IPSR_MODSEL_DATA(IP15_26_24, HRX0, SEL_HSCIF0_0), 1644 PINMUX_IPSR_MODSEL_DATA(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0), 1645 PINMUX_IPSR_MODSEL_DATA(IP15_26_24, GLO_Q1_C, SEL_GPS_2), 1646 PINMUX_IPSR_MODSEL_DATA(IP15_26_24, CAN0_RX_B, SEL_CAN0_1), 1647 PINMUX_IPSR_MODSEL_DATA(IP15_26_24, VI1_DATA4_C, SEL_VI1_2), 1648 PINMUX_IPSR_MODSEL_DATA(IP15_29_27, HTX0, SEL_HSCIF0_0), 1649 PINMUX_IPSR_MODSEL_DATA(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0), 1650 PINMUX_IPSR_MODSEL_DATA(IP15_29_27, GLO_SCLK_C, SEL_GPS_2), 1651 PINMUX_IPSR_MODSEL_DATA(IP15_29_27, CAN0_TX_B, SEL_CAN0_1), 1652 PINMUX_IPSR_MODSEL_DATA(IP15_29_27, VI1_DATA5_C, SEL_VI1_2), 1653 1654 /* IPSR16 */ 1655 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HRX1, SEL_HSCIF1_0), 1656 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0), 1657 PINMUX_IPSR_DATA(IP16_2_0, VI1_R0_B), 1658 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, GLO_SDATA_C, SEL_GPS_2), 1659 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, VI1_DATA6_C, SEL_VI1_2), 1660 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, HTX1, SEL_HSCIF1_0), 1661 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0), 1662 PINMUX_IPSR_DATA(IP16_5_3, VI1_R1_B), 1663 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, GLO_SS_C, SEL_GPS_2), 1664 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, VI1_DATA7_C, SEL_VI1_2), 1665 PINMUX_IPSR_MODSEL_DATA(IP16_7_6, HSCK1, SEL_HSCIF1_0), 1666 PINMUX_IPSR_MODSEL_DATA(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0), 1667 PINMUX_IPSR_DATA(IP16_7_6, MLB_CLK), 1668 PINMUX_IPSR_MODSEL_DATA(IP16_7_6, GLO_RFON_C, SEL_GPS_2), 1669 PINMUX_IPSR_MODSEL_DATA(IP16_9_8, HCTS1_N, SEL_HSCIF1_0), 1670 PINMUX_IPSR_DATA(IP16_9_8, SCIFB1_CTS_N), 1671 PINMUX_IPSR_DATA(IP16_9_8, MLB_SIG), 1672 PINMUX_IPSR_MODSEL_DATA(IP16_9_8, CAN1_TX_B, SEL_CAN1_1), 1673 PINMUX_IPSR_MODSEL_DATA(IP16_11_10, HRTS1_N, SEL_HSCIF1_0), 1674 PINMUX_IPSR_DATA(IP16_11_10, SCIFB1_RTS_N), 1675 PINMUX_IPSR_DATA(IP16_11_10, MLB_DAT), 1676 PINMUX_IPSR_MODSEL_DATA(IP16_11_10, CAN1_RX_B, SEL_CAN1_1), 1677 }; 1678 1679 static const struct sh_pfc_pin pinmux_pins[] = { 1680 PINMUX_GPIO_GP_ALL(), 1681 }; 1682 1683 /* - Audio Clock ------------------------------------------------------------ */ 1684 static const unsigned int audio_clk_a_pins[] = { 1685 /* CLK */ 1686 RCAR_GP_PIN(2, 28), 1687 }; 1688 1689 static const unsigned int audio_clk_a_mux[] = { 1690 AUDIO_CLKA_MARK, 1691 }; 1692 1693 static const unsigned int audio_clk_b_pins[] = { 1694 /* CLK */ 1695 RCAR_GP_PIN(2, 29), 1696 }; 1697 1698 static const unsigned int audio_clk_b_mux[] = { 1699 AUDIO_CLKB_MARK, 1700 }; 1701 1702 static const unsigned int audio_clk_b_b_pins[] = { 1703 /* CLK */ 1704 RCAR_GP_PIN(7, 20), 1705 }; 1706 1707 static const unsigned int audio_clk_b_b_mux[] = { 1708 AUDIO_CLKB_B_MARK, 1709 }; 1710 1711 static const unsigned int audio_clk_c_pins[] = { 1712 /* CLK */ 1713 RCAR_GP_PIN(2, 30), 1714 }; 1715 1716 static const unsigned int audio_clk_c_mux[] = { 1717 AUDIO_CLKC_MARK, 1718 }; 1719 1720 static const unsigned int audio_clkout_pins[] = { 1721 /* CLK */ 1722 RCAR_GP_PIN(2, 31), 1723 }; 1724 1725 static const unsigned int audio_clkout_mux[] = { 1726 AUDIO_CLKOUT_MARK, 1727 }; 1728 1729 /* - CAN -------------------------------------------------------------------- */ 1730 1731 static const unsigned int can0_data_pins[] = { 1732 /* TX, RX */ 1733 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29), 1734 }; 1735 1736 static const unsigned int can0_data_mux[] = { 1737 CAN0_TX_MARK, CAN0_RX_MARK, 1738 }; 1739 1740 static const unsigned int can0_data_b_pins[] = { 1741 /* TX, RX */ 1742 RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 3), 1743 }; 1744 1745 static const unsigned int can0_data_b_mux[] = { 1746 CAN0_TX_B_MARK, CAN0_RX_B_MARK, 1747 }; 1748 1749 static const unsigned int can0_data_c_pins[] = { 1750 /* TX, RX */ 1751 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18), 1752 }; 1753 1754 static const unsigned int can0_data_c_mux[] = { 1755 CAN0_TX_C_MARK, CAN0_RX_C_MARK, 1756 }; 1757 1758 static const unsigned int can0_data_d_pins[] = { 1759 /* TX, RX */ 1760 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27), 1761 }; 1762 1763 static const unsigned int can0_data_d_mux[] = { 1764 CAN0_TX_D_MARK, CAN0_RX_D_MARK, 1765 }; 1766 1767 static const unsigned int can0_data_e_pins[] = { 1768 /* TX, RX */ 1769 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 28), 1770 }; 1771 1772 static const unsigned int can0_data_e_mux[] = { 1773 CAN0_TX_E_MARK, CAN0_RX_E_MARK, 1774 }; 1775 1776 static const unsigned int can0_data_f_pins[] = { 1777 /* TX, RX */ 1778 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), 1779 }; 1780 1781 static const unsigned int can0_data_f_mux[] = { 1782 CAN0_TX_F_MARK, CAN0_RX_F_MARK, 1783 }; 1784 1785 static const unsigned int can1_data_pins[] = { 1786 /* TX, RX */ 1787 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 20), 1788 }; 1789 1790 static const unsigned int can1_data_mux[] = { 1791 CAN1_TX_MARK, CAN1_RX_MARK, 1792 }; 1793 1794 static const unsigned int can1_data_b_pins[] = { 1795 /* TX, RX */ 1796 RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9), 1797 }; 1798 1799 static const unsigned int can1_data_b_mux[] = { 1800 CAN1_TX_B_MARK, CAN1_RX_B_MARK, 1801 }; 1802 1803 static const unsigned int can1_data_c_pins[] = { 1804 /* TX, RX */ 1805 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 19), 1806 }; 1807 1808 static const unsigned int can1_data_c_mux[] = { 1809 CAN1_TX_C_MARK, CAN1_RX_C_MARK, 1810 }; 1811 1812 static const unsigned int can1_data_d_pins[] = { 1813 /* TX, RX */ 1814 RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 31), 1815 }; 1816 1817 static const unsigned int can1_data_d_mux[] = { 1818 CAN1_TX_D_MARK, CAN1_RX_D_MARK, 1819 }; 1820 1821 static const unsigned int can_clk_pins[] = { 1822 /* CLK */ 1823 RCAR_GP_PIN(7, 2), 1824 }; 1825 1826 static const unsigned int can_clk_mux[] = { 1827 CAN_CLK_MARK, 1828 }; 1829 1830 static const unsigned int can_clk_b_pins[] = { 1831 /* CLK */ 1832 RCAR_GP_PIN(5, 21), 1833 }; 1834 1835 static const unsigned int can_clk_b_mux[] = { 1836 CAN_CLK_B_MARK, 1837 }; 1838 1839 static const unsigned int can_clk_c_pins[] = { 1840 /* CLK */ 1841 RCAR_GP_PIN(4, 30), 1842 }; 1843 1844 static const unsigned int can_clk_c_mux[] = { 1845 CAN_CLK_C_MARK, 1846 }; 1847 1848 static const unsigned int can_clk_d_pins[] = { 1849 /* CLK */ 1850 RCAR_GP_PIN(7, 19), 1851 }; 1852 1853 static const unsigned int can_clk_d_mux[] = { 1854 CAN_CLK_D_MARK, 1855 }; 1856 1857 /* - DU --------------------------------------------------------------------- */ 1858 static const unsigned int du_rgb666_pins[] = { 1859 /* R[7:2], G[7:2], B[7:2] */ 1860 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5), 1861 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2), 1862 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13), 1863 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10), 1864 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21), 1865 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18), 1866 }; 1867 static const unsigned int du_rgb666_mux[] = { 1868 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, 1869 DU1_DR3_MARK, DU1_DR2_MARK, 1870 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK, 1871 DU1_DG3_MARK, DU1_DG2_MARK, 1872 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK, 1873 DU1_DB3_MARK, DU1_DB2_MARK, 1874 }; 1875 static const unsigned int du_rgb888_pins[] = { 1876 /* R[7:0], G[7:0], B[7:0] */ 1877 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5), 1878 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2), 1879 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0), 1880 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13), 1881 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10), 1882 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8), 1883 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21), 1884 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18), 1885 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16), 1886 }; 1887 static const unsigned int du_rgb888_mux[] = { 1888 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, 1889 DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK, 1890 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK, 1891 DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK, 1892 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK, 1893 DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK, 1894 }; 1895 static const unsigned int du_clk_out_0_pins[] = { 1896 /* CLKOUT */ 1897 RCAR_GP_PIN(3, 25), 1898 }; 1899 static const unsigned int du_clk_out_0_mux[] = { 1900 DU1_DOTCLKOUT0_MARK 1901 }; 1902 static const unsigned int du_clk_out_1_pins[] = { 1903 /* CLKOUT */ 1904 RCAR_GP_PIN(3, 26), 1905 }; 1906 static const unsigned int du_clk_out_1_mux[] = { 1907 DU1_DOTCLKOUT1_MARK 1908 }; 1909 static const unsigned int du_sync_pins[] = { 1910 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ 1911 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27), 1912 }; 1913 static const unsigned int du_sync_mux[] = { 1914 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK 1915 }; 1916 static const unsigned int du_oddf_pins[] = { 1917 /* EXDISP/EXODDF/EXCDE */ 1918 RCAR_GP_PIN(3, 29), 1919 }; 1920 static const unsigned int du_oddf_mux[] = { 1921 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, 1922 }; 1923 static const unsigned int du_cde_pins[] = { 1924 /* CDE */ 1925 RCAR_GP_PIN(3, 31), 1926 }; 1927 static const unsigned int du_cde_mux[] = { 1928 DU1_CDE_MARK, 1929 }; 1930 static const unsigned int du_disp_pins[] = { 1931 /* DISP */ 1932 RCAR_GP_PIN(3, 30), 1933 }; 1934 static const unsigned int du_disp_mux[] = { 1935 DU1_DISP_MARK, 1936 }; 1937 static const unsigned int du0_clk_in_pins[] = { 1938 /* CLKIN */ 1939 RCAR_GP_PIN(6, 31), 1940 }; 1941 static const unsigned int du0_clk_in_mux[] = { 1942 DU0_DOTCLKIN_MARK 1943 }; 1944 static const unsigned int du1_clk_in_pins[] = { 1945 /* CLKIN */ 1946 RCAR_GP_PIN(3, 24), 1947 }; 1948 static const unsigned int du1_clk_in_mux[] = { 1949 DU1_DOTCLKIN_MARK 1950 }; 1951 static const unsigned int du1_clk_in_b_pins[] = { 1952 /* CLKIN */ 1953 RCAR_GP_PIN(7, 19), 1954 }; 1955 static const unsigned int du1_clk_in_b_mux[] = { 1956 DU1_DOTCLKIN_B_MARK, 1957 }; 1958 static const unsigned int du1_clk_in_c_pins[] = { 1959 /* CLKIN */ 1960 RCAR_GP_PIN(7, 20), 1961 }; 1962 static const unsigned int du1_clk_in_c_mux[] = { 1963 DU1_DOTCLKIN_C_MARK, 1964 }; 1965 /* - ETH -------------------------------------------------------------------- */ 1966 static const unsigned int eth_link_pins[] = { 1967 /* LINK */ 1968 RCAR_GP_PIN(5, 18), 1969 }; 1970 static const unsigned int eth_link_mux[] = { 1971 ETH_LINK_MARK, 1972 }; 1973 static const unsigned int eth_magic_pins[] = { 1974 /* MAGIC */ 1975 RCAR_GP_PIN(5, 22), 1976 }; 1977 static const unsigned int eth_magic_mux[] = { 1978 ETH_MAGIC_MARK, 1979 }; 1980 static const unsigned int eth_mdio_pins[] = { 1981 /* MDC, MDIO */ 1982 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 13), 1983 }; 1984 static const unsigned int eth_mdio_mux[] = { 1985 ETH_MDC_MARK, ETH_MDIO_MARK, 1986 }; 1987 static const unsigned int eth_rmii_pins[] = { 1988 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */ 1989 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 15), 1990 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 20), 1991 RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 19), 1992 }; 1993 static const unsigned int eth_rmii_mux[] = { 1994 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK, 1995 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK, 1996 }; 1997 1998 /* - HSCIF0 ----------------------------------------------------------------- */ 1999 static const unsigned int hscif0_data_pins[] = { 2000 /* RX, TX */ 2001 RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4), 2002 }; 2003 static const unsigned int hscif0_data_mux[] = { 2004 HRX0_MARK, HTX0_MARK, 2005 }; 2006 static const unsigned int hscif0_clk_pins[] = { 2007 /* SCK */ 2008 RCAR_GP_PIN(7, 2), 2009 }; 2010 static const unsigned int hscif0_clk_mux[] = { 2011 HSCK0_MARK, 2012 }; 2013 static const unsigned int hscif0_ctrl_pins[] = { 2014 /* RTS, CTS */ 2015 RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0), 2016 }; 2017 static const unsigned int hscif0_ctrl_mux[] = { 2018 HRTS0_N_MARK, HCTS0_N_MARK, 2019 }; 2020 static const unsigned int hscif0_data_b_pins[] = { 2021 /* RX, TX */ 2022 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15), 2023 }; 2024 static const unsigned int hscif0_data_b_mux[] = { 2025 HRX0_B_MARK, HTX0_B_MARK, 2026 }; 2027 static const unsigned int hscif0_ctrl_b_pins[] = { 2028 /* RTS, CTS */ 2029 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13), 2030 }; 2031 static const unsigned int hscif0_ctrl_b_mux[] = { 2032 HRTS0_N_B_MARK, HCTS0_N_B_MARK, 2033 }; 2034 static const unsigned int hscif0_data_c_pins[] = { 2035 /* RX, TX */ 2036 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 2037 }; 2038 static const unsigned int hscif0_data_c_mux[] = { 2039 HRX0_C_MARK, HTX0_C_MARK, 2040 }; 2041 static const unsigned int hscif0_clk_c_pins[] = { 2042 /* SCK */ 2043 RCAR_GP_PIN(5, 31), 2044 }; 2045 static const unsigned int hscif0_clk_c_mux[] = { 2046 HSCK0_C_MARK, 2047 }; 2048 /* - HSCIF1 ----------------------------------------------------------------- */ 2049 static const unsigned int hscif1_data_pins[] = { 2050 /* RX, TX */ 2051 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6), 2052 }; 2053 static const unsigned int hscif1_data_mux[] = { 2054 HRX1_MARK, HTX1_MARK, 2055 }; 2056 static const unsigned int hscif1_clk_pins[] = { 2057 /* SCK */ 2058 RCAR_GP_PIN(7, 7), 2059 }; 2060 static const unsigned int hscif1_clk_mux[] = { 2061 HSCK1_MARK, 2062 }; 2063 static const unsigned int hscif1_ctrl_pins[] = { 2064 /* RTS, CTS */ 2065 RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8), 2066 }; 2067 static const unsigned int hscif1_ctrl_mux[] = { 2068 HRTS1_N_MARK, HCTS1_N_MARK, 2069 }; 2070 static const unsigned int hscif1_data_b_pins[] = { 2071 /* RX, TX */ 2072 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), 2073 }; 2074 static const unsigned int hscif1_data_b_mux[] = { 2075 HRX1_B_MARK, HTX1_B_MARK, 2076 }; 2077 static const unsigned int hscif1_data_c_pins[] = { 2078 /* RX, TX */ 2079 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15), 2080 }; 2081 static const unsigned int hscif1_data_c_mux[] = { 2082 HRX1_C_MARK, HTX1_C_MARK, 2083 }; 2084 static const unsigned int hscif1_clk_c_pins[] = { 2085 /* SCK */ 2086 RCAR_GP_PIN(7, 16), 2087 }; 2088 static const unsigned int hscif1_clk_c_mux[] = { 2089 HSCK1_C_MARK, 2090 }; 2091 static const unsigned int hscif1_ctrl_c_pins[] = { 2092 /* RTS, CTS */ 2093 RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17), 2094 }; 2095 static const unsigned int hscif1_ctrl_c_mux[] = { 2096 HRTS1_N_C_MARK, HCTS1_N_C_MARK, 2097 }; 2098 static const unsigned int hscif1_data_d_pins[] = { 2099 /* RX, TX */ 2100 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18), 2101 }; 2102 static const unsigned int hscif1_data_d_mux[] = { 2103 HRX1_D_MARK, HTX1_D_MARK, 2104 }; 2105 static const unsigned int hscif1_data_e_pins[] = { 2106 /* RX, TX */ 2107 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15), 2108 }; 2109 static const unsigned int hscif1_data_e_mux[] = { 2110 HRX1_C_MARK, HTX1_C_MARK, 2111 }; 2112 static const unsigned int hscif1_clk_e_pins[] = { 2113 /* SCK */ 2114 RCAR_GP_PIN(2, 6), 2115 }; 2116 static const unsigned int hscif1_clk_e_mux[] = { 2117 HSCK1_E_MARK, 2118 }; 2119 static const unsigned int hscif1_ctrl_e_pins[] = { 2120 /* RTS, CTS */ 2121 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7), 2122 }; 2123 static const unsigned int hscif1_ctrl_e_mux[] = { 2124 HRTS1_N_E_MARK, HCTS1_N_E_MARK, 2125 }; 2126 /* - HSCIF2 ----------------------------------------------------------------- */ 2127 static const unsigned int hscif2_data_pins[] = { 2128 /* RX, TX */ 2129 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17), 2130 }; 2131 static const unsigned int hscif2_data_mux[] = { 2132 HRX2_MARK, HTX2_MARK, 2133 }; 2134 static const unsigned int hscif2_clk_pins[] = { 2135 /* SCK */ 2136 RCAR_GP_PIN(4, 15), 2137 }; 2138 static const unsigned int hscif2_clk_mux[] = { 2139 HSCK2_MARK, 2140 }; 2141 static const unsigned int hscif2_ctrl_pins[] = { 2142 /* RTS, CTS */ 2143 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), 2144 }; 2145 static const unsigned int hscif2_ctrl_mux[] = { 2146 HRTS2_N_MARK, HCTS2_N_MARK, 2147 }; 2148 static const unsigned int hscif2_data_b_pins[] = { 2149 /* RX, TX */ 2150 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 22), 2151 }; 2152 static const unsigned int hscif2_data_b_mux[] = { 2153 HRX2_B_MARK, HTX2_B_MARK, 2154 }; 2155 static const unsigned int hscif2_ctrl_b_pins[] = { 2156 /* RTS, CTS */ 2157 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 21), 2158 }; 2159 static const unsigned int hscif2_ctrl_b_mux[] = { 2160 HRTS2_N_B_MARK, HCTS2_N_B_MARK, 2161 }; 2162 static const unsigned int hscif2_data_c_pins[] = { 2163 /* RX, TX */ 2164 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 2165 }; 2166 static const unsigned int hscif2_data_c_mux[] = { 2167 HRX2_C_MARK, HTX2_C_MARK, 2168 }; 2169 static const unsigned int hscif2_clk_c_pins[] = { 2170 /* SCK */ 2171 RCAR_GP_PIN(5, 31), 2172 }; 2173 static const unsigned int hscif2_clk_c_mux[] = { 2174 HSCK2_C_MARK, 2175 }; 2176 static const unsigned int hscif2_data_d_pins[] = { 2177 /* RX, TX */ 2178 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(5, 31), 2179 }; 2180 static const unsigned int hscif2_data_d_mux[] = { 2181 HRX2_B_MARK, HTX2_D_MARK, 2182 }; 2183 /* - I2C0 ------------------------------------------------------------------- */ 2184 static const unsigned int i2c0_pins[] = { 2185 /* SCL, SDA */ 2186 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), 2187 }; 2188 static const unsigned int i2c0_mux[] = { 2189 SCL0_MARK, SDA0_MARK, 2190 }; 2191 static const unsigned int i2c0_b_pins[] = { 2192 /* SCL, SDA */ 2193 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 2194 }; 2195 static const unsigned int i2c0_b_mux[] = { 2196 SCL0_B_MARK, SDA0_B_MARK, 2197 }; 2198 static const unsigned int i2c0_c_pins[] = { 2199 /* SCL, SDA */ 2200 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(1, 1), 2201 }; 2202 static const unsigned int i2c0_c_mux[] = { 2203 SCL0_C_MARK, SDA0_C_MARK, 2204 }; 2205 /* - I2C1 ------------------------------------------------------------------- */ 2206 static const unsigned int i2c1_pins[] = { 2207 /* SCL, SDA */ 2208 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11), 2209 }; 2210 static const unsigned int i2c1_mux[] = { 2211 SCL1_MARK, SDA1_MARK, 2212 }; 2213 static const unsigned int i2c1_b_pins[] = { 2214 /* SCL, SDA */ 2215 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 2216 }; 2217 static const unsigned int i2c1_b_mux[] = { 2218 SCL1_B_MARK, SDA1_B_MARK, 2219 }; 2220 static const unsigned int i2c1_c_pins[] = { 2221 /* SCL, SDA */ 2222 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), 2223 }; 2224 static const unsigned int i2c1_c_mux[] = { 2225 SCL1_C_MARK, SDA1_C_MARK, 2226 }; 2227 static const unsigned int i2c1_d_pins[] = { 2228 /* SCL, SDA */ 2229 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), 2230 }; 2231 static const unsigned int i2c1_d_mux[] = { 2232 SCL1_D_MARK, SDA1_D_MARK, 2233 }; 2234 static const unsigned int i2c1_e_pins[] = { 2235 /* SCL, SDA */ 2236 RCAR_GP_PIN(7, 15), RCAR_GP_PIN(7, 16), 2237 }; 2238 static const unsigned int i2c1_e_mux[] = { 2239 SCL1_E_MARK, SDA1_E_MARK, 2240 }; 2241 /* - I2C2 ------------------------------------------------------------------- */ 2242 static const unsigned int i2c2_pins[] = { 2243 /* SCL, SDA */ 2244 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 2245 }; 2246 static const unsigned int i2c2_mux[] = { 2247 SCL2_MARK, SDA2_MARK, 2248 }; 2249 static const unsigned int i2c2_b_pins[] = { 2250 /* SCL, SDA */ 2251 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29), 2252 }; 2253 static const unsigned int i2c2_b_mux[] = { 2254 SCL2_B_MARK, SDA2_B_MARK, 2255 }; 2256 static const unsigned int i2c2_c_pins[] = { 2257 /* SCL, SDA */ 2258 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), 2259 }; 2260 static const unsigned int i2c2_c_mux[] = { 2261 SCL2_C_MARK, SDA2_C_MARK, 2262 }; 2263 static const unsigned int i2c2_d_pins[] = { 2264 /* SCL, SDA */ 2265 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18), 2266 }; 2267 static const unsigned int i2c2_d_mux[] = { 2268 SCL2_D_MARK, SDA2_D_MARK, 2269 }; 2270 /* - I2C3 ------------------------------------------------------------------- */ 2271 static const unsigned int i2c3_pins[] = { 2272 /* SCL, SDA */ 2273 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 2274 }; 2275 static const unsigned int i2c3_mux[] = { 2276 SCL3_MARK, SDA3_MARK, 2277 }; 2278 static const unsigned int i2c3_b_pins[] = { 2279 /* SCL, SDA */ 2280 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), 2281 }; 2282 static const unsigned int i2c3_b_mux[] = { 2283 SCL3_B_MARK, SDA3_B_MARK, 2284 }; 2285 static const unsigned int i2c3_c_pins[] = { 2286 /* SCL, SDA */ 2287 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), 2288 }; 2289 static const unsigned int i2c3_c_mux[] = { 2290 SCL3_C_MARK, SDA3_C_MARK, 2291 }; 2292 static const unsigned int i2c3_d_pins[] = { 2293 /* SCL, SDA */ 2294 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), 2295 }; 2296 static const unsigned int i2c3_d_mux[] = { 2297 SCL3_D_MARK, SDA3_D_MARK, 2298 }; 2299 /* - I2C4 ------------------------------------------------------------------- */ 2300 static const unsigned int i2c4_pins[] = { 2301 /* SCL, SDA */ 2302 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), 2303 }; 2304 static const unsigned int i2c4_mux[] = { 2305 SCL4_MARK, SDA4_MARK, 2306 }; 2307 static const unsigned int i2c4_b_pins[] = { 2308 /* SCL, SDA */ 2309 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28), 2310 }; 2311 static const unsigned int i2c4_b_mux[] = { 2312 SCL4_B_MARK, SDA4_B_MARK, 2313 }; 2314 static const unsigned int i2c4_c_pins[] = { 2315 /* SCL, SDA */ 2316 RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14), 2317 }; 2318 static const unsigned int i2c4_c_mux[] = { 2319 SCL4_C_MARK, SDA4_C_MARK, 2320 }; 2321 /* - I2C7 ------------------------------------------------------------------- */ 2322 static const unsigned int i2c7_pins[] = { 2323 /* SCL, SDA */ 2324 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 2325 }; 2326 static const unsigned int i2c7_mux[] = { 2327 SCL7_MARK, SDA7_MARK, 2328 }; 2329 static const unsigned int i2c7_b_pins[] = { 2330 /* SCL, SDA */ 2331 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 2332 }; 2333 static const unsigned int i2c7_b_mux[] = { 2334 SCL7_B_MARK, SDA7_B_MARK, 2335 }; 2336 static const unsigned int i2c7_c_pins[] = { 2337 /* SCL, SDA */ 2338 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 2339 }; 2340 static const unsigned int i2c7_c_mux[] = { 2341 SCL7_C_MARK, SDA7_C_MARK, 2342 }; 2343 /* - I2C8 ------------------------------------------------------------------- */ 2344 static const unsigned int i2c8_pins[] = { 2345 /* SCL, SDA */ 2346 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), 2347 }; 2348 static const unsigned int i2c8_mux[] = { 2349 SCL8_MARK, SDA8_MARK, 2350 }; 2351 static const unsigned int i2c8_b_pins[] = { 2352 /* SCL, SDA */ 2353 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 2354 }; 2355 static const unsigned int i2c8_b_mux[] = { 2356 SCL8_B_MARK, SDA8_B_MARK, 2357 }; 2358 static const unsigned int i2c8_c_pins[] = { 2359 /* SCL, SDA */ 2360 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23), 2361 }; 2362 static const unsigned int i2c8_c_mux[] = { 2363 SCL8_C_MARK, SDA8_C_MARK, 2364 }; 2365 /* - INTC ------------------------------------------------------------------- */ 2366 static const unsigned int intc_irq0_pins[] = { 2367 /* IRQ */ 2368 RCAR_GP_PIN(7, 10), 2369 }; 2370 static const unsigned int intc_irq0_mux[] = { 2371 IRQ0_MARK, 2372 }; 2373 static const unsigned int intc_irq1_pins[] = { 2374 /* IRQ */ 2375 RCAR_GP_PIN(7, 11), 2376 }; 2377 static const unsigned int intc_irq1_mux[] = { 2378 IRQ1_MARK, 2379 }; 2380 static const unsigned int intc_irq2_pins[] = { 2381 /* IRQ */ 2382 RCAR_GP_PIN(7, 12), 2383 }; 2384 static const unsigned int intc_irq2_mux[] = { 2385 IRQ2_MARK, 2386 }; 2387 static const unsigned int intc_irq3_pins[] = { 2388 /* IRQ */ 2389 RCAR_GP_PIN(7, 13), 2390 }; 2391 static const unsigned int intc_irq3_mux[] = { 2392 IRQ3_MARK, 2393 }; 2394 /* - MLB+ ------------------------------------------------------------------- */ 2395 static const unsigned int mlb_3pin_pins[] = { 2396 RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9), 2397 }; 2398 static const unsigned int mlb_3pin_mux[] = { 2399 MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, 2400 }; 2401 /* - MMCIF ------------------------------------------------------------------ */ 2402 static const unsigned int mmc_data1_pins[] = { 2403 /* D[0] */ 2404 RCAR_GP_PIN(6, 18), 2405 }; 2406 static const unsigned int mmc_data1_mux[] = { 2407 MMC_D0_MARK, 2408 }; 2409 static const unsigned int mmc_data4_pins[] = { 2410 /* D[0:3] */ 2411 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), 2412 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), 2413 }; 2414 static const unsigned int mmc_data4_mux[] = { 2415 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, 2416 }; 2417 static const unsigned int mmc_data8_pins[] = { 2418 /* D[0:7] */ 2419 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), 2420 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), 2421 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23), 2422 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 2423 }; 2424 static const unsigned int mmc_data8_mux[] = { 2425 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, 2426 MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK, 2427 }; 2428 static const unsigned int mmc_ctrl_pins[] = { 2429 /* CLK, CMD */ 2430 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17), 2431 }; 2432 static const unsigned int mmc_ctrl_mux[] = { 2433 MMC_CLK_MARK, MMC_CMD_MARK, 2434 }; 2435 /* - MSIOF0 ----------------------------------------------------------------- */ 2436 static const unsigned int msiof0_clk_pins[] = { 2437 /* SCK */ 2438 RCAR_GP_PIN(6, 24), 2439 }; 2440 static const unsigned int msiof0_clk_mux[] = { 2441 MSIOF0_SCK_MARK, 2442 }; 2443 static const unsigned int msiof0_sync_pins[] = { 2444 /* SYNC */ 2445 RCAR_GP_PIN(6, 25), 2446 }; 2447 static const unsigned int msiof0_sync_mux[] = { 2448 MSIOF0_SYNC_MARK, 2449 }; 2450 static const unsigned int msiof0_ss1_pins[] = { 2451 /* SS1 */ 2452 RCAR_GP_PIN(6, 28), 2453 }; 2454 static const unsigned int msiof0_ss1_mux[] = { 2455 MSIOF0_SS1_MARK, 2456 }; 2457 static const unsigned int msiof0_ss2_pins[] = { 2458 /* SS2 */ 2459 RCAR_GP_PIN(6, 29), 2460 }; 2461 static const unsigned int msiof0_ss2_mux[] = { 2462 MSIOF0_SS2_MARK, 2463 }; 2464 static const unsigned int msiof0_rx_pins[] = { 2465 /* RXD */ 2466 RCAR_GP_PIN(6, 27), 2467 }; 2468 static const unsigned int msiof0_rx_mux[] = { 2469 MSIOF0_RXD_MARK, 2470 }; 2471 static const unsigned int msiof0_tx_pins[] = { 2472 /* TXD */ 2473 RCAR_GP_PIN(6, 26), 2474 }; 2475 static const unsigned int msiof0_tx_mux[] = { 2476 MSIOF0_TXD_MARK, 2477 }; 2478 2479 static const unsigned int msiof0_clk_b_pins[] = { 2480 /* SCK */ 2481 RCAR_GP_PIN(0, 16), 2482 }; 2483 static const unsigned int msiof0_clk_b_mux[] = { 2484 MSIOF0_SCK_B_MARK, 2485 }; 2486 static const unsigned int msiof0_sync_b_pins[] = { 2487 /* SYNC */ 2488 RCAR_GP_PIN(0, 17), 2489 }; 2490 static const unsigned int msiof0_sync_b_mux[] = { 2491 MSIOF0_SYNC_B_MARK, 2492 }; 2493 static const unsigned int msiof0_ss1_b_pins[] = { 2494 /* SS1 */ 2495 RCAR_GP_PIN(0, 18), 2496 }; 2497 static const unsigned int msiof0_ss1_b_mux[] = { 2498 MSIOF0_SS1_B_MARK, 2499 }; 2500 static const unsigned int msiof0_ss2_b_pins[] = { 2501 /* SS2 */ 2502 RCAR_GP_PIN(0, 19), 2503 }; 2504 static const unsigned int msiof0_ss2_b_mux[] = { 2505 MSIOF0_SS2_B_MARK, 2506 }; 2507 static const unsigned int msiof0_rx_b_pins[] = { 2508 /* RXD */ 2509 RCAR_GP_PIN(0, 21), 2510 }; 2511 static const unsigned int msiof0_rx_b_mux[] = { 2512 MSIOF0_RXD_B_MARK, 2513 }; 2514 static const unsigned int msiof0_tx_b_pins[] = { 2515 /* TXD */ 2516 RCAR_GP_PIN(0, 20), 2517 }; 2518 static const unsigned int msiof0_tx_b_mux[] = { 2519 MSIOF0_TXD_B_MARK, 2520 }; 2521 2522 static const unsigned int msiof0_clk_c_pins[] = { 2523 /* SCK */ 2524 RCAR_GP_PIN(5, 26), 2525 }; 2526 static const unsigned int msiof0_clk_c_mux[] = { 2527 MSIOF0_SCK_C_MARK, 2528 }; 2529 static const unsigned int msiof0_sync_c_pins[] = { 2530 /* SYNC */ 2531 RCAR_GP_PIN(5, 25), 2532 }; 2533 static const unsigned int msiof0_sync_c_mux[] = { 2534 MSIOF0_SYNC_C_MARK, 2535 }; 2536 static const unsigned int msiof0_ss1_c_pins[] = { 2537 /* SS1 */ 2538 RCAR_GP_PIN(5, 27), 2539 }; 2540 static const unsigned int msiof0_ss1_c_mux[] = { 2541 MSIOF0_SS1_C_MARK, 2542 }; 2543 static const unsigned int msiof0_ss2_c_pins[] = { 2544 /* SS2 */ 2545 RCAR_GP_PIN(5, 28), 2546 }; 2547 static const unsigned int msiof0_ss2_c_mux[] = { 2548 MSIOF0_SS2_C_MARK, 2549 }; 2550 static const unsigned int msiof0_rx_c_pins[] = { 2551 /* RXD */ 2552 RCAR_GP_PIN(5, 29), 2553 }; 2554 static const unsigned int msiof0_rx_c_mux[] = { 2555 MSIOF0_RXD_C_MARK, 2556 }; 2557 static const unsigned int msiof0_tx_c_pins[] = { 2558 /* TXD */ 2559 RCAR_GP_PIN(5, 30), 2560 }; 2561 static const unsigned int msiof0_tx_c_mux[] = { 2562 MSIOF0_TXD_C_MARK, 2563 }; 2564 /* - MSIOF1 ----------------------------------------------------------------- */ 2565 static const unsigned int msiof1_clk_pins[] = { 2566 /* SCK */ 2567 RCAR_GP_PIN(0, 22), 2568 }; 2569 static const unsigned int msiof1_clk_mux[] = { 2570 MSIOF1_SCK_MARK, 2571 }; 2572 static const unsigned int msiof1_sync_pins[] = { 2573 /* SYNC */ 2574 RCAR_GP_PIN(0, 23), 2575 }; 2576 static const unsigned int msiof1_sync_mux[] = { 2577 MSIOF1_SYNC_MARK, 2578 }; 2579 static const unsigned int msiof1_ss1_pins[] = { 2580 /* SS1 */ 2581 RCAR_GP_PIN(0, 24), 2582 }; 2583 static const unsigned int msiof1_ss1_mux[] = { 2584 MSIOF1_SS1_MARK, 2585 }; 2586 static const unsigned int msiof1_ss2_pins[] = { 2587 /* SS2 */ 2588 RCAR_GP_PIN(0, 25), 2589 }; 2590 static const unsigned int msiof1_ss2_mux[] = { 2591 MSIOF1_SS2_MARK, 2592 }; 2593 static const unsigned int msiof1_rx_pins[] = { 2594 /* RXD */ 2595 RCAR_GP_PIN(0, 27), 2596 }; 2597 static const unsigned int msiof1_rx_mux[] = { 2598 MSIOF1_RXD_MARK, 2599 }; 2600 static const unsigned int msiof1_tx_pins[] = { 2601 /* TXD */ 2602 RCAR_GP_PIN(0, 26), 2603 }; 2604 static const unsigned int msiof1_tx_mux[] = { 2605 MSIOF1_TXD_MARK, 2606 }; 2607 2608 static const unsigned int msiof1_clk_b_pins[] = { 2609 /* SCK */ 2610 RCAR_GP_PIN(2, 29), 2611 }; 2612 static const unsigned int msiof1_clk_b_mux[] = { 2613 MSIOF1_SCK_B_MARK, 2614 }; 2615 static const unsigned int msiof1_sync_b_pins[] = { 2616 /* SYNC */ 2617 RCAR_GP_PIN(2, 30), 2618 }; 2619 static const unsigned int msiof1_sync_b_mux[] = { 2620 MSIOF1_SYNC_B_MARK, 2621 }; 2622 static const unsigned int msiof1_ss1_b_pins[] = { 2623 /* SS1 */ 2624 RCAR_GP_PIN(2, 31), 2625 }; 2626 static const unsigned int msiof1_ss1_b_mux[] = { 2627 MSIOF1_SS1_B_MARK, 2628 }; 2629 static const unsigned int msiof1_ss2_b_pins[] = { 2630 /* SS2 */ 2631 RCAR_GP_PIN(7, 16), 2632 }; 2633 static const unsigned int msiof1_ss2_b_mux[] = { 2634 MSIOF1_SS2_B_MARK, 2635 }; 2636 static const unsigned int msiof1_rx_b_pins[] = { 2637 /* RXD */ 2638 RCAR_GP_PIN(7, 18), 2639 }; 2640 static const unsigned int msiof1_rx_b_mux[] = { 2641 MSIOF1_RXD_B_MARK, 2642 }; 2643 static const unsigned int msiof1_tx_b_pins[] = { 2644 /* TXD */ 2645 RCAR_GP_PIN(7, 17), 2646 }; 2647 static const unsigned int msiof1_tx_b_mux[] = { 2648 MSIOF1_TXD_B_MARK, 2649 }; 2650 2651 static const unsigned int msiof1_clk_c_pins[] = { 2652 /* SCK */ 2653 RCAR_GP_PIN(2, 15), 2654 }; 2655 static const unsigned int msiof1_clk_c_mux[] = { 2656 MSIOF1_SCK_C_MARK, 2657 }; 2658 static const unsigned int msiof1_sync_c_pins[] = { 2659 /* SYNC */ 2660 RCAR_GP_PIN(2, 16), 2661 }; 2662 static const unsigned int msiof1_sync_c_mux[] = { 2663 MSIOF1_SYNC_C_MARK, 2664 }; 2665 static const unsigned int msiof1_rx_c_pins[] = { 2666 /* RXD */ 2667 RCAR_GP_PIN(2, 18), 2668 }; 2669 static const unsigned int msiof1_rx_c_mux[] = { 2670 MSIOF1_RXD_C_MARK, 2671 }; 2672 static const unsigned int msiof1_tx_c_pins[] = { 2673 /* TXD */ 2674 RCAR_GP_PIN(2, 17), 2675 }; 2676 static const unsigned int msiof1_tx_c_mux[] = { 2677 MSIOF1_TXD_C_MARK, 2678 }; 2679 2680 static const unsigned int msiof1_clk_d_pins[] = { 2681 /* SCK */ 2682 RCAR_GP_PIN(0, 28), 2683 }; 2684 static const unsigned int msiof1_clk_d_mux[] = { 2685 MSIOF1_SCK_D_MARK, 2686 }; 2687 static const unsigned int msiof1_sync_d_pins[] = { 2688 /* SYNC */ 2689 RCAR_GP_PIN(0, 30), 2690 }; 2691 static const unsigned int msiof1_sync_d_mux[] = { 2692 MSIOF1_SYNC_D_MARK, 2693 }; 2694 static const unsigned int msiof1_ss1_d_pins[] = { 2695 /* SS1 */ 2696 RCAR_GP_PIN(0, 29), 2697 }; 2698 static const unsigned int msiof1_ss1_d_mux[] = { 2699 MSIOF1_SS1_D_MARK, 2700 }; 2701 static const unsigned int msiof1_rx_d_pins[] = { 2702 /* RXD */ 2703 RCAR_GP_PIN(0, 27), 2704 }; 2705 static const unsigned int msiof1_rx_d_mux[] = { 2706 MSIOF1_RXD_D_MARK, 2707 }; 2708 static const unsigned int msiof1_tx_d_pins[] = { 2709 /* TXD */ 2710 RCAR_GP_PIN(0, 26), 2711 }; 2712 static const unsigned int msiof1_tx_d_mux[] = { 2713 MSIOF1_TXD_D_MARK, 2714 }; 2715 2716 static const unsigned int msiof1_clk_e_pins[] = { 2717 /* SCK */ 2718 RCAR_GP_PIN(5, 18), 2719 }; 2720 static const unsigned int msiof1_clk_e_mux[] = { 2721 MSIOF1_SCK_E_MARK, 2722 }; 2723 static const unsigned int msiof1_sync_e_pins[] = { 2724 /* SYNC */ 2725 RCAR_GP_PIN(5, 19), 2726 }; 2727 static const unsigned int msiof1_sync_e_mux[] = { 2728 MSIOF1_SYNC_E_MARK, 2729 }; 2730 static const unsigned int msiof1_rx_e_pins[] = { 2731 /* RXD */ 2732 RCAR_GP_PIN(5, 17), 2733 }; 2734 static const unsigned int msiof1_rx_e_mux[] = { 2735 MSIOF1_RXD_E_MARK, 2736 }; 2737 static const unsigned int msiof1_tx_e_pins[] = { 2738 /* TXD */ 2739 RCAR_GP_PIN(5, 20), 2740 }; 2741 static const unsigned int msiof1_tx_e_mux[] = { 2742 MSIOF1_TXD_E_MARK, 2743 }; 2744 /* - MSIOF2 ----------------------------------------------------------------- */ 2745 static const unsigned int msiof2_clk_pins[] = { 2746 /* SCK */ 2747 RCAR_GP_PIN(1, 13), 2748 }; 2749 static const unsigned int msiof2_clk_mux[] = { 2750 MSIOF2_SCK_MARK, 2751 }; 2752 static const unsigned int msiof2_sync_pins[] = { 2753 /* SYNC */ 2754 RCAR_GP_PIN(1, 14), 2755 }; 2756 static const unsigned int msiof2_sync_mux[] = { 2757 MSIOF2_SYNC_MARK, 2758 }; 2759 static const unsigned int msiof2_ss1_pins[] = { 2760 /* SS1 */ 2761 RCAR_GP_PIN(1, 17), 2762 }; 2763 static const unsigned int msiof2_ss1_mux[] = { 2764 MSIOF2_SS1_MARK, 2765 }; 2766 static const unsigned int msiof2_ss2_pins[] = { 2767 /* SS2 */ 2768 RCAR_GP_PIN(1, 18), 2769 }; 2770 static const unsigned int msiof2_ss2_mux[] = { 2771 MSIOF2_SS2_MARK, 2772 }; 2773 static const unsigned int msiof2_rx_pins[] = { 2774 /* RXD */ 2775 RCAR_GP_PIN(1, 16), 2776 }; 2777 static const unsigned int msiof2_rx_mux[] = { 2778 MSIOF2_RXD_MARK, 2779 }; 2780 static const unsigned int msiof2_tx_pins[] = { 2781 /* TXD */ 2782 RCAR_GP_PIN(1, 15), 2783 }; 2784 static const unsigned int msiof2_tx_mux[] = { 2785 MSIOF2_TXD_MARK, 2786 }; 2787 2788 static const unsigned int msiof2_clk_b_pins[] = { 2789 /* SCK */ 2790 RCAR_GP_PIN(3, 0), 2791 }; 2792 static const unsigned int msiof2_clk_b_mux[] = { 2793 MSIOF2_SCK_B_MARK, 2794 }; 2795 static const unsigned int msiof2_sync_b_pins[] = { 2796 /* SYNC */ 2797 RCAR_GP_PIN(3, 1), 2798 }; 2799 static const unsigned int msiof2_sync_b_mux[] = { 2800 MSIOF2_SYNC_B_MARK, 2801 }; 2802 static const unsigned int msiof2_ss1_b_pins[] = { 2803 /* SS1 */ 2804 RCAR_GP_PIN(3, 8), 2805 }; 2806 static const unsigned int msiof2_ss1_b_mux[] = { 2807 MSIOF2_SS1_B_MARK, 2808 }; 2809 static const unsigned int msiof2_ss2_b_pins[] = { 2810 /* SS2 */ 2811 RCAR_GP_PIN(3, 9), 2812 }; 2813 static const unsigned int msiof2_ss2_b_mux[] = { 2814 MSIOF2_SS2_B_MARK, 2815 }; 2816 static const unsigned int msiof2_rx_b_pins[] = { 2817 /* RXD */ 2818 RCAR_GP_PIN(3, 17), 2819 }; 2820 static const unsigned int msiof2_rx_b_mux[] = { 2821 MSIOF2_RXD_B_MARK, 2822 }; 2823 static const unsigned int msiof2_tx_b_pins[] = { 2824 /* TXD */ 2825 RCAR_GP_PIN(3, 16), 2826 }; 2827 static const unsigned int msiof2_tx_b_mux[] = { 2828 MSIOF2_TXD_B_MARK, 2829 }; 2830 2831 static const unsigned int msiof2_clk_c_pins[] = { 2832 /* SCK */ 2833 RCAR_GP_PIN(2, 2), 2834 }; 2835 static const unsigned int msiof2_clk_c_mux[] = { 2836 MSIOF2_SCK_C_MARK, 2837 }; 2838 static const unsigned int msiof2_sync_c_pins[] = { 2839 /* SYNC */ 2840 RCAR_GP_PIN(2, 3), 2841 }; 2842 static const unsigned int msiof2_sync_c_mux[] = { 2843 MSIOF2_SYNC_C_MARK, 2844 }; 2845 static const unsigned int msiof2_rx_c_pins[] = { 2846 /* RXD */ 2847 RCAR_GP_PIN(2, 5), 2848 }; 2849 static const unsigned int msiof2_rx_c_mux[] = { 2850 MSIOF2_RXD_C_MARK, 2851 }; 2852 static const unsigned int msiof2_tx_c_pins[] = { 2853 /* TXD */ 2854 RCAR_GP_PIN(2, 4), 2855 }; 2856 static const unsigned int msiof2_tx_c_mux[] = { 2857 MSIOF2_TXD_C_MARK, 2858 }; 2859 2860 static const unsigned int msiof2_clk_d_pins[] = { 2861 /* SCK */ 2862 RCAR_GP_PIN(2, 14), 2863 }; 2864 static const unsigned int msiof2_clk_d_mux[] = { 2865 MSIOF2_SCK_D_MARK, 2866 }; 2867 static const unsigned int msiof2_sync_d_pins[] = { 2868 /* SYNC */ 2869 RCAR_GP_PIN(2, 15), 2870 }; 2871 static const unsigned int msiof2_sync_d_mux[] = { 2872 MSIOF2_SYNC_D_MARK, 2873 }; 2874 static const unsigned int msiof2_ss1_d_pins[] = { 2875 /* SS1 */ 2876 RCAR_GP_PIN(2, 17), 2877 }; 2878 static const unsigned int msiof2_ss1_d_mux[] = { 2879 MSIOF2_SS1_D_MARK, 2880 }; 2881 static const unsigned int msiof2_ss2_d_pins[] = { 2882 /* SS2 */ 2883 RCAR_GP_PIN(2, 19), 2884 }; 2885 static const unsigned int msiof2_ss2_d_mux[] = { 2886 MSIOF2_SS2_D_MARK, 2887 }; 2888 static const unsigned int msiof2_rx_d_pins[] = { 2889 /* RXD */ 2890 RCAR_GP_PIN(2, 18), 2891 }; 2892 static const unsigned int msiof2_rx_d_mux[] = { 2893 MSIOF2_RXD_D_MARK, 2894 }; 2895 static const unsigned int msiof2_tx_d_pins[] = { 2896 /* TXD */ 2897 RCAR_GP_PIN(2, 16), 2898 }; 2899 static const unsigned int msiof2_tx_d_mux[] = { 2900 MSIOF2_TXD_D_MARK, 2901 }; 2902 2903 static const unsigned int msiof2_clk_e_pins[] = { 2904 /* SCK */ 2905 RCAR_GP_PIN(7, 15), 2906 }; 2907 static const unsigned int msiof2_clk_e_mux[] = { 2908 MSIOF2_SCK_E_MARK, 2909 }; 2910 static const unsigned int msiof2_sync_e_pins[] = { 2911 /* SYNC */ 2912 RCAR_GP_PIN(7, 16), 2913 }; 2914 static const unsigned int msiof2_sync_e_mux[] = { 2915 MSIOF2_SYNC_E_MARK, 2916 }; 2917 static const unsigned int msiof2_rx_e_pins[] = { 2918 /* RXD */ 2919 RCAR_GP_PIN(7, 14), 2920 }; 2921 static const unsigned int msiof2_rx_e_mux[] = { 2922 MSIOF2_RXD_E_MARK, 2923 }; 2924 static const unsigned int msiof2_tx_e_pins[] = { 2925 /* TXD */ 2926 RCAR_GP_PIN(7, 13), 2927 }; 2928 static const unsigned int msiof2_tx_e_mux[] = { 2929 MSIOF2_TXD_E_MARK, 2930 }; 2931 /* - QSPI ------------------------------------------------------------------- */ 2932 static const unsigned int qspi_ctrl_pins[] = { 2933 /* SPCLK, SSL */ 2934 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9), 2935 }; 2936 static const unsigned int qspi_ctrl_mux[] = { 2937 SPCLK_MARK, SSL_MARK, 2938 }; 2939 static const unsigned int qspi_data2_pins[] = { 2940 /* MOSI_IO0, MISO_IO1 */ 2941 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), 2942 }; 2943 static const unsigned int qspi_data2_mux[] = { 2944 MOSI_IO0_MARK, MISO_IO1_MARK, 2945 }; 2946 static const unsigned int qspi_data4_pins[] = { 2947 /* MOSI_IO0, MISO_IO1, IO2, IO3 */ 2948 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 2949 RCAR_GP_PIN(1, 8), 2950 }; 2951 static const unsigned int qspi_data4_mux[] = { 2952 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, 2953 }; 2954 2955 static const unsigned int qspi_ctrl_b_pins[] = { 2956 /* SPCLK, SSL */ 2957 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5), 2958 }; 2959 static const unsigned int qspi_ctrl_b_mux[] = { 2960 SPCLK_B_MARK, SSL_B_MARK, 2961 }; 2962 static const unsigned int qspi_data2_b_pins[] = { 2963 /* MOSI_IO0, MISO_IO1 */ 2964 RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), 2965 }; 2966 static const unsigned int qspi_data2_b_mux[] = { 2967 MOSI_IO0_B_MARK, MISO_IO1_B_MARK, 2968 }; 2969 static const unsigned int qspi_data4_b_pins[] = { 2970 /* MOSI_IO0, MISO_IO1, IO2, IO3 */ 2971 RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), 2972 RCAR_GP_PIN(6, 4), 2973 }; 2974 static const unsigned int qspi_data4_b_mux[] = { 2975 SPCLK_B_MARK, MOSI_IO0_B_MARK, MISO_IO1_B_MARK, 2976 IO2_B_MARK, IO3_B_MARK, SSL_B_MARK, 2977 }; 2978 /* - SCIF0 ------------------------------------------------------------------ */ 2979 static const unsigned int scif0_data_pins[] = { 2980 /* RX, TX */ 2981 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), 2982 }; 2983 static const unsigned int scif0_data_mux[] = { 2984 RX0_MARK, TX0_MARK, 2985 }; 2986 static const unsigned int scif0_data_b_pins[] = { 2987 /* RX, TX */ 2988 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0), 2989 }; 2990 static const unsigned int scif0_data_b_mux[] = { 2991 RX0_B_MARK, TX0_B_MARK, 2992 }; 2993 static const unsigned int scif0_data_c_pins[] = { 2994 /* RX, TX */ 2995 RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 25), 2996 }; 2997 static const unsigned int scif0_data_c_mux[] = { 2998 RX0_C_MARK, TX0_C_MARK, 2999 }; 3000 static const unsigned int scif0_data_d_pins[] = { 3001 /* RX, TX */ 3002 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), 3003 }; 3004 static const unsigned int scif0_data_d_mux[] = { 3005 RX0_D_MARK, TX0_D_MARK, 3006 }; 3007 static const unsigned int scif0_data_e_pins[] = { 3008 /* RX, TX */ 3009 RCAR_GP_PIN(6, 29), RCAR_GP_PIN(6, 28), 3010 }; 3011 static const unsigned int scif0_data_e_mux[] = { 3012 RX0_E_MARK, TX0_E_MARK, 3013 }; 3014 /* - SCIF1 ------------------------------------------------------------------ */ 3015 static const unsigned int scif1_data_pins[] = { 3016 /* RX, TX */ 3017 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), 3018 }; 3019 static const unsigned int scif1_data_mux[] = { 3020 RX1_MARK, TX1_MARK, 3021 }; 3022 static const unsigned int scif1_data_b_pins[] = { 3023 /* RX, TX */ 3024 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8), 3025 }; 3026 static const unsigned int scif1_data_b_mux[] = { 3027 RX1_B_MARK, TX1_B_MARK, 3028 }; 3029 static const unsigned int scif1_clk_b_pins[] = { 3030 /* SCK */ 3031 RCAR_GP_PIN(3, 10), 3032 }; 3033 static const unsigned int scif1_clk_b_mux[] = { 3034 SCIF1_SCK_B_MARK, 3035 }; 3036 static const unsigned int scif1_data_c_pins[] = { 3037 /* RX, TX */ 3038 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27), 3039 }; 3040 static const unsigned int scif1_data_c_mux[] = { 3041 RX1_C_MARK, TX1_C_MARK, 3042 }; 3043 static const unsigned int scif1_data_d_pins[] = { 3044 /* RX, TX */ 3045 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24), 3046 }; 3047 static const unsigned int scif1_data_d_mux[] = { 3048 RX1_D_MARK, TX1_D_MARK, 3049 }; 3050 /* - SCIF2 ------------------------------------------------------------------ */ 3051 static const unsigned int scif2_data_pins[] = { 3052 /* RX, TX */ 3053 RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31), 3054 }; 3055 static const unsigned int scif2_data_mux[] = { 3056 RX2_MARK, TX2_MARK, 3057 }; 3058 static const unsigned int scif2_data_b_pins[] = { 3059 /* RX, TX */ 3060 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16), 3061 }; 3062 static const unsigned int scif2_data_b_mux[] = { 3063 RX2_B_MARK, TX2_B_MARK, 3064 }; 3065 static const unsigned int scif2_clk_b_pins[] = { 3066 /* SCK */ 3067 RCAR_GP_PIN(3, 18), 3068 }; 3069 static const unsigned int scif2_clk_b_mux[] = { 3070 SCIF2_SCK_B_MARK, 3071 }; 3072 static const unsigned int scif2_data_c_pins[] = { 3073 /* RX, TX */ 3074 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 3075 }; 3076 static const unsigned int scif2_data_c_mux[] = { 3077 RX2_C_MARK, TX2_C_MARK, 3078 }; 3079 static const unsigned int scif2_data_e_pins[] = { 3080 /* RX, TX */ 3081 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 3082 }; 3083 static const unsigned int scif2_data_e_mux[] = { 3084 RX2_E_MARK, TX2_E_MARK, 3085 }; 3086 /* - SCIF3 ------------------------------------------------------------------ */ 3087 static const unsigned int scif3_data_pins[] = { 3088 /* RX, TX */ 3089 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21), 3090 }; 3091 static const unsigned int scif3_data_mux[] = { 3092 RX3_MARK, TX3_MARK, 3093 }; 3094 static const unsigned int scif3_clk_pins[] = { 3095 /* SCK */ 3096 RCAR_GP_PIN(3, 23), 3097 }; 3098 static const unsigned int scif3_clk_mux[] = { 3099 SCIF3_SCK_MARK, 3100 }; 3101 static const unsigned int scif3_data_b_pins[] = { 3102 /* RX, TX */ 3103 RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 26), 3104 }; 3105 static const unsigned int scif3_data_b_mux[] = { 3106 RX3_B_MARK, TX3_B_MARK, 3107 }; 3108 static const unsigned int scif3_clk_b_pins[] = { 3109 /* SCK */ 3110 RCAR_GP_PIN(4, 8), 3111 }; 3112 static const unsigned int scif3_clk_b_mux[] = { 3113 SCIF3_SCK_B_MARK, 3114 }; 3115 static const unsigned int scif3_data_c_pins[] = { 3116 /* RX, TX */ 3117 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), 3118 }; 3119 static const unsigned int scif3_data_c_mux[] = { 3120 RX3_C_MARK, TX3_C_MARK, 3121 }; 3122 static const unsigned int scif3_data_d_pins[] = { 3123 /* RX, TX */ 3124 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 26), 3125 }; 3126 static const unsigned int scif3_data_d_mux[] = { 3127 RX3_D_MARK, TX3_D_MARK, 3128 }; 3129 /* - SCIF4 ------------------------------------------------------------------ */ 3130 static const unsigned int scif4_data_pins[] = { 3131 /* RX, TX */ 3132 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1), 3133 }; 3134 static const unsigned int scif4_data_mux[] = { 3135 RX4_MARK, TX4_MARK, 3136 }; 3137 static const unsigned int scif4_data_b_pins[] = { 3138 /* RX, TX */ 3139 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0), 3140 }; 3141 static const unsigned int scif4_data_b_mux[] = { 3142 RX4_B_MARK, TX4_B_MARK, 3143 }; 3144 static const unsigned int scif4_data_c_pins[] = { 3145 /* RX, TX */ 3146 RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21), 3147 }; 3148 static const unsigned int scif4_data_c_mux[] = { 3149 RX4_C_MARK, TX4_C_MARK, 3150 }; 3151 /* - SCIF5 ------------------------------------------------------------------ */ 3152 static const unsigned int scif5_data_pins[] = { 3153 /* RX, TX */ 3154 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3), 3155 }; 3156 static const unsigned int scif5_data_mux[] = { 3157 RX5_MARK, TX5_MARK, 3158 }; 3159 static const unsigned int scif5_data_b_pins[] = { 3160 /* RX, TX */ 3161 RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22), 3162 }; 3163 static const unsigned int scif5_data_b_mux[] = { 3164 RX5_B_MARK, TX5_B_MARK, 3165 }; 3166 /* - SCIFA0 ----------------------------------------------------------------- */ 3167 static const unsigned int scifa0_data_pins[] = { 3168 /* RXD, TXD */ 3169 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), 3170 }; 3171 static const unsigned int scifa0_data_mux[] = { 3172 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, 3173 }; 3174 static const unsigned int scifa0_data_b_pins[] = { 3175 /* RXD, TXD */ 3176 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0), 3177 }; 3178 static const unsigned int scifa0_data_b_mux[] = { 3179 SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK 3180 }; 3181 /* - SCIFA1 ----------------------------------------------------------------- */ 3182 static const unsigned int scifa1_data_pins[] = { 3183 /* RXD, TXD */ 3184 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), 3185 }; 3186 static const unsigned int scifa1_data_mux[] = { 3187 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, 3188 }; 3189 static const unsigned int scifa1_clk_pins[] = { 3190 /* SCK */ 3191 RCAR_GP_PIN(3, 10), 3192 }; 3193 static const unsigned int scifa1_clk_mux[] = { 3194 SCIFA1_SCK_MARK, 3195 }; 3196 static const unsigned int scifa1_data_b_pins[] = { 3197 /* RXD, TXD */ 3198 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8), 3199 }; 3200 static const unsigned int scifa1_data_b_mux[] = { 3201 SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK, 3202 }; 3203 static const unsigned int scifa1_clk_b_pins[] = { 3204 /* SCK */ 3205 RCAR_GP_PIN(1, 0), 3206 }; 3207 static const unsigned int scifa1_clk_b_mux[] = { 3208 SCIFA1_SCK_B_MARK, 3209 }; 3210 static const unsigned int scifa1_data_c_pins[] = { 3211 /* RXD, TXD */ 3212 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 3213 }; 3214 static const unsigned int scifa1_data_c_mux[] = { 3215 SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK, 3216 }; 3217 /* - SCIFA2 ----------------------------------------------------------------- */ 3218 static const unsigned int scifa2_data_pins[] = { 3219 /* RXD, TXD */ 3220 RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31), 3221 }; 3222 static const unsigned int scifa2_data_mux[] = { 3223 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK, 3224 }; 3225 static const unsigned int scifa2_clk_pins[] = { 3226 /* SCK */ 3227 RCAR_GP_PIN(3, 18), 3228 }; 3229 static const unsigned int scifa2_clk_mux[] = { 3230 SCIFA2_SCK_MARK, 3231 }; 3232 static const unsigned int scifa2_data_b_pins[] = { 3233 /* RXD, TXD */ 3234 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16), 3235 }; 3236 static const unsigned int scifa2_data_b_mux[] = { 3237 SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK, 3238 }; 3239 /* - SCIFA3 ----------------------------------------------------------------- */ 3240 static const unsigned int scifa3_data_pins[] = { 3241 /* RXD, TXD */ 3242 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21), 3243 }; 3244 static const unsigned int scifa3_data_mux[] = { 3245 SCIFA3_RXD_MARK, SCIFA3_TXD_MARK, 3246 }; 3247 static const unsigned int scifa3_clk_pins[] = { 3248 /* SCK */ 3249 RCAR_GP_PIN(3, 23), 3250 }; 3251 static const unsigned int scifa3_clk_mux[] = { 3252 SCIFA3_SCK_MARK, 3253 }; 3254 static const unsigned int scifa3_data_b_pins[] = { 3255 /* RXD, TXD */ 3256 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20), 3257 }; 3258 static const unsigned int scifa3_data_b_mux[] = { 3259 SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK, 3260 }; 3261 static const unsigned int scifa3_clk_b_pins[] = { 3262 /* SCK */ 3263 RCAR_GP_PIN(4, 8), 3264 }; 3265 static const unsigned int scifa3_clk_b_mux[] = { 3266 SCIFA3_SCK_B_MARK, 3267 }; 3268 static const unsigned int scifa3_data_c_pins[] = { 3269 /* RXD, TXD */ 3270 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 20), 3271 }; 3272 static const unsigned int scifa3_data_c_mux[] = { 3273 SCIFA3_RXD_C_MARK, SCIFA3_TXD_C_MARK, 3274 }; 3275 static const unsigned int scifa3_clk_c_pins[] = { 3276 /* SCK */ 3277 RCAR_GP_PIN(7, 22), 3278 }; 3279 static const unsigned int scifa3_clk_c_mux[] = { 3280 SCIFA3_SCK_C_MARK, 3281 }; 3282 /* - SCIFA4 ----------------------------------------------------------------- */ 3283 static const unsigned int scifa4_data_pins[] = { 3284 /* RXD, TXD */ 3285 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1), 3286 }; 3287 static const unsigned int scifa4_data_mux[] = { 3288 SCIFA4_RXD_MARK, SCIFA4_TXD_MARK, 3289 }; 3290 static const unsigned int scifa4_data_b_pins[] = { 3291 /* RXD, TXD */ 3292 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0), 3293 }; 3294 static const unsigned int scifa4_data_b_mux[] = { 3295 SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK, 3296 }; 3297 static const unsigned int scifa4_data_c_pins[] = { 3298 /* RXD, TXD */ 3299 RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21), 3300 }; 3301 static const unsigned int scifa4_data_c_mux[] = { 3302 SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK, 3303 }; 3304 /* - SCIFA5 ----------------------------------------------------------------- */ 3305 static const unsigned int scifa5_data_pins[] = { 3306 /* RXD, TXD */ 3307 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3), 3308 }; 3309 static const unsigned int scifa5_data_mux[] = { 3310 SCIFA5_RXD_MARK, SCIFA5_TXD_MARK, 3311 }; 3312 static const unsigned int scifa5_data_b_pins[] = { 3313 /* RXD, TXD */ 3314 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), 3315 }; 3316 static const unsigned int scifa5_data_b_mux[] = { 3317 SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK, 3318 }; 3319 static const unsigned int scifa5_data_c_pins[] = { 3320 /* RXD, TXD */ 3321 RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22), 3322 }; 3323 static const unsigned int scifa5_data_c_mux[] = { 3324 SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK, 3325 }; 3326 /* - SCIFB0 ----------------------------------------------------------------- */ 3327 static const unsigned int scifb0_data_pins[] = { 3328 /* RXD, TXD */ 3329 RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4), 3330 }; 3331 static const unsigned int scifb0_data_mux[] = { 3332 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK, 3333 }; 3334 static const unsigned int scifb0_clk_pins[] = { 3335 /* SCK */ 3336 RCAR_GP_PIN(7, 2), 3337 }; 3338 static const unsigned int scifb0_clk_mux[] = { 3339 SCIFB0_SCK_MARK, 3340 }; 3341 static const unsigned int scifb0_ctrl_pins[] = { 3342 /* RTS, CTS */ 3343 RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0), 3344 }; 3345 static const unsigned int scifb0_ctrl_mux[] = { 3346 SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK, 3347 }; 3348 static const unsigned int scifb0_data_b_pins[] = { 3349 /* RXD, TXD */ 3350 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21), 3351 }; 3352 static const unsigned int scifb0_data_b_mux[] = { 3353 SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK, 3354 }; 3355 static const unsigned int scifb0_clk_b_pins[] = { 3356 /* SCK */ 3357 RCAR_GP_PIN(5, 31), 3358 }; 3359 static const unsigned int scifb0_clk_b_mux[] = { 3360 SCIFB0_SCK_B_MARK, 3361 }; 3362 static const unsigned int scifb0_ctrl_b_pins[] = { 3363 /* RTS, CTS */ 3364 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23), 3365 }; 3366 static const unsigned int scifb0_ctrl_b_mux[] = { 3367 SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK, 3368 }; 3369 static const unsigned int scifb0_data_c_pins[] = { 3370 /* RXD, TXD */ 3371 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 3372 }; 3373 static const unsigned int scifb0_data_c_mux[] = { 3374 SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK, 3375 }; 3376 static const unsigned int scifb0_clk_c_pins[] = { 3377 /* SCK */ 3378 RCAR_GP_PIN(2, 30), 3379 }; 3380 static const unsigned int scifb0_clk_c_mux[] = { 3381 SCIFB0_SCK_C_MARK, 3382 }; 3383 static const unsigned int scifb0_data_d_pins[] = { 3384 /* RXD, TXD */ 3385 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18), 3386 }; 3387 static const unsigned int scifb0_data_d_mux[] = { 3388 SCIFB0_RXD_D_MARK, SCIFB0_TXD_D_MARK, 3389 }; 3390 static const unsigned int scifb0_clk_d_pins[] = { 3391 /* SCK */ 3392 RCAR_GP_PIN(4, 17), 3393 }; 3394 static const unsigned int scifb0_clk_d_mux[] = { 3395 SCIFB0_SCK_D_MARK, 3396 }; 3397 /* - SCIFB1 ----------------------------------------------------------------- */ 3398 static const unsigned int scifb1_data_pins[] = { 3399 /* RXD, TXD */ 3400 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6), 3401 }; 3402 static const unsigned int scifb1_data_mux[] = { 3403 SCIFB1_RXD_MARK, SCIFB1_TXD_MARK, 3404 }; 3405 static const unsigned int scifb1_clk_pins[] = { 3406 /* SCK */ 3407 RCAR_GP_PIN(7, 7), 3408 }; 3409 static const unsigned int scifb1_clk_mux[] = { 3410 SCIFB1_SCK_MARK, 3411 }; 3412 static const unsigned int scifb1_ctrl_pins[] = { 3413 /* RTS, CTS */ 3414 RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8), 3415 }; 3416 static const unsigned int scifb1_ctrl_mux[] = { 3417 SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK, 3418 }; 3419 static const unsigned int scifb1_data_b_pins[] = { 3420 /* RXD, TXD */ 3421 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), 3422 }; 3423 static const unsigned int scifb1_data_b_mux[] = { 3424 SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK, 3425 }; 3426 static const unsigned int scifb1_clk_b_pins[] = { 3427 /* SCK */ 3428 RCAR_GP_PIN(1, 3), 3429 }; 3430 static const unsigned int scifb1_clk_b_mux[] = { 3431 SCIFB1_SCK_B_MARK, 3432 }; 3433 static const unsigned int scifb1_data_c_pins[] = { 3434 /* RXD, TXD */ 3435 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 3436 }; 3437 static const unsigned int scifb1_data_c_mux[] = { 3438 SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK, 3439 }; 3440 static const unsigned int scifb1_clk_c_pins[] = { 3441 /* SCK */ 3442 RCAR_GP_PIN(7, 11), 3443 }; 3444 static const unsigned int scifb1_clk_c_mux[] = { 3445 SCIFB1_SCK_C_MARK, 3446 }; 3447 static const unsigned int scifb1_data_d_pins[] = { 3448 /* RXD, TXD */ 3449 RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 12), 3450 }; 3451 static const unsigned int scifb1_data_d_mux[] = { 3452 SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK, 3453 }; 3454 /* - SCIFB2 ----------------------------------------------------------------- */ 3455 static const unsigned int scifb2_data_pins[] = { 3456 /* RXD, TXD */ 3457 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17), 3458 }; 3459 static const unsigned int scifb2_data_mux[] = { 3460 SCIFB2_RXD_MARK, SCIFB2_TXD_MARK, 3461 }; 3462 static const unsigned int scifb2_clk_pins[] = { 3463 /* SCK */ 3464 RCAR_GP_PIN(4, 15), 3465 }; 3466 static const unsigned int scifb2_clk_mux[] = { 3467 SCIFB2_SCK_MARK, 3468 }; 3469 static const unsigned int scifb2_ctrl_pins[] = { 3470 /* RTS, CTS */ 3471 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), 3472 }; 3473 static const unsigned int scifb2_ctrl_mux[] = { 3474 SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK, 3475 }; 3476 static const unsigned int scifb2_data_b_pins[] = { 3477 /* RXD, TXD */ 3478 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), 3479 }; 3480 static const unsigned int scifb2_data_b_mux[] = { 3481 SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK, 3482 }; 3483 static const unsigned int scifb2_clk_b_pins[] = { 3484 /* SCK */ 3485 RCAR_GP_PIN(5, 31), 3486 }; 3487 static const unsigned int scifb2_clk_b_mux[] = { 3488 SCIFB2_SCK_B_MARK, 3489 }; 3490 static const unsigned int scifb2_ctrl_b_pins[] = { 3491 /* RTS, CTS */ 3492 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), 3493 }; 3494 static const unsigned int scifb2_ctrl_b_mux[] = { 3495 SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK, 3496 }; 3497 static const unsigned int scifb2_data_c_pins[] = { 3498 /* RXD, TXD */ 3499 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 3500 }; 3501 static const unsigned int scifb2_data_c_mux[] = { 3502 SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK, 3503 }; 3504 static const unsigned int scifb2_clk_c_pins[] = { 3505 /* SCK */ 3506 RCAR_GP_PIN(5, 27), 3507 }; 3508 static const unsigned int scifb2_clk_c_mux[] = { 3509 SCIFB2_SCK_C_MARK, 3510 }; 3511 static const unsigned int scifb2_data_d_pins[] = { 3512 /* RXD, TXD */ 3513 RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 25), 3514 }; 3515 static const unsigned int scifb2_data_d_mux[] = { 3516 SCIFB2_RXD_D_MARK, SCIFB2_TXD_D_MARK, 3517 }; 3518 /* - SDHI0 ------------------------------------------------------------------ */ 3519 static const unsigned int sdhi0_data1_pins[] = { 3520 /* D0 */ 3521 RCAR_GP_PIN(6, 2), 3522 }; 3523 static const unsigned int sdhi0_data1_mux[] = { 3524 SD0_DATA0_MARK, 3525 }; 3526 static const unsigned int sdhi0_data4_pins[] = { 3527 /* D[0:3] */ 3528 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), 3529 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5), 3530 }; 3531 static const unsigned int sdhi0_data4_mux[] = { 3532 SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK, 3533 }; 3534 static const unsigned int sdhi0_ctrl_pins[] = { 3535 /* CLK, CMD */ 3536 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), 3537 }; 3538 static const unsigned int sdhi0_ctrl_mux[] = { 3539 SD0_CLK_MARK, SD0_CMD_MARK, 3540 }; 3541 static const unsigned int sdhi0_cd_pins[] = { 3542 /* CD */ 3543 RCAR_GP_PIN(6, 6), 3544 }; 3545 static const unsigned int sdhi0_cd_mux[] = { 3546 SD0_CD_MARK, 3547 }; 3548 static const unsigned int sdhi0_wp_pins[] = { 3549 /* WP */ 3550 RCAR_GP_PIN(6, 7), 3551 }; 3552 static const unsigned int sdhi0_wp_mux[] = { 3553 SD0_WP_MARK, 3554 }; 3555 /* - SDHI1 ------------------------------------------------------------------ */ 3556 static const unsigned int sdhi1_data1_pins[] = { 3557 /* D0 */ 3558 RCAR_GP_PIN(6, 10), 3559 }; 3560 static const unsigned int sdhi1_data1_mux[] = { 3561 SD1_DATA0_MARK, 3562 }; 3563 static const unsigned int sdhi1_data4_pins[] = { 3564 /* D[0:3] */ 3565 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11), 3566 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13), 3567 }; 3568 static const unsigned int sdhi1_data4_mux[] = { 3569 SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK, 3570 }; 3571 static const unsigned int sdhi1_ctrl_pins[] = { 3572 /* CLK, CMD */ 3573 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 3574 }; 3575 static const unsigned int sdhi1_ctrl_mux[] = { 3576 SD1_CLK_MARK, SD1_CMD_MARK, 3577 }; 3578 static const unsigned int sdhi1_cd_pins[] = { 3579 /* CD */ 3580 RCAR_GP_PIN(6, 14), 3581 }; 3582 static const unsigned int sdhi1_cd_mux[] = { 3583 SD1_CD_MARK, 3584 }; 3585 static const unsigned int sdhi1_wp_pins[] = { 3586 /* WP */ 3587 RCAR_GP_PIN(6, 15), 3588 }; 3589 static const unsigned int sdhi1_wp_mux[] = { 3590 SD1_WP_MARK, 3591 }; 3592 /* - SDHI2 ------------------------------------------------------------------ */ 3593 static const unsigned int sdhi2_data1_pins[] = { 3594 /* D0 */ 3595 RCAR_GP_PIN(6, 18), 3596 }; 3597 static const unsigned int sdhi2_data1_mux[] = { 3598 SD2_DATA0_MARK, 3599 }; 3600 static const unsigned int sdhi2_data4_pins[] = { 3601 /* D[0:3] */ 3602 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), 3603 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), 3604 }; 3605 static const unsigned int sdhi2_data4_mux[] = { 3606 SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK, 3607 }; 3608 static const unsigned int sdhi2_ctrl_pins[] = { 3609 /* CLK, CMD */ 3610 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17), 3611 }; 3612 static const unsigned int sdhi2_ctrl_mux[] = { 3613 SD2_CLK_MARK, SD2_CMD_MARK, 3614 }; 3615 static const unsigned int sdhi2_cd_pins[] = { 3616 /* CD */ 3617 RCAR_GP_PIN(6, 22), 3618 }; 3619 static const unsigned int sdhi2_cd_mux[] = { 3620 SD2_CD_MARK, 3621 }; 3622 static const unsigned int sdhi2_wp_pins[] = { 3623 /* WP */ 3624 RCAR_GP_PIN(6, 23), 3625 }; 3626 static const unsigned int sdhi2_wp_mux[] = { 3627 SD2_WP_MARK, 3628 }; 3629 3630 /* - SSI -------------------------------------------------------------------- */ 3631 static const unsigned int ssi0_data_pins[] = { 3632 /* SDATA */ 3633 RCAR_GP_PIN(2, 2), 3634 }; 3635 3636 static const unsigned int ssi0_data_mux[] = { 3637 SSI_SDATA0_MARK, 3638 }; 3639 3640 static const unsigned int ssi0_data_b_pins[] = { 3641 /* SDATA */ 3642 RCAR_GP_PIN(3, 4), 3643 }; 3644 3645 static const unsigned int ssi0_data_b_mux[] = { 3646 SSI_SDATA0_B_MARK, 3647 }; 3648 3649 static const unsigned int ssi0129_ctrl_pins[] = { 3650 /* SCK, WS */ 3651 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 3652 }; 3653 3654 static const unsigned int ssi0129_ctrl_mux[] = { 3655 SSI_SCK0129_MARK, SSI_WS0129_MARK, 3656 }; 3657 3658 static const unsigned int ssi0129_ctrl_b_pins[] = { 3659 /* SCK, WS */ 3660 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 3661 }; 3662 3663 static const unsigned int ssi0129_ctrl_b_mux[] = { 3664 SSI_SCK0129_B_MARK, SSI_WS0129_B_MARK, 3665 }; 3666 3667 static const unsigned int ssi1_data_pins[] = { 3668 /* SDATA */ 3669 RCAR_GP_PIN(2, 5), 3670 }; 3671 3672 static const unsigned int ssi1_data_mux[] = { 3673 SSI_SDATA1_MARK, 3674 }; 3675 3676 static const unsigned int ssi1_data_b_pins[] = { 3677 /* SDATA */ 3678 RCAR_GP_PIN(3, 7), 3679 }; 3680 3681 static const unsigned int ssi1_data_b_mux[] = { 3682 SSI_SDATA1_B_MARK, 3683 }; 3684 3685 static const unsigned int ssi1_ctrl_pins[] = { 3686 /* SCK, WS */ 3687 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), 3688 }; 3689 3690 static const unsigned int ssi1_ctrl_mux[] = { 3691 SSI_SCK1_MARK, SSI_WS1_MARK, 3692 }; 3693 3694 static const unsigned int ssi1_ctrl_b_pins[] = { 3695 /* SCK, WS */ 3696 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), 3697 }; 3698 3699 static const unsigned int ssi1_ctrl_b_mux[] = { 3700 SSI_SCK1_B_MARK, SSI_WS1_B_MARK, 3701 }; 3702 3703 static const unsigned int ssi2_data_pins[] = { 3704 /* SDATA */ 3705 RCAR_GP_PIN(2, 8), 3706 }; 3707 3708 static const unsigned int ssi2_data_mux[] = { 3709 SSI_SDATA2_MARK, 3710 }; 3711 3712 static const unsigned int ssi2_ctrl_pins[] = { 3713 /* SCK, WS */ 3714 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 3715 }; 3716 3717 static const unsigned int ssi2_ctrl_mux[] = { 3718 SSI_SCK2_MARK, SSI_WS2_MARK, 3719 }; 3720 3721 static const unsigned int ssi3_data_pins[] = { 3722 /* SDATA */ 3723 RCAR_GP_PIN(2, 11), 3724 }; 3725 3726 static const unsigned int ssi3_data_mux[] = { 3727 SSI_SDATA3_MARK, 3728 }; 3729 3730 static const unsigned int ssi34_ctrl_pins[] = { 3731 /* SCK, WS */ 3732 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), 3733 }; 3734 3735 static const unsigned int ssi34_ctrl_mux[] = { 3736 SSI_SCK34_MARK, SSI_WS34_MARK, 3737 }; 3738 3739 static const unsigned int ssi4_data_pins[] = { 3740 /* SDATA */ 3741 RCAR_GP_PIN(2, 14), 3742 }; 3743 3744 static const unsigned int ssi4_data_mux[] = { 3745 SSI_SDATA4_MARK, 3746 }; 3747 3748 static const unsigned int ssi4_ctrl_pins[] = { 3749 /* SCK, WS */ 3750 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), 3751 }; 3752 3753 static const unsigned int ssi4_ctrl_mux[] = { 3754 SSI_SCK4_MARK, SSI_WS4_MARK, 3755 }; 3756 3757 static const unsigned int ssi5_data_pins[] = { 3758 /* SDATA */ 3759 RCAR_GP_PIN(2, 17), 3760 }; 3761 3762 static const unsigned int ssi5_data_mux[] = { 3763 SSI_SDATA5_MARK, 3764 }; 3765 3766 static const unsigned int ssi5_ctrl_pins[] = { 3767 /* SCK, WS */ 3768 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), 3769 }; 3770 3771 static const unsigned int ssi5_ctrl_mux[] = { 3772 SSI_SCK5_MARK, SSI_WS5_MARK, 3773 }; 3774 3775 static const unsigned int ssi6_data_pins[] = { 3776 /* SDATA */ 3777 RCAR_GP_PIN(2, 20), 3778 }; 3779 3780 static const unsigned int ssi6_data_mux[] = { 3781 SSI_SDATA6_MARK, 3782 }; 3783 3784 static const unsigned int ssi6_ctrl_pins[] = { 3785 /* SCK, WS */ 3786 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19), 3787 }; 3788 3789 static const unsigned int ssi6_ctrl_mux[] = { 3790 SSI_SCK6_MARK, SSI_WS6_MARK, 3791 }; 3792 3793 static const unsigned int ssi7_data_pins[] = { 3794 /* SDATA */ 3795 RCAR_GP_PIN(2, 23), 3796 }; 3797 3798 static const unsigned int ssi7_data_mux[] = { 3799 SSI_SDATA7_MARK, 3800 }; 3801 3802 static const unsigned int ssi7_data_b_pins[] = { 3803 /* SDATA */ 3804 RCAR_GP_PIN(3, 12), 3805 }; 3806 3807 static const unsigned int ssi7_data_b_mux[] = { 3808 SSI_SDATA7_B_MARK, 3809 }; 3810 3811 static const unsigned int ssi78_ctrl_pins[] = { 3812 /* SCK, WS */ 3813 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), 3814 }; 3815 3816 static const unsigned int ssi78_ctrl_mux[] = { 3817 SSI_SCK78_MARK, SSI_WS78_MARK, 3818 }; 3819 3820 static const unsigned int ssi78_ctrl_b_pins[] = { 3821 /* SCK, WS */ 3822 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3823 }; 3824 3825 static const unsigned int ssi78_ctrl_b_mux[] = { 3826 SSI_SCK78_B_MARK, SSI_WS78_B_MARK, 3827 }; 3828 3829 static const unsigned int ssi8_data_pins[] = { 3830 /* SDATA */ 3831 RCAR_GP_PIN(2, 24), 3832 }; 3833 3834 static const unsigned int ssi8_data_mux[] = { 3835 SSI_SDATA8_MARK, 3836 }; 3837 3838 static const unsigned int ssi8_data_b_pins[] = { 3839 /* SDATA */ 3840 RCAR_GP_PIN(3, 13), 3841 }; 3842 3843 static const unsigned int ssi8_data_b_mux[] = { 3844 SSI_SDATA8_B_MARK, 3845 }; 3846 3847 static const unsigned int ssi9_data_pins[] = { 3848 /* SDATA */ 3849 RCAR_GP_PIN(2, 27), 3850 }; 3851 3852 static const unsigned int ssi9_data_mux[] = { 3853 SSI_SDATA9_MARK, 3854 }; 3855 3856 static const unsigned int ssi9_data_b_pins[] = { 3857 /* SDATA */ 3858 RCAR_GP_PIN(3, 18), 3859 }; 3860 3861 static const unsigned int ssi9_data_b_mux[] = { 3862 SSI_SDATA9_B_MARK, 3863 }; 3864 3865 static const unsigned int ssi9_ctrl_pins[] = { 3866 /* SCK, WS */ 3867 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26), 3868 }; 3869 3870 static const unsigned int ssi9_ctrl_mux[] = { 3871 SSI_SCK9_MARK, SSI_WS9_MARK, 3872 }; 3873 3874 static const unsigned int ssi9_ctrl_b_pins[] = { 3875 /* SCK, WS */ 3876 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 3877 }; 3878 3879 static const unsigned int ssi9_ctrl_b_mux[] = { 3880 SSI_SCK9_B_MARK, SSI_WS9_B_MARK, 3881 }; 3882 3883 /* - USB0 ------------------------------------------------------------------- */ 3884 static const unsigned int usb0_pins[] = { 3885 RCAR_GP_PIN(7, 23), /* PWEN */ 3886 RCAR_GP_PIN(7, 24), /* OVC */ 3887 }; 3888 static const unsigned int usb0_mux[] = { 3889 USB0_PWEN_MARK, 3890 USB0_OVC_MARK, 3891 }; 3892 /* - USB1 ------------------------------------------------------------------- */ 3893 static const unsigned int usb1_pins[] = { 3894 RCAR_GP_PIN(7, 25), /* PWEN */ 3895 RCAR_GP_PIN(6, 30), /* OVC */ 3896 }; 3897 static const unsigned int usb1_mux[] = { 3898 USB1_PWEN_MARK, 3899 USB1_OVC_MARK, 3900 }; 3901 3902 union vin_data { 3903 unsigned int data24[24]; 3904 unsigned int data20[20]; 3905 unsigned int data16[16]; 3906 unsigned int data12[12]; 3907 unsigned int data10[10]; 3908 unsigned int data8[8]; 3909 }; 3910 3911 #define VIN_DATA_PIN_GROUP(n, s) \ 3912 { \ 3913 .name = #n#s, \ 3914 .pins = n##_pins.data##s, \ 3915 .mux = n##_mux.data##s, \ 3916 .nr_pins = ARRAY_SIZE(n##_pins.data##s), \ 3917 } 3918 3919 /* - VIN0 ------------------------------------------------------------------- */ 3920 static const union vin_data vin0_data_pins = { 3921 .data24 = { 3922 /* B */ 3923 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6), 3924 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), 3925 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 3926 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3927 /* G */ 3928 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), 3929 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), 3930 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18), 3931 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20), 3932 /* R */ 3933 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22), 3934 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24), 3935 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), 3936 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28), 3937 }, 3938 }; 3939 static const union vin_data vin0_data_mux = { 3940 .data24 = { 3941 /* B */ 3942 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, 3943 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, 3944 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, 3945 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, 3946 /* G */ 3947 VI0_G0_MARK, VI0_G1_MARK, 3948 VI0_G2_MARK, VI0_G3_MARK, 3949 VI0_G4_MARK, VI0_G5_MARK, 3950 VI0_G6_MARK, VI0_G7_MARK, 3951 /* R */ 3952 VI0_R0_MARK, VI0_R1_MARK, 3953 VI0_R2_MARK, VI0_R3_MARK, 3954 VI0_R4_MARK, VI0_R5_MARK, 3955 VI0_R6_MARK, VI0_R7_MARK, 3956 }, 3957 }; 3958 static const unsigned int vin0_data18_pins[] = { 3959 /* B */ 3960 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), 3961 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 3962 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3963 /* G */ 3964 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), 3965 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18), 3966 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20), 3967 /* R */ 3968 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24), 3969 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), 3970 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28), 3971 }; 3972 static const unsigned int vin0_data18_mux[] = { 3973 /* B */ 3974 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, 3975 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, 3976 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, 3977 /* G */ 3978 VI0_G2_MARK, VI0_G3_MARK, 3979 VI0_G4_MARK, VI0_G5_MARK, 3980 VI0_G6_MARK, VI0_G7_MARK, 3981 /* R */ 3982 VI0_R2_MARK, VI0_R3_MARK, 3983 VI0_R4_MARK, VI0_R5_MARK, 3984 VI0_R6_MARK, VI0_R7_MARK, 3985 }; 3986 static const unsigned int vin0_sync_pins[] = { 3987 RCAR_GP_PIN(4, 3), /* HSYNC */ 3988 RCAR_GP_PIN(4, 4), /* VSYNC */ 3989 }; 3990 static const unsigned int vin0_sync_mux[] = { 3991 VI0_HSYNC_N_MARK, 3992 VI0_VSYNC_N_MARK, 3993 }; 3994 static const unsigned int vin0_field_pins[] = { 3995 RCAR_GP_PIN(4, 2), 3996 }; 3997 static const unsigned int vin0_field_mux[] = { 3998 VI0_FIELD_MARK, 3999 }; 4000 static const unsigned int vin0_clkenb_pins[] = { 4001 RCAR_GP_PIN(4, 1), 4002 }; 4003 static const unsigned int vin0_clkenb_mux[] = { 4004 VI0_CLKENB_MARK, 4005 }; 4006 static const unsigned int vin0_clk_pins[] = { 4007 RCAR_GP_PIN(4, 0), 4008 }; 4009 static const unsigned int vin0_clk_mux[] = { 4010 VI0_CLK_MARK, 4011 }; 4012 /* - VIN1 ----------------------------------------------------------------- */ 4013 static const unsigned int vin1_data8_pins[] = { 4014 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 4015 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), 4016 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), 4017 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12), 4018 }; 4019 static const unsigned int vin1_data8_mux[] = { 4020 VI1_DATA0_MARK, VI1_DATA1_MARK, 4021 VI1_DATA2_MARK, VI1_DATA3_MARK, 4022 VI1_DATA4_MARK, VI1_DATA5_MARK, 4023 VI1_DATA6_MARK, VI1_DATA7_MARK, 4024 }; 4025 static const unsigned int vin1_sync_pins[] = { 4026 RCAR_GP_PIN(5, 0), /* HSYNC */ 4027 RCAR_GP_PIN(5, 1), /* VSYNC */ 4028 }; 4029 static const unsigned int vin1_sync_mux[] = { 4030 VI1_HSYNC_N_MARK, 4031 VI1_VSYNC_N_MARK, 4032 }; 4033 static const unsigned int vin1_field_pins[] = { 4034 RCAR_GP_PIN(5, 3), 4035 }; 4036 static const unsigned int vin1_field_mux[] = { 4037 VI1_FIELD_MARK, 4038 }; 4039 static const unsigned int vin1_clkenb_pins[] = { 4040 RCAR_GP_PIN(5, 2), 4041 }; 4042 static const unsigned int vin1_clkenb_mux[] = { 4043 VI1_CLKENB_MARK, 4044 }; 4045 static const unsigned int vin1_clk_pins[] = { 4046 RCAR_GP_PIN(5, 4), 4047 }; 4048 static const unsigned int vin1_clk_mux[] = { 4049 VI1_CLK_MARK, 4050 }; 4051 static const union vin_data vin1_b_data_pins = { 4052 .data24 = { 4053 /* B */ 4054 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), 4055 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 4056 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 4057 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), 4058 /* G */ 4059 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 4060 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 4061 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 4062 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22), 4063 /* R */ 4064 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6), 4065 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), 4066 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), 4067 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), 4068 }, 4069 }; 4070 static const union vin_data vin1_b_data_mux = { 4071 .data24 = { 4072 /* B */ 4073 VI1_DATA0_B_MARK, VI1_DATA1_B_MARK, 4074 VI1_DATA2_B_MARK, VI1_DATA3_B_MARK, 4075 VI1_DATA4_B_MARK, VI1_DATA5_B_MARK, 4076 VI1_DATA6_B_MARK, VI1_DATA7_B_MARK, 4077 /* G */ 4078 VI1_G0_B_MARK, VI1_G1_B_MARK, 4079 VI1_G2_B_MARK, VI1_G3_B_MARK, 4080 VI1_G4_B_MARK, VI1_G5_B_MARK, 4081 VI1_G6_B_MARK, VI1_G7_B_MARK, 4082 /* R */ 4083 VI1_R0_B_MARK, VI1_R1_B_MARK, 4084 VI1_R2_B_MARK, VI1_R3_B_MARK, 4085 VI1_R4_B_MARK, VI1_R5_B_MARK, 4086 VI1_R6_B_MARK, VI1_R7_B_MARK, 4087 }, 4088 }; 4089 static const unsigned int vin1_b_data18_pins[] = { 4090 /* B */ 4091 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 4092 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 4093 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), 4094 /* G */ 4095 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 4096 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 4097 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22), 4098 /* R */ 4099 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), 4100 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), 4101 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), 4102 }; 4103 static const unsigned int vin1_b_data18_mux[] = { 4104 /* B */ 4105 VI1_DATA0_B_MARK, VI1_DATA1_B_MARK, 4106 VI1_DATA2_B_MARK, VI1_DATA3_B_MARK, 4107 VI1_DATA4_B_MARK, VI1_DATA5_B_MARK, 4108 VI1_DATA6_B_MARK, VI1_DATA7_B_MARK, 4109 /* G */ 4110 VI1_G0_B_MARK, VI1_G1_B_MARK, 4111 VI1_G2_B_MARK, VI1_G3_B_MARK, 4112 VI1_G4_B_MARK, VI1_G5_B_MARK, 4113 VI1_G6_B_MARK, VI1_G7_B_MARK, 4114 /* R */ 4115 VI1_R0_B_MARK, VI1_R1_B_MARK, 4116 VI1_R2_B_MARK, VI1_R3_B_MARK, 4117 VI1_R4_B_MARK, VI1_R5_B_MARK, 4118 VI1_R6_B_MARK, VI1_R7_B_MARK, 4119 }; 4120 static const unsigned int vin1_b_sync_pins[] = { 4121 RCAR_GP_PIN(3, 17), /* HSYNC */ 4122 RCAR_GP_PIN(3, 18), /* VSYNC */ 4123 }; 4124 static const unsigned int vin1_b_sync_mux[] = { 4125 VI1_HSYNC_N_B_MARK, 4126 VI1_VSYNC_N_B_MARK, 4127 }; 4128 static const unsigned int vin1_b_field_pins[] = { 4129 RCAR_GP_PIN(3, 20), 4130 }; 4131 static const unsigned int vin1_b_field_mux[] = { 4132 VI1_FIELD_B_MARK, 4133 }; 4134 static const unsigned int vin1_b_clkenb_pins[] = { 4135 RCAR_GP_PIN(3, 19), 4136 }; 4137 static const unsigned int vin1_b_clkenb_mux[] = { 4138 VI1_CLKENB_B_MARK, 4139 }; 4140 static const unsigned int vin1_b_clk_pins[] = { 4141 RCAR_GP_PIN(3, 16), 4142 }; 4143 static const unsigned int vin1_b_clk_mux[] = { 4144 VI1_CLK_B_MARK, 4145 }; 4146 /* - VIN2 ----------------------------------------------------------------- */ 4147 static const unsigned int vin2_data8_pins[] = { 4148 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), 4149 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), 4150 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25), 4151 RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27), 4152 }; 4153 static const unsigned int vin2_data8_mux[] = { 4154 VI2_DATA0_MARK, VI2_DATA1_MARK, 4155 VI2_DATA2_MARK, VI2_DATA3_MARK, 4156 VI2_DATA4_MARK, VI2_DATA5_MARK, 4157 VI2_DATA6_MARK, VI2_DATA7_MARK, 4158 }; 4159 static const unsigned int vin2_sync_pins[] = { 4160 RCAR_GP_PIN(4, 15), /* HSYNC */ 4161 RCAR_GP_PIN(4, 16), /* VSYNC */ 4162 }; 4163 static const unsigned int vin2_sync_mux[] = { 4164 VI2_HSYNC_N_MARK, 4165 VI2_VSYNC_N_MARK, 4166 }; 4167 static const unsigned int vin2_field_pins[] = { 4168 RCAR_GP_PIN(4, 18), 4169 }; 4170 static const unsigned int vin2_field_mux[] = { 4171 VI2_FIELD_MARK, 4172 }; 4173 static const unsigned int vin2_clkenb_pins[] = { 4174 RCAR_GP_PIN(4, 17), 4175 }; 4176 static const unsigned int vin2_clkenb_mux[] = { 4177 VI2_CLKENB_MARK, 4178 }; 4179 static const unsigned int vin2_clk_pins[] = { 4180 RCAR_GP_PIN(4, 19), 4181 }; 4182 static const unsigned int vin2_clk_mux[] = { 4183 VI2_CLK_MARK, 4184 }; 4185 4186 static const struct sh_pfc_pin_group pinmux_groups[] = { 4187 SH_PFC_PIN_GROUP(audio_clk_a), 4188 SH_PFC_PIN_GROUP(audio_clk_b), 4189 SH_PFC_PIN_GROUP(audio_clk_b_b), 4190 SH_PFC_PIN_GROUP(audio_clk_c), 4191 SH_PFC_PIN_GROUP(audio_clkout), 4192 SH_PFC_PIN_GROUP(can0_data), 4193 SH_PFC_PIN_GROUP(can0_data_b), 4194 SH_PFC_PIN_GROUP(can0_data_c), 4195 SH_PFC_PIN_GROUP(can0_data_d), 4196 SH_PFC_PIN_GROUP(can0_data_e), 4197 SH_PFC_PIN_GROUP(can0_data_f), 4198 SH_PFC_PIN_GROUP(can1_data), 4199 SH_PFC_PIN_GROUP(can1_data_b), 4200 SH_PFC_PIN_GROUP(can1_data_c), 4201 SH_PFC_PIN_GROUP(can1_data_d), 4202 SH_PFC_PIN_GROUP(can_clk), 4203 SH_PFC_PIN_GROUP(can_clk_b), 4204 SH_PFC_PIN_GROUP(can_clk_c), 4205 SH_PFC_PIN_GROUP(can_clk_d), 4206 SH_PFC_PIN_GROUP(du_rgb666), 4207 SH_PFC_PIN_GROUP(du_rgb888), 4208 SH_PFC_PIN_GROUP(du_clk_out_0), 4209 SH_PFC_PIN_GROUP(du_clk_out_1), 4210 SH_PFC_PIN_GROUP(du_sync), 4211 SH_PFC_PIN_GROUP(du_oddf), 4212 SH_PFC_PIN_GROUP(du_cde), 4213 SH_PFC_PIN_GROUP(du_disp), 4214 SH_PFC_PIN_GROUP(du0_clk_in), 4215 SH_PFC_PIN_GROUP(du1_clk_in), 4216 SH_PFC_PIN_GROUP(du1_clk_in_b), 4217 SH_PFC_PIN_GROUP(du1_clk_in_c), 4218 SH_PFC_PIN_GROUP(eth_link), 4219 SH_PFC_PIN_GROUP(eth_magic), 4220 SH_PFC_PIN_GROUP(eth_mdio), 4221 SH_PFC_PIN_GROUP(eth_rmii), 4222 SH_PFC_PIN_GROUP(hscif0_data), 4223 SH_PFC_PIN_GROUP(hscif0_clk), 4224 SH_PFC_PIN_GROUP(hscif0_ctrl), 4225 SH_PFC_PIN_GROUP(hscif0_data_b), 4226 SH_PFC_PIN_GROUP(hscif0_ctrl_b), 4227 SH_PFC_PIN_GROUP(hscif0_data_c), 4228 SH_PFC_PIN_GROUP(hscif0_clk_c), 4229 SH_PFC_PIN_GROUP(hscif1_data), 4230 SH_PFC_PIN_GROUP(hscif1_clk), 4231 SH_PFC_PIN_GROUP(hscif1_ctrl), 4232 SH_PFC_PIN_GROUP(hscif1_data_b), 4233 SH_PFC_PIN_GROUP(hscif1_data_c), 4234 SH_PFC_PIN_GROUP(hscif1_clk_c), 4235 SH_PFC_PIN_GROUP(hscif1_ctrl_c), 4236 SH_PFC_PIN_GROUP(hscif1_data_d), 4237 SH_PFC_PIN_GROUP(hscif1_data_e), 4238 SH_PFC_PIN_GROUP(hscif1_clk_e), 4239 SH_PFC_PIN_GROUP(hscif1_ctrl_e), 4240 SH_PFC_PIN_GROUP(hscif2_data), 4241 SH_PFC_PIN_GROUP(hscif2_clk), 4242 SH_PFC_PIN_GROUP(hscif2_ctrl), 4243 SH_PFC_PIN_GROUP(hscif2_data_b), 4244 SH_PFC_PIN_GROUP(hscif2_ctrl_b), 4245 SH_PFC_PIN_GROUP(hscif2_data_c), 4246 SH_PFC_PIN_GROUP(hscif2_clk_c), 4247 SH_PFC_PIN_GROUP(hscif2_data_d), 4248 SH_PFC_PIN_GROUP(i2c0), 4249 SH_PFC_PIN_GROUP(i2c0_b), 4250 SH_PFC_PIN_GROUP(i2c0_c), 4251 SH_PFC_PIN_GROUP(i2c1), 4252 SH_PFC_PIN_GROUP(i2c1_b), 4253 SH_PFC_PIN_GROUP(i2c1_c), 4254 SH_PFC_PIN_GROUP(i2c1_d), 4255 SH_PFC_PIN_GROUP(i2c1_e), 4256 SH_PFC_PIN_GROUP(i2c2), 4257 SH_PFC_PIN_GROUP(i2c2_b), 4258 SH_PFC_PIN_GROUP(i2c2_c), 4259 SH_PFC_PIN_GROUP(i2c2_d), 4260 SH_PFC_PIN_GROUP(i2c3), 4261 SH_PFC_PIN_GROUP(i2c3_b), 4262 SH_PFC_PIN_GROUP(i2c3_c), 4263 SH_PFC_PIN_GROUP(i2c3_d), 4264 SH_PFC_PIN_GROUP(i2c4), 4265 SH_PFC_PIN_GROUP(i2c4_b), 4266 SH_PFC_PIN_GROUP(i2c4_c), 4267 SH_PFC_PIN_GROUP(i2c7), 4268 SH_PFC_PIN_GROUP(i2c7_b), 4269 SH_PFC_PIN_GROUP(i2c7_c), 4270 SH_PFC_PIN_GROUP(i2c8), 4271 SH_PFC_PIN_GROUP(i2c8_b), 4272 SH_PFC_PIN_GROUP(i2c8_c), 4273 SH_PFC_PIN_GROUP(intc_irq0), 4274 SH_PFC_PIN_GROUP(intc_irq1), 4275 SH_PFC_PIN_GROUP(intc_irq2), 4276 SH_PFC_PIN_GROUP(intc_irq3), 4277 SH_PFC_PIN_GROUP(mlb_3pin), 4278 SH_PFC_PIN_GROUP(mmc_data1), 4279 SH_PFC_PIN_GROUP(mmc_data4), 4280 SH_PFC_PIN_GROUP(mmc_data8), 4281 SH_PFC_PIN_GROUP(mmc_ctrl), 4282 SH_PFC_PIN_GROUP(msiof0_clk), 4283 SH_PFC_PIN_GROUP(msiof0_sync), 4284 SH_PFC_PIN_GROUP(msiof0_ss1), 4285 SH_PFC_PIN_GROUP(msiof0_ss2), 4286 SH_PFC_PIN_GROUP(msiof0_rx), 4287 SH_PFC_PIN_GROUP(msiof0_tx), 4288 SH_PFC_PIN_GROUP(msiof0_clk_b), 4289 SH_PFC_PIN_GROUP(msiof0_sync_b), 4290 SH_PFC_PIN_GROUP(msiof0_ss1_b), 4291 SH_PFC_PIN_GROUP(msiof0_ss2_b), 4292 SH_PFC_PIN_GROUP(msiof0_rx_b), 4293 SH_PFC_PIN_GROUP(msiof0_tx_b), 4294 SH_PFC_PIN_GROUP(msiof0_clk_c), 4295 SH_PFC_PIN_GROUP(msiof0_sync_c), 4296 SH_PFC_PIN_GROUP(msiof0_ss1_c), 4297 SH_PFC_PIN_GROUP(msiof0_ss2_c), 4298 SH_PFC_PIN_GROUP(msiof0_rx_c), 4299 SH_PFC_PIN_GROUP(msiof0_tx_c), 4300 SH_PFC_PIN_GROUP(msiof1_clk), 4301 SH_PFC_PIN_GROUP(msiof1_sync), 4302 SH_PFC_PIN_GROUP(msiof1_ss1), 4303 SH_PFC_PIN_GROUP(msiof1_ss2), 4304 SH_PFC_PIN_GROUP(msiof1_rx), 4305 SH_PFC_PIN_GROUP(msiof1_tx), 4306 SH_PFC_PIN_GROUP(msiof1_clk_b), 4307 SH_PFC_PIN_GROUP(msiof1_sync_b), 4308 SH_PFC_PIN_GROUP(msiof1_ss1_b), 4309 SH_PFC_PIN_GROUP(msiof1_ss2_b), 4310 SH_PFC_PIN_GROUP(msiof1_rx_b), 4311 SH_PFC_PIN_GROUP(msiof1_tx_b), 4312 SH_PFC_PIN_GROUP(msiof1_clk_c), 4313 SH_PFC_PIN_GROUP(msiof1_sync_c), 4314 SH_PFC_PIN_GROUP(msiof1_rx_c), 4315 SH_PFC_PIN_GROUP(msiof1_tx_c), 4316 SH_PFC_PIN_GROUP(msiof1_clk_d), 4317 SH_PFC_PIN_GROUP(msiof1_sync_d), 4318 SH_PFC_PIN_GROUP(msiof1_ss1_d), 4319 SH_PFC_PIN_GROUP(msiof1_rx_d), 4320 SH_PFC_PIN_GROUP(msiof1_tx_d), 4321 SH_PFC_PIN_GROUP(msiof1_clk_e), 4322 SH_PFC_PIN_GROUP(msiof1_sync_e), 4323 SH_PFC_PIN_GROUP(msiof1_rx_e), 4324 SH_PFC_PIN_GROUP(msiof1_tx_e), 4325 SH_PFC_PIN_GROUP(msiof2_clk), 4326 SH_PFC_PIN_GROUP(msiof2_sync), 4327 SH_PFC_PIN_GROUP(msiof2_ss1), 4328 SH_PFC_PIN_GROUP(msiof2_ss2), 4329 SH_PFC_PIN_GROUP(msiof2_rx), 4330 SH_PFC_PIN_GROUP(msiof2_tx), 4331 SH_PFC_PIN_GROUP(msiof2_clk_b), 4332 SH_PFC_PIN_GROUP(msiof2_sync_b), 4333 SH_PFC_PIN_GROUP(msiof2_ss1_b), 4334 SH_PFC_PIN_GROUP(msiof2_ss2_b), 4335 SH_PFC_PIN_GROUP(msiof2_rx_b), 4336 SH_PFC_PIN_GROUP(msiof2_tx_b), 4337 SH_PFC_PIN_GROUP(msiof2_clk_c), 4338 SH_PFC_PIN_GROUP(msiof2_sync_c), 4339 SH_PFC_PIN_GROUP(msiof2_rx_c), 4340 SH_PFC_PIN_GROUP(msiof2_tx_c), 4341 SH_PFC_PIN_GROUP(msiof2_clk_d), 4342 SH_PFC_PIN_GROUP(msiof2_sync_d), 4343 SH_PFC_PIN_GROUP(msiof2_ss1_d), 4344 SH_PFC_PIN_GROUP(msiof2_ss2_d), 4345 SH_PFC_PIN_GROUP(msiof2_rx_d), 4346 SH_PFC_PIN_GROUP(msiof2_tx_d), 4347 SH_PFC_PIN_GROUP(msiof2_clk_e), 4348 SH_PFC_PIN_GROUP(msiof2_sync_e), 4349 SH_PFC_PIN_GROUP(msiof2_rx_e), 4350 SH_PFC_PIN_GROUP(msiof2_tx_e), 4351 SH_PFC_PIN_GROUP(qspi_ctrl), 4352 SH_PFC_PIN_GROUP(qspi_data2), 4353 SH_PFC_PIN_GROUP(qspi_data4), 4354 SH_PFC_PIN_GROUP(qspi_ctrl_b), 4355 SH_PFC_PIN_GROUP(qspi_data2_b), 4356 SH_PFC_PIN_GROUP(qspi_data4_b), 4357 SH_PFC_PIN_GROUP(scif0_data), 4358 SH_PFC_PIN_GROUP(scif0_data_b), 4359 SH_PFC_PIN_GROUP(scif0_data_c), 4360 SH_PFC_PIN_GROUP(scif0_data_d), 4361 SH_PFC_PIN_GROUP(scif0_data_e), 4362 SH_PFC_PIN_GROUP(scif1_data), 4363 SH_PFC_PIN_GROUP(scif1_data_b), 4364 SH_PFC_PIN_GROUP(scif1_clk_b), 4365 SH_PFC_PIN_GROUP(scif1_data_c), 4366 SH_PFC_PIN_GROUP(scif1_data_d), 4367 SH_PFC_PIN_GROUP(scif2_data), 4368 SH_PFC_PIN_GROUP(scif2_data_b), 4369 SH_PFC_PIN_GROUP(scif2_clk_b), 4370 SH_PFC_PIN_GROUP(scif2_data_c), 4371 SH_PFC_PIN_GROUP(scif2_data_e), 4372 SH_PFC_PIN_GROUP(scif3_data), 4373 SH_PFC_PIN_GROUP(scif3_clk), 4374 SH_PFC_PIN_GROUP(scif3_data_b), 4375 SH_PFC_PIN_GROUP(scif3_clk_b), 4376 SH_PFC_PIN_GROUP(scif3_data_c), 4377 SH_PFC_PIN_GROUP(scif3_data_d), 4378 SH_PFC_PIN_GROUP(scif4_data), 4379 SH_PFC_PIN_GROUP(scif4_data_b), 4380 SH_PFC_PIN_GROUP(scif4_data_c), 4381 SH_PFC_PIN_GROUP(scif5_data), 4382 SH_PFC_PIN_GROUP(scif5_data_b), 4383 SH_PFC_PIN_GROUP(scifa0_data), 4384 SH_PFC_PIN_GROUP(scifa0_data_b), 4385 SH_PFC_PIN_GROUP(scifa1_data), 4386 SH_PFC_PIN_GROUP(scifa1_clk), 4387 SH_PFC_PIN_GROUP(scifa1_data_b), 4388 SH_PFC_PIN_GROUP(scifa1_clk_b), 4389 SH_PFC_PIN_GROUP(scifa1_data_c), 4390 SH_PFC_PIN_GROUP(scifa2_data), 4391 SH_PFC_PIN_GROUP(scifa2_clk), 4392 SH_PFC_PIN_GROUP(scifa2_data_b), 4393 SH_PFC_PIN_GROUP(scifa3_data), 4394 SH_PFC_PIN_GROUP(scifa3_clk), 4395 SH_PFC_PIN_GROUP(scifa3_data_b), 4396 SH_PFC_PIN_GROUP(scifa3_clk_b), 4397 SH_PFC_PIN_GROUP(scifa3_data_c), 4398 SH_PFC_PIN_GROUP(scifa3_clk_c), 4399 SH_PFC_PIN_GROUP(scifa4_data), 4400 SH_PFC_PIN_GROUP(scifa4_data_b), 4401 SH_PFC_PIN_GROUP(scifa4_data_c), 4402 SH_PFC_PIN_GROUP(scifa5_data), 4403 SH_PFC_PIN_GROUP(scifa5_data_b), 4404 SH_PFC_PIN_GROUP(scifa5_data_c), 4405 SH_PFC_PIN_GROUP(scifb0_data), 4406 SH_PFC_PIN_GROUP(scifb0_clk), 4407 SH_PFC_PIN_GROUP(scifb0_ctrl), 4408 SH_PFC_PIN_GROUP(scifb0_data_b), 4409 SH_PFC_PIN_GROUP(scifb0_clk_b), 4410 SH_PFC_PIN_GROUP(scifb0_ctrl_b), 4411 SH_PFC_PIN_GROUP(scifb0_data_c), 4412 SH_PFC_PIN_GROUP(scifb0_clk_c), 4413 SH_PFC_PIN_GROUP(scifb0_data_d), 4414 SH_PFC_PIN_GROUP(scifb0_clk_d), 4415 SH_PFC_PIN_GROUP(scifb1_data), 4416 SH_PFC_PIN_GROUP(scifb1_clk), 4417 SH_PFC_PIN_GROUP(scifb1_ctrl), 4418 SH_PFC_PIN_GROUP(scifb1_data_b), 4419 SH_PFC_PIN_GROUP(scifb1_clk_b), 4420 SH_PFC_PIN_GROUP(scifb1_data_c), 4421 SH_PFC_PIN_GROUP(scifb1_clk_c), 4422 SH_PFC_PIN_GROUP(scifb1_data_d), 4423 SH_PFC_PIN_GROUP(scifb2_data), 4424 SH_PFC_PIN_GROUP(scifb2_clk), 4425 SH_PFC_PIN_GROUP(scifb2_ctrl), 4426 SH_PFC_PIN_GROUP(scifb2_data_b), 4427 SH_PFC_PIN_GROUP(scifb2_clk_b), 4428 SH_PFC_PIN_GROUP(scifb2_ctrl_b), 4429 SH_PFC_PIN_GROUP(scifb2_data_c), 4430 SH_PFC_PIN_GROUP(scifb2_clk_c), 4431 SH_PFC_PIN_GROUP(scifb2_data_d), 4432 SH_PFC_PIN_GROUP(sdhi0_data1), 4433 SH_PFC_PIN_GROUP(sdhi0_data4), 4434 SH_PFC_PIN_GROUP(sdhi0_ctrl), 4435 SH_PFC_PIN_GROUP(sdhi0_cd), 4436 SH_PFC_PIN_GROUP(sdhi0_wp), 4437 SH_PFC_PIN_GROUP(sdhi1_data1), 4438 SH_PFC_PIN_GROUP(sdhi1_data4), 4439 SH_PFC_PIN_GROUP(sdhi1_ctrl), 4440 SH_PFC_PIN_GROUP(sdhi1_cd), 4441 SH_PFC_PIN_GROUP(sdhi1_wp), 4442 SH_PFC_PIN_GROUP(sdhi2_data1), 4443 SH_PFC_PIN_GROUP(sdhi2_data4), 4444 SH_PFC_PIN_GROUP(sdhi2_ctrl), 4445 SH_PFC_PIN_GROUP(sdhi2_cd), 4446 SH_PFC_PIN_GROUP(sdhi2_wp), 4447 SH_PFC_PIN_GROUP(ssi0_data), 4448 SH_PFC_PIN_GROUP(ssi0_data_b), 4449 SH_PFC_PIN_GROUP(ssi0129_ctrl), 4450 SH_PFC_PIN_GROUP(ssi0129_ctrl_b), 4451 SH_PFC_PIN_GROUP(ssi1_data), 4452 SH_PFC_PIN_GROUP(ssi1_data_b), 4453 SH_PFC_PIN_GROUP(ssi1_ctrl), 4454 SH_PFC_PIN_GROUP(ssi1_ctrl_b), 4455 SH_PFC_PIN_GROUP(ssi2_data), 4456 SH_PFC_PIN_GROUP(ssi2_ctrl), 4457 SH_PFC_PIN_GROUP(ssi3_data), 4458 SH_PFC_PIN_GROUP(ssi34_ctrl), 4459 SH_PFC_PIN_GROUP(ssi4_data), 4460 SH_PFC_PIN_GROUP(ssi4_ctrl), 4461 SH_PFC_PIN_GROUP(ssi5_data), 4462 SH_PFC_PIN_GROUP(ssi5_ctrl), 4463 SH_PFC_PIN_GROUP(ssi6_data), 4464 SH_PFC_PIN_GROUP(ssi6_ctrl), 4465 SH_PFC_PIN_GROUP(ssi7_data), 4466 SH_PFC_PIN_GROUP(ssi7_data_b), 4467 SH_PFC_PIN_GROUP(ssi78_ctrl), 4468 SH_PFC_PIN_GROUP(ssi78_ctrl_b), 4469 SH_PFC_PIN_GROUP(ssi8_data), 4470 SH_PFC_PIN_GROUP(ssi8_data_b), 4471 SH_PFC_PIN_GROUP(ssi9_data), 4472 SH_PFC_PIN_GROUP(ssi9_data_b), 4473 SH_PFC_PIN_GROUP(ssi9_ctrl), 4474 SH_PFC_PIN_GROUP(ssi9_ctrl_b), 4475 SH_PFC_PIN_GROUP(usb0), 4476 SH_PFC_PIN_GROUP(usb1), 4477 VIN_DATA_PIN_GROUP(vin0_data, 24), 4478 VIN_DATA_PIN_GROUP(vin0_data, 20), 4479 SH_PFC_PIN_GROUP(vin0_data18), 4480 VIN_DATA_PIN_GROUP(vin0_data, 16), 4481 VIN_DATA_PIN_GROUP(vin0_data, 12), 4482 VIN_DATA_PIN_GROUP(vin0_data, 10), 4483 VIN_DATA_PIN_GROUP(vin0_data, 8), 4484 SH_PFC_PIN_GROUP(vin0_sync), 4485 SH_PFC_PIN_GROUP(vin0_field), 4486 SH_PFC_PIN_GROUP(vin0_clkenb), 4487 SH_PFC_PIN_GROUP(vin0_clk), 4488 SH_PFC_PIN_GROUP(vin1_data8), 4489 SH_PFC_PIN_GROUP(vin1_sync), 4490 SH_PFC_PIN_GROUP(vin1_field), 4491 SH_PFC_PIN_GROUP(vin1_clkenb), 4492 SH_PFC_PIN_GROUP(vin1_clk), 4493 VIN_DATA_PIN_GROUP(vin1_b_data, 24), 4494 VIN_DATA_PIN_GROUP(vin1_b_data, 20), 4495 SH_PFC_PIN_GROUP(vin1_b_data18), 4496 VIN_DATA_PIN_GROUP(vin1_b_data, 16), 4497 VIN_DATA_PIN_GROUP(vin1_b_data, 12), 4498 VIN_DATA_PIN_GROUP(vin1_b_data, 10), 4499 VIN_DATA_PIN_GROUP(vin1_b_data, 8), 4500 SH_PFC_PIN_GROUP(vin1_b_sync), 4501 SH_PFC_PIN_GROUP(vin1_b_field), 4502 SH_PFC_PIN_GROUP(vin1_b_clkenb), 4503 SH_PFC_PIN_GROUP(vin1_b_clk), 4504 SH_PFC_PIN_GROUP(vin2_data8), 4505 SH_PFC_PIN_GROUP(vin2_sync), 4506 SH_PFC_PIN_GROUP(vin2_field), 4507 SH_PFC_PIN_GROUP(vin2_clkenb), 4508 SH_PFC_PIN_GROUP(vin2_clk), 4509 }; 4510 4511 static const char * const audio_clk_groups[] = { 4512 "audio_clk_a", 4513 "audio_clk_b", 4514 "audio_clk_b_b", 4515 "audio_clk_c", 4516 "audio_clkout", 4517 }; 4518 4519 static const char * const can0_groups[] = { 4520 "can0_data", 4521 "can0_data_b", 4522 "can0_data_c", 4523 "can0_data_d", 4524 "can0_data_e", 4525 "can0_data_f", 4526 "can_clk", 4527 "can_clk_b", 4528 "can_clk_c", 4529 "can_clk_d", 4530 }; 4531 4532 static const char * const can1_groups[] = { 4533 "can1_data", 4534 "can1_data_b", 4535 "can1_data_c", 4536 "can1_data_d", 4537 "can_clk", 4538 "can_clk_b", 4539 "can_clk_c", 4540 "can_clk_d", 4541 }; 4542 4543 static const char * const du_groups[] = { 4544 "du_rgb666", 4545 "du_rgb888", 4546 "du_clk_out_0", 4547 "du_clk_out_1", 4548 "du_sync", 4549 "du_oddf", 4550 "du_cde", 4551 "du_disp", 4552 }; 4553 4554 static const char * const du0_groups[] = { 4555 "du0_clk_in", 4556 }; 4557 4558 static const char * const du1_groups[] = { 4559 "du1_clk_in", 4560 "du1_clk_in_b", 4561 "du1_clk_in_c", 4562 }; 4563 4564 static const char * const eth_groups[] = { 4565 "eth_link", 4566 "eth_magic", 4567 "eth_mdio", 4568 "eth_rmii", 4569 }; 4570 4571 static const char * const hscif0_groups[] = { 4572 "hscif0_data", 4573 "hscif0_clk", 4574 "hscif0_ctrl", 4575 "hscif0_data_b", 4576 "hscif0_ctrl_b", 4577 "hscif0_data_c", 4578 "hscif0_clk_c", 4579 }; 4580 4581 static const char * const hscif1_groups[] = { 4582 "hscif1_data", 4583 "hscif1_clk", 4584 "hscif1_ctrl", 4585 "hscif1_data_b", 4586 "hscif1_data_c", 4587 "hscif1_clk_c", 4588 "hscif1_ctrl_c", 4589 "hscif1_data_d", 4590 "hscif1_data_e", 4591 "hscif1_clk_e", 4592 "hscif1_ctrl_e", 4593 }; 4594 4595 static const char * const hscif2_groups[] = { 4596 "hscif2_data", 4597 "hscif2_clk", 4598 "hscif2_ctrl", 4599 "hscif2_data_b", 4600 "hscif2_ctrl_b", 4601 "hscif2_data_c", 4602 "hscif2_clk_c", 4603 "hscif2_data_d", 4604 }; 4605 4606 static const char * const i2c0_groups[] = { 4607 "i2c0", 4608 "i2c0_b", 4609 "i2c0_c", 4610 }; 4611 4612 static const char * const i2c1_groups[] = { 4613 "i2c1", 4614 "i2c1_b", 4615 "i2c1_c", 4616 "i2c1_d", 4617 "i2c1_e", 4618 }; 4619 4620 static const char * const i2c2_groups[] = { 4621 "i2c2", 4622 "i2c2_b", 4623 "i2c2_c", 4624 "i2c2_d", 4625 }; 4626 4627 static const char * const i2c3_groups[] = { 4628 "i2c3", 4629 "i2c3_b", 4630 "i2c3_c", 4631 "i2c3_d", 4632 }; 4633 4634 static const char * const i2c4_groups[] = { 4635 "i2c4", 4636 "i2c4_b", 4637 "i2c4_c", 4638 }; 4639 4640 static const char * const i2c7_groups[] = { 4641 "i2c7", 4642 "i2c7_b", 4643 "i2c7_c", 4644 }; 4645 4646 static const char * const i2c8_groups[] = { 4647 "i2c8", 4648 "i2c8_b", 4649 "i2c8_c", 4650 }; 4651 4652 static const char * const intc_groups[] = { 4653 "intc_irq0", 4654 "intc_irq1", 4655 "intc_irq2", 4656 "intc_irq3", 4657 }; 4658 4659 static const char * const mlb_groups[] = { 4660 "mlb_3pin", 4661 }; 4662 4663 static const char * const mmc_groups[] = { 4664 "mmc_data1", 4665 "mmc_data4", 4666 "mmc_data8", 4667 "mmc_ctrl", 4668 }; 4669 4670 static const char * const msiof0_groups[] = { 4671 "msiof0_clk", 4672 "msiof0_sync", 4673 "msiof0_ss1", 4674 "msiof0_ss2", 4675 "msiof0_rx", 4676 "msiof0_tx", 4677 "msiof0_clk_b", 4678 "msiof0_sync_b", 4679 "msiof0_ss1_b", 4680 "msiof0_ss2_b", 4681 "msiof0_rx_b", 4682 "msiof0_tx_b", 4683 "msiof0_clk_c", 4684 "msiof0_sync_c", 4685 "msiof0_ss1_c", 4686 "msiof0_ss2_c", 4687 "msiof0_rx_c", 4688 "msiof0_tx_c", 4689 }; 4690 4691 static const char * const msiof1_groups[] = { 4692 "msiof1_clk", 4693 "msiof1_sync", 4694 "msiof1_ss1", 4695 "msiof1_ss2", 4696 "msiof1_rx", 4697 "msiof1_tx", 4698 "msiof1_clk_b", 4699 "msiof1_sync_b", 4700 "msiof1_ss1_b", 4701 "msiof1_ss2_b", 4702 "msiof1_rx_b", 4703 "msiof1_tx_b", 4704 "msiof1_clk_c", 4705 "msiof1_sync_c", 4706 "msiof1_rx_c", 4707 "msiof1_tx_c", 4708 "msiof1_clk_d", 4709 "msiof1_sync_d", 4710 "msiof1_ss1_d", 4711 "msiof1_rx_d", 4712 "msiof1_tx_d", 4713 "msiof1_clk_e", 4714 "msiof1_sync_e", 4715 "msiof1_rx_e", 4716 "msiof1_tx_e", 4717 }; 4718 4719 static const char * const msiof2_groups[] = { 4720 "msiof2_clk", 4721 "msiof2_sync", 4722 "msiof2_ss1", 4723 "msiof2_ss2", 4724 "msiof2_rx", 4725 "msiof2_tx", 4726 "msiof2_clk_b", 4727 "msiof2_sync_b", 4728 "msiof2_ss1_b", 4729 "msiof2_ss2_b", 4730 "msiof2_rx_b", 4731 "msiof2_tx_b", 4732 "msiof2_clk_c", 4733 "msiof2_sync_c", 4734 "msiof2_rx_c", 4735 "msiof2_tx_c", 4736 "msiof2_clk_d", 4737 "msiof2_sync_d", 4738 "msiof2_ss1_d", 4739 "msiof2_ss2_d", 4740 "msiof2_rx_d", 4741 "msiof2_tx_d", 4742 "msiof2_clk_e", 4743 "msiof2_sync_e", 4744 "msiof2_rx_e", 4745 "msiof2_tx_e", 4746 }; 4747 4748 static const char * const qspi_groups[] = { 4749 "qspi_ctrl", 4750 "qspi_data2", 4751 "qspi_data4", 4752 "qspi_ctrl_b", 4753 "qspi_data2_b", 4754 "qspi_data4_b", 4755 }; 4756 4757 static const char * const scif0_groups[] = { 4758 "scif0_data", 4759 "scif0_data_b", 4760 "scif0_data_c", 4761 "scif0_data_d", 4762 "scif0_data_e", 4763 }; 4764 4765 static const char * const scif1_groups[] = { 4766 "scif1_data", 4767 "scif1_data_b", 4768 "scif1_clk_b", 4769 "scif1_data_c", 4770 "scif1_data_d", 4771 }; 4772 4773 static const char * const scif2_groups[] = { 4774 "scif2_data", 4775 "scif2_data_b", 4776 "scif2_clk_b", 4777 "scif2_data_c", 4778 "scif2_data_e", 4779 }; 4780 static const char * const scif3_groups[] = { 4781 "scif3_data", 4782 "scif3_clk", 4783 "scif3_data_b", 4784 "scif3_clk_b", 4785 "scif3_data_c", 4786 "scif3_data_d", 4787 }; 4788 static const char * const scif4_groups[] = { 4789 "scif4_data", 4790 "scif4_data_b", 4791 "scif4_data_c", 4792 }; 4793 static const char * const scif5_groups[] = { 4794 "scif5_data", 4795 "scif5_data_b", 4796 }; 4797 static const char * const scifa0_groups[] = { 4798 "scifa0_data", 4799 "scifa0_data_b", 4800 }; 4801 static const char * const scifa1_groups[] = { 4802 "scifa1_data", 4803 "scifa1_clk", 4804 "scifa1_data_b", 4805 "scifa1_clk_b", 4806 "scifa1_data_c", 4807 }; 4808 static const char * const scifa2_groups[] = { 4809 "scifa2_data", 4810 "scifa2_clk", 4811 "scifa2_data_b", 4812 }; 4813 static const char * const scifa3_groups[] = { 4814 "scifa3_data", 4815 "scifa3_clk", 4816 "scifa3_data_b", 4817 "scifa3_clk_b", 4818 "scifa3_data_c", 4819 "scifa3_clk_c", 4820 }; 4821 static const char * const scifa4_groups[] = { 4822 "scifa4_data", 4823 "scifa4_data_b", 4824 "scifa4_data_c", 4825 }; 4826 static const char * const scifa5_groups[] = { 4827 "scifa5_data", 4828 "scifa5_data_b", 4829 "scifa5_data_c", 4830 }; 4831 static const char * const scifb0_groups[] = { 4832 "scifb0_data", 4833 "scifb0_clk", 4834 "scifb0_ctrl", 4835 "scifb0_data_b", 4836 "scifb0_clk_b", 4837 "scifb0_ctrl_b", 4838 "scifb0_data_c", 4839 "scifb0_clk_c", 4840 "scifb0_data_d", 4841 "scifb0_clk_d", 4842 }; 4843 static const char * const scifb1_groups[] = { 4844 "scifb1_data", 4845 "scifb1_clk", 4846 "scifb1_ctrl", 4847 "scifb1_data_b", 4848 "scifb1_clk_b", 4849 "scifb1_data_c", 4850 "scifb1_clk_c", 4851 "scifb1_data_d", 4852 }; 4853 static const char * const scifb2_groups[] = { 4854 "scifb2_data", 4855 "scifb2_clk", 4856 "scifb2_ctrl", 4857 "scifb2_data_b", 4858 "scifb2_clk_b", 4859 "scifb2_ctrl_b", 4860 "scifb0_data_c", 4861 "scifb2_clk_c", 4862 "scifb2_data_d", 4863 }; 4864 4865 static const char * const sdhi0_groups[] = { 4866 "sdhi0_data1", 4867 "sdhi0_data4", 4868 "sdhi0_ctrl", 4869 "sdhi0_cd", 4870 "sdhi0_wp", 4871 }; 4872 4873 static const char * const sdhi1_groups[] = { 4874 "sdhi1_data1", 4875 "sdhi1_data4", 4876 "sdhi1_ctrl", 4877 "sdhi1_cd", 4878 "sdhi1_wp", 4879 }; 4880 4881 static const char * const sdhi2_groups[] = { 4882 "sdhi2_data1", 4883 "sdhi2_data4", 4884 "sdhi2_ctrl", 4885 "sdhi2_cd", 4886 "sdhi2_wp", 4887 }; 4888 4889 static const char * const ssi_groups[] = { 4890 "ssi0_data", 4891 "ssi0_data_b", 4892 "ssi0129_ctrl", 4893 "ssi0129_ctrl_b", 4894 "ssi1_data", 4895 "ssi1_data_b", 4896 "ssi1_ctrl", 4897 "ssi1_ctrl_b", 4898 "ssi2_data", 4899 "ssi2_ctrl", 4900 "ssi3_data", 4901 "ssi34_ctrl", 4902 "ssi4_data", 4903 "ssi4_ctrl", 4904 "ssi5_data", 4905 "ssi5_ctrl", 4906 "ssi6_data", 4907 "ssi6_ctrl", 4908 "ssi7_data", 4909 "ssi7_data_b", 4910 "ssi78_ctrl", 4911 "ssi78_ctrl_b", 4912 "ssi8_data", 4913 "ssi8_data_b", 4914 "ssi9_data", 4915 "ssi9_data_b", 4916 "ssi9_ctrl", 4917 "ssi9_ctrl_b", 4918 }; 4919 4920 static const char * const usb0_groups[] = { 4921 "usb0", 4922 }; 4923 static const char * const usb1_groups[] = { 4924 "usb1", 4925 }; 4926 4927 static const char * const vin0_groups[] = { 4928 "vin0_data24", 4929 "vin0_data20", 4930 "vin0_data18", 4931 "vin0_data16", 4932 "vin0_data12", 4933 "vin0_data10", 4934 "vin0_data8", 4935 "vin0_sync", 4936 "vin0_field", 4937 "vin0_clkenb", 4938 "vin0_clk", 4939 }; 4940 4941 static const char * const vin1_groups[] = { 4942 "vin1_data8", 4943 "vin1_sync", 4944 "vin1_field", 4945 "vin1_clkenb", 4946 "vin1_clk", 4947 "vin1_b_data24", 4948 "vin1_b_data20", 4949 "vin1_b_data18", 4950 "vin1_b_data16", 4951 "vin1_b_data12", 4952 "vin1_b_data10", 4953 "vin1_b_data8", 4954 "vin1_b_sync", 4955 "vin1_b_field", 4956 "vin1_b_clkenb", 4957 "vin1_b_clk", 4958 }; 4959 4960 static const char * const vin2_groups[] = { 4961 "vin2_data8", 4962 "vin2_sync", 4963 "vin2_field", 4964 "vin2_clkenb", 4965 "vin2_clk", 4966 }; 4967 4968 static const struct sh_pfc_function pinmux_functions[] = { 4969 SH_PFC_FUNCTION(audio_clk), 4970 SH_PFC_FUNCTION(can0), 4971 SH_PFC_FUNCTION(can1), 4972 SH_PFC_FUNCTION(du), 4973 SH_PFC_FUNCTION(du0), 4974 SH_PFC_FUNCTION(du1), 4975 SH_PFC_FUNCTION(eth), 4976 SH_PFC_FUNCTION(hscif0), 4977 SH_PFC_FUNCTION(hscif1), 4978 SH_PFC_FUNCTION(hscif2), 4979 SH_PFC_FUNCTION(i2c0), 4980 SH_PFC_FUNCTION(i2c1), 4981 SH_PFC_FUNCTION(i2c2), 4982 SH_PFC_FUNCTION(i2c3), 4983 SH_PFC_FUNCTION(i2c4), 4984 SH_PFC_FUNCTION(i2c7), 4985 SH_PFC_FUNCTION(i2c8), 4986 SH_PFC_FUNCTION(intc), 4987 SH_PFC_FUNCTION(mlb), 4988 SH_PFC_FUNCTION(mmc), 4989 SH_PFC_FUNCTION(msiof0), 4990 SH_PFC_FUNCTION(msiof1), 4991 SH_PFC_FUNCTION(msiof2), 4992 SH_PFC_FUNCTION(qspi), 4993 SH_PFC_FUNCTION(scif0), 4994 SH_PFC_FUNCTION(scif1), 4995 SH_PFC_FUNCTION(scif2), 4996 SH_PFC_FUNCTION(scif3), 4997 SH_PFC_FUNCTION(scif4), 4998 SH_PFC_FUNCTION(scif5), 4999 SH_PFC_FUNCTION(scifa0), 5000 SH_PFC_FUNCTION(scifa1), 5001 SH_PFC_FUNCTION(scifa2), 5002 SH_PFC_FUNCTION(scifa3), 5003 SH_PFC_FUNCTION(scifa4), 5004 SH_PFC_FUNCTION(scifa5), 5005 SH_PFC_FUNCTION(scifb0), 5006 SH_PFC_FUNCTION(scifb1), 5007 SH_PFC_FUNCTION(scifb2), 5008 SH_PFC_FUNCTION(sdhi0), 5009 SH_PFC_FUNCTION(sdhi1), 5010 SH_PFC_FUNCTION(sdhi2), 5011 SH_PFC_FUNCTION(ssi), 5012 SH_PFC_FUNCTION(usb0), 5013 SH_PFC_FUNCTION(usb1), 5014 SH_PFC_FUNCTION(vin0), 5015 SH_PFC_FUNCTION(vin1), 5016 SH_PFC_FUNCTION(vin2), 5017 }; 5018 5019 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 5020 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { 5021 GP_0_31_FN, FN_IP1_22_20, 5022 GP_0_30_FN, FN_IP1_19_17, 5023 GP_0_29_FN, FN_IP1_16_14, 5024 GP_0_28_FN, FN_IP1_13_11, 5025 GP_0_27_FN, FN_IP1_10_8, 5026 GP_0_26_FN, FN_IP1_7_6, 5027 GP_0_25_FN, FN_IP1_5_4, 5028 GP_0_24_FN, FN_IP1_3_2, 5029 GP_0_23_FN, FN_IP1_1_0, 5030 GP_0_22_FN, FN_IP0_30_29, 5031 GP_0_21_FN, FN_IP0_28_27, 5032 GP_0_20_FN, FN_IP0_26_25, 5033 GP_0_19_FN, FN_IP0_24_23, 5034 GP_0_18_FN, FN_IP0_22_21, 5035 GP_0_17_FN, FN_IP0_20_19, 5036 GP_0_16_FN, FN_IP0_18_16, 5037 GP_0_15_FN, FN_IP0_15, 5038 GP_0_14_FN, FN_IP0_14, 5039 GP_0_13_FN, FN_IP0_13, 5040 GP_0_12_FN, FN_IP0_12, 5041 GP_0_11_FN, FN_IP0_11, 5042 GP_0_10_FN, FN_IP0_10, 5043 GP_0_9_FN, FN_IP0_9, 5044 GP_0_8_FN, FN_IP0_8, 5045 GP_0_7_FN, FN_IP0_7, 5046 GP_0_6_FN, FN_IP0_6, 5047 GP_0_5_FN, FN_IP0_5, 5048 GP_0_4_FN, FN_IP0_4, 5049 GP_0_3_FN, FN_IP0_3, 5050 GP_0_2_FN, FN_IP0_2, 5051 GP_0_1_FN, FN_IP0_1, 5052 GP_0_0_FN, FN_IP0_0, } 5053 }, 5054 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { 5055 0, 0, 5056 0, 0, 5057 0, 0, 5058 0, 0, 5059 0, 0, 5060 0, 0, 5061 GP_1_25_FN, FN_IP3_21_20, 5062 GP_1_24_FN, FN_IP3_19_18, 5063 GP_1_23_FN, FN_IP3_17_16, 5064 GP_1_22_FN, FN_IP3_15_14, 5065 GP_1_21_FN, FN_IP3_13_12, 5066 GP_1_20_FN, FN_IP3_11_9, 5067 GP_1_19_FN, FN_RD_N, 5068 GP_1_18_FN, FN_IP3_8_6, 5069 GP_1_17_FN, FN_IP3_5_3, 5070 GP_1_16_FN, FN_IP3_2_0, 5071 GP_1_15_FN, FN_IP2_29_27, 5072 GP_1_14_FN, FN_IP2_26_25, 5073 GP_1_13_FN, FN_IP2_24_23, 5074 GP_1_12_FN, FN_EX_CS0_N, 5075 GP_1_11_FN, FN_IP2_22_21, 5076 GP_1_10_FN, FN_IP2_20_19, 5077 GP_1_9_FN, FN_IP2_18_16, 5078 GP_1_8_FN, FN_IP2_15_13, 5079 GP_1_7_FN, FN_IP2_12_10, 5080 GP_1_6_FN, FN_IP2_9_7, 5081 GP_1_5_FN, FN_IP2_6_5, 5082 GP_1_4_FN, FN_IP2_4_3, 5083 GP_1_3_FN, FN_IP2_2_0, 5084 GP_1_2_FN, FN_IP1_31_29, 5085 GP_1_1_FN, FN_IP1_28_26, 5086 GP_1_0_FN, FN_IP1_25_23, } 5087 }, 5088 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { 5089 GP_2_31_FN, FN_IP6_7_6, 5090 GP_2_30_FN, FN_IP6_5_3, 5091 GP_2_29_FN, FN_IP6_2_0, 5092 GP_2_28_FN, FN_AUDIO_CLKA, 5093 GP_2_27_FN, FN_IP5_31_29, 5094 GP_2_26_FN, FN_IP5_28_26, 5095 GP_2_25_FN, FN_IP5_25_24, 5096 GP_2_24_FN, FN_IP5_23_22, 5097 GP_2_23_FN, FN_IP5_21_20, 5098 GP_2_22_FN, FN_IP5_19_17, 5099 GP_2_21_FN, FN_IP5_16_15, 5100 GP_2_20_FN, FN_IP5_14_12, 5101 GP_2_19_FN, FN_IP5_11_9, 5102 GP_2_18_FN, FN_IP5_8_6, 5103 GP_2_17_FN, FN_IP5_5_3, 5104 GP_2_16_FN, FN_IP5_2_0, 5105 GP_2_15_FN, FN_IP4_30_28, 5106 GP_2_14_FN, FN_IP4_27_26, 5107 GP_2_13_FN, FN_IP4_25_24, 5108 GP_2_12_FN, FN_IP4_23_22, 5109 GP_2_11_FN, FN_IP4_21, 5110 GP_2_10_FN, FN_IP4_20, 5111 GP_2_9_FN, FN_IP4_19, 5112 GP_2_8_FN, FN_IP4_18_16, 5113 GP_2_7_FN, FN_IP4_15_13, 5114 GP_2_6_FN, FN_IP4_12_10, 5115 GP_2_5_FN, FN_IP4_9_8, 5116 GP_2_4_FN, FN_IP4_7_5, 5117 GP_2_3_FN, FN_IP4_4_2, 5118 GP_2_2_FN, FN_IP4_1_0, 5119 GP_2_1_FN, FN_IP3_30_28, 5120 GP_2_0_FN, FN_IP3_27_25 } 5121 }, 5122 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { 5123 GP_3_31_FN, FN_IP9_18_17, 5124 GP_3_30_FN, FN_IP9_16, 5125 GP_3_29_FN, FN_IP9_15_13, 5126 GP_3_28_FN, FN_IP9_12, 5127 GP_3_27_FN, FN_IP9_11, 5128 GP_3_26_FN, FN_IP9_10_8, 5129 GP_3_25_FN, FN_IP9_7, 5130 GP_3_24_FN, FN_IP9_6, 5131 GP_3_23_FN, FN_IP9_5_3, 5132 GP_3_22_FN, FN_IP9_2_0, 5133 GP_3_21_FN, FN_IP8_30_28, 5134 GP_3_20_FN, FN_IP8_27_26, 5135 GP_3_19_FN, FN_IP8_25_24, 5136 GP_3_18_FN, FN_IP8_23_21, 5137 GP_3_17_FN, FN_IP8_20_18, 5138 GP_3_16_FN, FN_IP8_17_15, 5139 GP_3_15_FN, FN_IP8_14_12, 5140 GP_3_14_FN, FN_IP8_11_9, 5141 GP_3_13_FN, FN_IP8_8_6, 5142 GP_3_12_FN, FN_IP8_5_3, 5143 GP_3_11_FN, FN_IP8_2_0, 5144 GP_3_10_FN, FN_IP7_29_27, 5145 GP_3_9_FN, FN_IP7_26_24, 5146 GP_3_8_FN, FN_IP7_23_21, 5147 GP_3_7_FN, FN_IP7_20_19, 5148 GP_3_6_FN, FN_IP7_18_17, 5149 GP_3_5_FN, FN_IP7_16_15, 5150 GP_3_4_FN, FN_IP7_14_13, 5151 GP_3_3_FN, FN_IP7_12_11, 5152 GP_3_2_FN, FN_IP7_10_9, 5153 GP_3_1_FN, FN_IP7_8_6, 5154 GP_3_0_FN, FN_IP7_5_3 } 5155 }, 5156 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { 5157 GP_4_31_FN, FN_IP15_5_4, 5158 GP_4_30_FN, FN_IP15_3_2, 5159 GP_4_29_FN, FN_IP15_1_0, 5160 GP_4_28_FN, FN_IP11_8_6, 5161 GP_4_27_FN, FN_IP11_5_3, 5162 GP_4_26_FN, FN_IP11_2_0, 5163 GP_4_25_FN, FN_IP10_31_29, 5164 GP_4_24_FN, FN_IP10_28_27, 5165 GP_4_23_FN, FN_IP10_26_25, 5166 GP_4_22_FN, FN_IP10_24_22, 5167 GP_4_21_FN, FN_IP10_21_19, 5168 GP_4_20_FN, FN_IP10_18_17, 5169 GP_4_19_FN, FN_IP10_16_15, 5170 GP_4_18_FN, FN_IP10_14_12, 5171 GP_4_17_FN, FN_IP10_11_9, 5172 GP_4_16_FN, FN_IP10_8_6, 5173 GP_4_15_FN, FN_IP10_5_3, 5174 GP_4_14_FN, FN_IP10_2_0, 5175 GP_4_13_FN, FN_IP9_31_29, 5176 GP_4_12_FN, FN_VI0_DATA7_VI0_B7, 5177 GP_4_11_FN, FN_VI0_DATA6_VI0_B6, 5178 GP_4_10_FN, FN_VI0_DATA5_VI0_B5, 5179 GP_4_9_FN, FN_VI0_DATA4_VI0_B4, 5180 GP_4_8_FN, FN_IP9_28_27, 5181 GP_4_7_FN, FN_VI0_DATA2_VI0_B2, 5182 GP_4_6_FN, FN_VI0_DATA1_VI0_B1, 5183 GP_4_5_FN, FN_VI0_DATA0_VI0_B0, 5184 GP_4_4_FN, FN_IP9_26_25, 5185 GP_4_3_FN, FN_IP9_24_23, 5186 GP_4_2_FN, FN_IP9_22_21, 5187 GP_4_1_FN, FN_IP9_20_19, 5188 GP_4_0_FN, FN_VI0_CLK } 5189 }, 5190 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { 5191 GP_5_31_FN, FN_IP3_24_22, 5192 GP_5_30_FN, FN_IP13_9_7, 5193 GP_5_29_FN, FN_IP13_6_5, 5194 GP_5_28_FN, FN_IP13_4_3, 5195 GP_5_27_FN, FN_IP13_2_0, 5196 GP_5_26_FN, FN_IP12_29_27, 5197 GP_5_25_FN, FN_IP12_26_24, 5198 GP_5_24_FN, FN_IP12_23_22, 5199 GP_5_23_FN, FN_IP12_21_20, 5200 GP_5_22_FN, FN_IP12_19_18, 5201 GP_5_21_FN, FN_IP12_17_16, 5202 GP_5_20_FN, FN_IP12_15_13, 5203 GP_5_19_FN, FN_IP12_12_10, 5204 GP_5_18_FN, FN_IP12_9_7, 5205 GP_5_17_FN, FN_IP12_6_4, 5206 GP_5_16_FN, FN_IP12_3_2, 5207 GP_5_15_FN, FN_IP12_1_0, 5208 GP_5_14_FN, FN_IP11_31_30, 5209 GP_5_13_FN, FN_IP11_29_28, 5210 GP_5_12_FN, FN_IP11_27, 5211 GP_5_11_FN, FN_IP11_26, 5212 GP_5_10_FN, FN_IP11_25, 5213 GP_5_9_FN, FN_IP11_24, 5214 GP_5_8_FN, FN_IP11_23, 5215 GP_5_7_FN, FN_IP11_22, 5216 GP_5_6_FN, FN_IP11_21, 5217 GP_5_5_FN, FN_IP11_20, 5218 GP_5_4_FN, FN_IP11_19, 5219 GP_5_3_FN, FN_IP11_18_17, 5220 GP_5_2_FN, FN_IP11_16_15, 5221 GP_5_1_FN, FN_IP11_14_12, 5222 GP_5_0_FN, FN_IP11_11_9 } 5223 }, 5224 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) { 5225 GP_6_31_FN, FN_DU0_DOTCLKIN, 5226 GP_6_30_FN, FN_USB1_OVC, 5227 GP_6_29_FN, FN_IP14_31_29, 5228 GP_6_28_FN, FN_IP14_28_26, 5229 GP_6_27_FN, FN_IP14_25_23, 5230 GP_6_26_FN, FN_IP14_22_20, 5231 GP_6_25_FN, FN_IP14_19_17, 5232 GP_6_24_FN, FN_IP14_16_14, 5233 GP_6_23_FN, FN_IP14_13_11, 5234 GP_6_22_FN, FN_IP14_10_8, 5235 GP_6_21_FN, FN_IP14_7, 5236 GP_6_20_FN, FN_IP14_6, 5237 GP_6_19_FN, FN_IP14_5, 5238 GP_6_18_FN, FN_IP14_4, 5239 GP_6_17_FN, FN_IP14_3, 5240 GP_6_16_FN, FN_IP14_2, 5241 GP_6_15_FN, FN_IP14_1_0, 5242 GP_6_14_FN, FN_IP13_30_28, 5243 GP_6_13_FN, FN_IP13_27, 5244 GP_6_12_FN, FN_IP13_26, 5245 GP_6_11_FN, FN_IP13_25, 5246 GP_6_10_FN, FN_IP13_24_23, 5247 GP_6_9_FN, FN_IP13_22, 5248 GP_6_8_FN, FN_SD1_CLK, 5249 GP_6_7_FN, FN_IP13_21_19, 5250 GP_6_6_FN, FN_IP13_18_16, 5251 GP_6_5_FN, FN_IP13_15, 5252 GP_6_4_FN, FN_IP13_14, 5253 GP_6_3_FN, FN_IP13_13, 5254 GP_6_2_FN, FN_IP13_12, 5255 GP_6_1_FN, FN_IP13_11, 5256 GP_6_0_FN, FN_IP13_10 } 5257 }, 5258 { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) { 5259 0, 0, 5260 0, 0, 5261 0, 0, 5262 0, 0, 5263 0, 0, 5264 0, 0, 5265 GP_7_25_FN, FN_USB1_PWEN, 5266 GP_7_24_FN, FN_USB0_OVC, 5267 GP_7_23_FN, FN_USB0_PWEN, 5268 GP_7_22_FN, FN_IP15_14_12, 5269 GP_7_21_FN, FN_IP15_11_9, 5270 GP_7_20_FN, FN_IP15_8_6, 5271 GP_7_19_FN, FN_IP7_2_0, 5272 GP_7_18_FN, FN_IP6_29_27, 5273 GP_7_17_FN, FN_IP6_26_24, 5274 GP_7_16_FN, FN_IP6_23_21, 5275 GP_7_15_FN, FN_IP6_20_19, 5276 GP_7_14_FN, FN_IP6_18_16, 5277 GP_7_13_FN, FN_IP6_15_14, 5278 GP_7_12_FN, FN_IP6_13_12, 5279 GP_7_11_FN, FN_IP6_11_10, 5280 GP_7_10_FN, FN_IP6_9_8, 5281 GP_7_9_FN, FN_IP16_11_10, 5282 GP_7_8_FN, FN_IP16_9_8, 5283 GP_7_7_FN, FN_IP16_7_6, 5284 GP_7_6_FN, FN_IP16_5_3, 5285 GP_7_5_FN, FN_IP16_2_0, 5286 GP_7_4_FN, FN_IP15_29_27, 5287 GP_7_3_FN, FN_IP15_26_24, 5288 GP_7_2_FN, FN_IP15_23_21, 5289 GP_7_1_FN, FN_IP15_20_18, 5290 GP_7_0_FN, FN_IP15_17_15 } 5291 }, 5292 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, 5293 1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, 1, 1, 1, 1, 5294 1, 1, 1, 1, 1, 1, 1, 1) { 5295 /* IP0_31 [1] */ 5296 0, 0, 5297 /* IP0_30_29 [2] */ 5298 FN_A6, FN_MSIOF1_SCK, 5299 0, 0, 5300 /* IP0_28_27 [2] */ 5301 FN_A5, FN_MSIOF0_RXD_B, 5302 0, 0, 5303 /* IP0_26_25 [2] */ 5304 FN_A4, FN_MSIOF0_TXD_B, 5305 0, 0, 5306 /* IP0_24_23 [2] */ 5307 FN_A3, FN_MSIOF0_SS2_B, 5308 0, 0, 5309 /* IP0_22_21 [2] */ 5310 FN_A2, FN_MSIOF0_SS1_B, 5311 0, 0, 5312 /* IP0_20_19 [2] */ 5313 FN_A1, FN_MSIOF0_SYNC_B, 5314 0, 0, 5315 /* IP0_18_16 [3] */ 5316 FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_SCL0_C, FN_PWM2_B, 5317 0, 0, 0, 5318 /* IP0_15 [1] */ 5319 FN_D15, 0, 5320 /* IP0_14 [1] */ 5321 FN_D14, 0, 5322 /* IP0_13 [1] */ 5323 FN_D13, 0, 5324 /* IP0_12 [1] */ 5325 FN_D12, 0, 5326 /* IP0_11 [1] */ 5327 FN_D11, 0, 5328 /* IP0_10 [1] */ 5329 FN_D10, 0, 5330 /* IP0_9 [1] */ 5331 FN_D9, 0, 5332 /* IP0_8 [1] */ 5333 FN_D8, 0, 5334 /* IP0_7 [1] */ 5335 FN_D7, 0, 5336 /* IP0_6 [1] */ 5337 FN_D6, 0, 5338 /* IP0_5 [1] */ 5339 FN_D5, 0, 5340 /* IP0_4 [1] */ 5341 FN_D4, 0, 5342 /* IP0_3 [1] */ 5343 FN_D3, 0, 5344 /* IP0_2 [1] */ 5345 FN_D2, 0, 5346 /* IP0_1 [1] */ 5347 FN_D1, 0, 5348 /* IP0_0 [1] */ 5349 FN_D0, 0, } 5350 }, 5351 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, 5352 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2) { 5353 /* IP1_31_29 [3] */ 5354 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C, 5355 0, 0, 0, 5356 /* IP1_28_26 [3] */ 5357 FN_A17, FN_DACK2_B, 0, FN_SDA0_C, 5358 0, 0, 0, 0, 5359 /* IP1_25_23 [3] */ 5360 FN_A16, FN_DREQ2_B, FN_FMCLK_C, 0, FN_SCIFA1_SCK_B, 5361 0, 0, 0, 5362 /* IP1_22_20 [3] */ 5363 FN_A15, FN_BPFCLK_C, 5364 0, 0, 0, 0, 0, 0, 5365 /* IP1_19_17 [3] */ 5366 FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D, 5367 0, 0, 0, 5368 /* IP1_16_14 [3] */ 5369 FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D, 5370 0, 0, 0, 0, 5371 /* IP1_13_11 [3] */ 5372 FN_A12, FN_FMCLK, FN_SDA3_D, FN_MSIOF1_SCK_D, 5373 0, 0, 0, 0, 5374 /* IP1_10_8 [3] */ 5375 FN_A11, FN_MSIOF1_RXD, FN_SCL3_D, FN_MSIOF1_RXD_D, 5376 0, 0, 0, 0, 5377 /* IP1_7_6 [2] */ 5378 FN_A10, FN_MSIOF1_TXD, 0, FN_MSIOF1_TXD_D, 5379 /* IP1_5_4 [2] */ 5380 FN_A9, FN_MSIOF1_SS2, FN_SDA0, 0, 5381 /* IP1_3_2 [2] */ 5382 FN_A8, FN_MSIOF1_SS1, FN_SCL0, 0, 5383 /* IP1_1_0 [2] */ 5384 FN_A7, FN_MSIOF1_SYNC, 5385 0, 0, } 5386 }, 5387 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, 5388 2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3) { 5389 /* IP2_31_20 [2] */ 5390 0, 0, 0, 0, 5391 /* IP2_29_27 [3] */ 5392 FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, 5393 FN_ATAG0_N, 0, FN_EX_WAIT1, 5394 0, 0, 5395 /* IP2_26_25 [2] */ 5396 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 0, 5397 /* IP2_24_23 [2] */ 5398 FN_EX_CS1_N, FN_MSIOF2_SCK, 0, 0, 5399 /* IP2_22_21 [2] */ 5400 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_SDA1, 0, 5401 /* IP2_20_19 [2] */ 5402 FN_CS0_N, FN_ATAG0_N_B, FN_SCL1, 0, 5403 /* IP2_18_16 [3] */ 5404 FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD, 5405 0, 0, 5406 /* IP2_15_13 [3] */ 5407 FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD, 5408 0, 0, 0, 5409 /* IP2_12_0 [3] */ 5410 FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD, 5411 0, 0, 0, 5412 /* IP2_9_7 [3] */ 5413 FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD, 5414 0, 0, 0, 5415 /* IP2_6_5 [2] */ 5416 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 0, 5417 /* IP2_4_3 [2] */ 5418 FN_A20, FN_SPCLK, 0, 0, 5419 /* IP2_2_0 [3] */ 5420 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0, 5421 FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, } 5422 }, 5423 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, 5424 1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3) { 5425 /* IP3_31 [1] */ 5426 0, 0, 5427 /* IP3_30_28 [3] */ 5428 FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, 5429 FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C, 5430 0, 0, 0, 5431 /* IP3_27_25 [3] */ 5432 FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, 5433 FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C, 5434 0, 0, 0, 5435 /* IP3_24_22 [3] */ 5436 FN_SPEEDIN, 0, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B, 5437 FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D, 5438 /* IP3_21_20 [2] */ 5439 FN_DACK0, FN_DRACK0, FN_REMOCON, 0, 5440 /* IP3_19_18 [2] */ 5441 FN_DREQ0, FN_PWM3, FN_TPU_TO3, 0, 5442 /* IP3_17_16 [2] */ 5443 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 0, 5444 /* IP3_15_14 [2] */ 5445 FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B, 5446 /* IP3_13_12 [2] */ 5447 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 0, 5448 /* IP3_11_9 [3] */ 5449 FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D, 5450 0, 0, 0, 5451 /* IP3_8_6 [3] */ 5452 FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B, 5453 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 0, 5454 /* IP3_5_3 [3] */ 5455 FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B, 5456 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0, 5457 /* IP3_2_0 [3] */ 5458 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2, 5459 0, 0, 0, } 5460 }, 5461 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, 5462 1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, 3, 3, 2) { 5463 /* IP4_31 [1] */ 5464 0, 0, 5465 /* IP4_30_28 [3] */ 5466 FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0, 5467 FN_MSIOF2_SYNC_D, FN_VI1_R2_B, 5468 0, 0, 5469 /* IP4_27_26 [2] */ 5470 FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 0, 0, 5471 /* IP4_25_24 [2] */ 5472 FN_SSI_WS4, FN_GLO_RFON_D, 0, 0, 5473 /* IP4_23_22 [2] */ 5474 FN_SSI_SCK4, FN_GLO_SS_D, 0, 0, 5475 /* IP4_21 [1] */ 5476 FN_SSI_SDATA3, 0, 5477 /* IP4_20 [1] */ 5478 FN_SSI_WS34, 0, 5479 /* IP4_19 [1] */ 5480 FN_SSI_SCK34, 0, 5481 /* IP4_18_16 [3] */ 5482 FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E, 5483 0, 0, 0, 0, 5484 /* IP4_15_13 [3] */ 5485 FN_SSI_WS2, FN_SDA2, FN_GPS_SIGN_B, FN_RX2_E, 5486 FN_GLO_Q1_D, FN_HCTS1_N_E, 5487 0, 0, 5488 /* IP4_12_10 [3] */ 5489 FN_SSI_SCK2, FN_SCL2, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E, 5490 0, 0, 0, 5491 /* IP4_9_8 [2] */ 5492 FN_SSI_SDATA1, FN_SDA1_B, FN_SDA8_B, FN_MSIOF2_RXD_C, 5493 /* IP4_7_5 [3] */ 5494 FN_SSI_WS1, FN_SCL1_B, FN_SCL8_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D, 5495 0, 0, 0, 5496 /* IP4_4_2 [3] */ 5497 FN_SSI_SCK1, FN_SDA0_B, FN_SDA7_B, 5498 FN_MSIOF2_SYNC_C, FN_GLO_I0_D, 5499 0, 0, 0, 5500 /* IP4_1_0 [2] */ 5501 FN_SSI_SDATA0, FN_SCL0_B, FN_SCL7_B, FN_MSIOF2_SCK_C, } 5502 }, 5503 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, 5504 3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3) { 5505 /* IP5_31_29 [3] */ 5506 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D, 5507 0, 0, 0, 0, 0, 5508 /* IP5_28_26 [3] */ 5509 FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D, 5510 0, 0, 0, 0, 5511 /* IP5_25_24 [2] */ 5512 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 0, 5513 /* IP5_23_22 [2] */ 5514 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 0, 5515 /* IP5_21_20 [2] */ 5516 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 0, 5517 /* IP5_19_17 [3] */ 5518 FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON, 5519 0, 0, 0, 0, 5520 /* IP5_16_15 [2] */ 5521 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 0, 5522 /* IP5_14_12 [3] */ 5523 FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B, 5524 0, 0, 0, 0, 5525 /* IP5_11_9 [3] */ 5526 FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B, 5527 0, 0, 0, 0, 5528 /* IP5_8_6 [3] */ 5529 FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1, 5530 FN_MSIOF2_RXD_D, FN_VI1_R5_B, 5531 0, 0, 5532 /* IP5_5_3 [3] */ 5533 FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0, 5534 FN_MSIOF2_SS1_D, FN_VI1_R4_B, 5535 0, 0, 5536 /* IP5_2_0 [3] */ 5537 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1, 5538 FN_MSIOF2_TXD_D, FN_VI1_R3_B, 5539 0, 0, } 5540 }, 5541 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, 5542 2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3) { 5543 /* IP6_31_30 [2] */ 5544 0, 0, 0, 0, 5545 /* IP6_29_27 [3] */ 5546 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, 5547 FN_GPS_SIGN_C, FN_GPS_SIGN_D, 5548 0, 0, 0, 5549 /* IP6_26_24 [3] */ 5550 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, 5551 FN_GPS_CLK_C, FN_GPS_CLK_D, 5552 0, 0, 0, 5553 /* IP6_23_21 [3] */ 5554 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, 5555 FN_SDA1_E, FN_MSIOF2_SYNC_E, 5556 0, 0, 0, 5557 /* IP6_20_19 [2] */ 5558 FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E, 5559 /* IP6_18_16 [3] */ 5560 FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N, 5561 0, 0, 0, 5562 /* IP6_15_14 [2] */ 5563 FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N, 5564 /* IP6_13_12 [2] */ 5565 FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0, 5566 /* IP6_11_10 [2] */ 5567 FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0, 5568 /* IP6_9_8 [2] */ 5569 FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0, 5570 /* IP6_7_6 [2] */ 5571 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD, 5572 /* IP6_5_3 [3] */ 5573 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2, 5574 FN_SCIFA2_RXD, FN_FMIN_E, 5575 0, 0, 5576 /* IP6_2_0 [3] */ 5577 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B, 5578 FN_SCIF_CLK, 0, FN_BPFCLK_E, 5579 0, 0, } 5580 }, 5581 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, 5582 2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3) { 5583 /* IP7_31_30 [2] */ 5584 0, 0, 0, 0, 5585 /* IP7_29_27 [3] */ 5586 FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B, 5587 FN_SCIFA1_SCK, FN_SSI_SCK78_B, 5588 0, 0, 5589 /* IP7_26_24 [3] */ 5590 FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B, 5591 FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B, 5592 0, 0, 5593 /* IP7_23_21 [3] */ 5594 FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B, 5595 FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B, 5596 0, 0, 5597 /* IP7_20_19 [2] */ 5598 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 0, 5599 /* IP7_18_17 [2] */ 5600 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 0, 5601 /* IP7_16_15 [2] */ 5602 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 0, 5603 /* IP7_14_13 [2] */ 5604 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 0, 5605 /* IP7_12_11 [2] */ 5606 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 0, 5607 /* IP7_10_9 [2] */ 5608 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 0, 5609 /* IP7_8_6 [3] */ 5610 FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B, 5611 FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B, 5612 0, 0, 5613 /* IP7_5_3 [3] */ 5614 FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B, 5615 FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B, 5616 0, 0, 5617 /* IP7_2_0 [3] */ 5618 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C, 5619 FN_SCIF_CLK_B, FN_GPS_MAG_D, 5620 0, 0, } 5621 }, 5622 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, 5623 1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3) { 5624 /* IP8_31 [1] */ 5625 0, 0, 5626 /* IP8_30_28 [3] */ 5627 FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX, 5628 0, 0, 0, 5629 /* IP8_27_26 [2] */ 5630 FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX, 5631 /* IP8_25_24 [2] */ 5632 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 0, 5633 /* IP8_23_21 [3] */ 5634 FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B, 5635 FN_SCIFA2_SCK, FN_SSI_SDATA9_B, 5636 0, 0, 5637 /* IP8_20_18 [3] */ 5638 FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B, 5639 FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B, 5640 0, 0, 5641 /* IP8_17_15 [3] */ 5642 FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B, 5643 FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B, 5644 0, 0, 5645 /* IP8_14_12 [3] */ 5646 FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, 5647 FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B, 5648 0, 0, 0, 5649 /* IP8_11_9 [3] */ 5650 FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B, 5651 FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B, 5652 0, 0, 0, 5653 /* IP8_8_6 [3] */ 5654 FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B, 5655 FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B, 5656 0, 0, 5657 /* IP8_5_3 [3] */ 5658 FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B, 5659 FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B, 5660 0, 0, 5661 /* IP8_2_0 [3] */ 5662 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B, 5663 0, 0, 0, } 5664 }, 5665 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, 5666 3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, 1, 1, 3, 3) { 5667 /* IP9_31_29 [3] */ 5668 FN_VI0_G0, FN_SCL8, FN_STP_IVCXO27_0_C, FN_SCL4, 5669 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0, 5670 /* IP9_28_27 [2] */ 5671 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 0, 5672 /* IP9_26_25 [2] */ 5673 FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D, 5674 /* IP9_24_23 [2] */ 5675 FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D, 5676 /* IP9_22_21 [2] */ 5677 FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D, 5678 /* IP9_20_19 [2] */ 5679 FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D, 5680 /* IP9_18_17 [2] */ 5681 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 0, 5682 /* IP9_16 [1] */ 5683 FN_DU1_DISP, FN_QPOLA, 5684 /* IP9_15_13 [3] */ 5685 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE, 5686 FN_CAN0_RX, FN_RX3_B, FN_SDA2_B, 5687 0, 0, 0, 5688 /* IP9_12 [1] */ 5689 FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE, 5690 /* IP9_11 [1] */ 5691 FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS, 5692 /* IP9_10_8 [3] */ 5693 FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX, 5694 FN_TX3_B, FN_SCL2_B, FN_PWM4, 5695 0, 0, 5696 /* IP9_7 [1] */ 5697 FN_DU1_DOTCLKOUT0, FN_QCLK, 5698 /* IP9_6 [1] */ 5699 FN_DU1_DOTCLKIN, FN_QSTVA_QVS, 5700 /* IP9_5_3 [3] */ 5701 FN_DU1_DB7, FN_LCDOUT23, FN_SDA3_C, 5702 FN_SCIF3_SCK, FN_SCIFA3_SCK, 5703 0, 0, 0, 5704 /* IP9_2_0 [3] */ 5705 FN_DU1_DB6, FN_LCDOUT22, FN_SCL3_C, FN_RX3, FN_SCIFA3_RXD, 5706 0, 0, 0, } 5707 }, 5708 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, 5709 3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3) { 5710 /* IP10_31_29 [3] */ 5711 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_SCL1_D, 5712 0, 0, 0, 5713 /* IP10_28_27 [2] */ 5714 FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C, 5715 /* IP10_26_25 [2] */ 5716 FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C, 5717 /* IP10_24_22 [3] */ 5718 FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, FN_TS_SCK0_C, FN_ATAG1_N, 5719 0, 0, 0, 5720 /* IP10_21_29 [3] */ 5721 FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B, 5722 FN_TS_SDATA0_C, FN_ATACS11_N, 5723 0, 0, 0, 5724 /* IP10_18_17 [2] */ 5725 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 0, 5726 /* IP10_16_15 [2] */ 5727 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 0, 5728 /* IP10_14_12 [3] */ 5729 FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D, 5730 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 0, 5731 /* IP10_11_9 [3] */ 5732 FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C, 5733 FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D, 5734 0, 0, 5735 /* IP10_8_6 [3] */ 5736 FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_SDA3_B, 5737 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 0, 5738 /* IP10_5_3 [3] */ 5739 FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_SCL3_B, 5740 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0, 5741 /* IP10_2_0 [3] */ 5742 FN_VI0_G1, FN_SDA8, FN_STP_ISCLK_0_C, FN_SDA4, 5743 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, } 5744 }, 5745 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, 5746 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 5747 3, 3, 3, 3, 3) { 5748 /* IP11_31_30 [2] */ 5749 FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, 0, 5750 /* IP11_29_28 [2] */ 5751 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, 0, 5752 /* IP11_27 [1] */ 5753 FN_VI1_DATA7, FN_AVB_MDC, 5754 /* IP11_26 [1] */ 5755 FN_VI1_DATA6, FN_AVB_MAGIC, 5756 /* IP11_25 [1] */ 5757 FN_VI1_DATA5, FN_AVB_RX_DV, 5758 /* IP11_24 [1] */ 5759 FN_VI1_DATA4, FN_AVB_MDIO, 5760 /* IP11_23 [1] */ 5761 FN_VI1_DATA3, FN_AVB_RX_ER, 5762 /* IP11_22 [1] */ 5763 FN_VI1_DATA2, FN_AVB_RXD7, 5764 /* IP11_21 [1] */ 5765 FN_VI1_DATA1, FN_AVB_RXD6, 5766 /* IP11_20 [1] */ 5767 FN_VI1_DATA0, FN_AVB_RXD5, 5768 /* IP11_19 [1] */ 5769 FN_VI1_CLK, FN_AVB_RXD4, 5770 /* IP11_18_17 [2] */ 5771 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0, 5772 /* IP11_16_15 [2] */ 5773 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0, 5774 /* IP11_14_12 [3] */ 5775 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, 5776 FN_RX4_B, FN_SCIFA4_RXD_B, 5777 0, 0, 0, 5778 /* IP11_11_9 [3] */ 5779 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, 5780 FN_TX4_B, FN_SCIFA4_TXD_B, 5781 0, 0, 0, 5782 /* IP11_8_6 [3] */ 5783 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E, 5784 FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0, 5785 /* IP11_5_3 [3] */ 5786 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B, 5787 0, 0, 0, 5788 /* IP11_2_0 [3] */ 5789 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D, 5790 0, 0, 0, } 5791 }, 5792 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, 5793 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) { 5794 /* IP12_31_30 [2] */ 5795 0, 0, 0, 0, 5796 /* IP12_29_27 [3] */ 5797 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D, 5798 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C, 5799 0, 0, 0, 5800 /* IP12_26_24 [3] */ 5801 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D, 5802 FN_ADIDATA_B, FN_MSIOF0_SYNC_C, 5803 0, 0, 0, 5804 /* IP12_23_22 [2] */ 5805 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0, 5806 /* IP12_21_20 [2] */ 5807 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0, 5808 /* IP12_19_18 [2] */ 5809 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0, 5810 /* IP12_17_16 [2] */ 5811 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B, 5812 /* IP12_15_13 [3] */ 5813 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B, 5814 FN_CAN1_TX_C, FN_MSIOF1_TXD_E, 5815 0, 0, 0, 5816 /* IP12_12_10 [3] */ 5817 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B, 5818 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E, 5819 0, 0, 0, 5820 /* IP12_9_7 [3] */ 5821 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, 5822 FN_SDA2_D, FN_MSIOF1_SCK_E, 5823 0, 0, 0, 5824 /* IP12_6_4 [3] */ 5825 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C, 5826 FN_SCL2_D, FN_MSIOF1_RXD_E, 5827 0, 0, 0, 5828 /* IP12_3_2 [2] */ 5829 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7, 5830 /* IP12_1_0 [2] */ 5831 FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, } 5832 }, 5833 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, 5834 1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1, 5835 3, 2, 2, 3) { 5836 /* IP13_31 [1] */ 5837 0, 0, 5838 /* IP13_30_28 [3] */ 5839 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C, 5840 0, 0, 0, 0, 5841 /* IP13_27 [1] */ 5842 FN_SD1_DATA3, FN_IERX_B, 5843 /* IP13_26 [1] */ 5844 FN_SD1_DATA2, FN_IECLK_B, 5845 /* IP13_25 [1] */ 5846 FN_SD1_DATA1, FN_IETX_B, 5847 /* IP13_24_23 [2] */ 5848 FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0, 5849 /* IP13_22 [1] */ 5850 FN_SD1_CMD, FN_REMOCON_B, 5851 /* IP13_21_19 [3] */ 5852 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F, 5853 FN_SCIFA5_RXD_B, FN_RX3_C, 5854 0, 0, 5855 /* IP13_18_16 [3] */ 5856 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F, 5857 FN_SCIFA5_TXD_B, FN_TX3_C, 5858 0, 0, 5859 /* IP13_15 [1] */ 5860 FN_SD0_DATA3, FN_SSL_B, 5861 /* IP13_14 [1] */ 5862 FN_SD0_DATA2, FN_IO3_B, 5863 /* IP13_13 [1] */ 5864 FN_SD0_DATA1, FN_IO2_B, 5865 /* IP13_12 [1] */ 5866 FN_SD0_DATA0, FN_MISO_IO1_B, 5867 /* IP13_11 [1] */ 5868 FN_SD0_CMD, FN_MOSI_IO0_B, 5869 /* IP13_10 [1] */ 5870 FN_SD0_CLK, FN_SPCLK_B, 5871 /* IP13_9_7 [3] */ 5872 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B, 5873 FN_ADICHS2_B, FN_MSIOF0_TXD_C, 5874 0, 0, 0, 5875 /* IP13_6_5 [2] */ 5876 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C, 5877 /* IP13_4_3 [2] */ 5878 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C, 5879 /* IP13_2_0 [3] */ 5880 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C, 5881 FN_ADICLK_B, FN_MSIOF0_SS1_C, 5882 0, 0, 0, } 5883 }, 5884 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32, 5885 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) { 5886 /* IP14_31_29 [3] */ 5887 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E, 5888 FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B, 0, 5889 /* IP14_28_26 [3] */ 5890 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E, 5891 FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B, 0, 5892 /* IP14_25_23 [3] */ 5893 FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B, 5894 0, 0, 0, 5895 /* IP14_22_20 [3] */ 5896 FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B, 5897 0, 0, 0, 5898 /* IP14_19_17 [3] */ 5899 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0, 5900 FN_VI1_CLKENB_C, FN_VI1_G1_B, 5901 0, 0, 5902 /* IP14_16_14 [3] */ 5903 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0, 5904 FN_VI1_CLK_C, FN_VI1_G0_B, 5905 0, 0, 5906 /* IP14_13_11 [3] */ 5907 FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C, 5908 0, 0, 0, 5909 /* IP14_10_8 [3] */ 5910 FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C, 5911 0, 0, 0, 5912 /* IP14_7 [1] */ 5913 FN_SD2_DATA3, FN_MMC_D3, 5914 /* IP14_6 [1] */ 5915 FN_SD2_DATA2, FN_MMC_D2, 5916 /* IP14_5 [1] */ 5917 FN_SD2_DATA1, FN_MMC_D1, 5918 /* IP14_4 [1] */ 5919 FN_SD2_DATA0, FN_MMC_D0, 5920 /* IP14_3 [1] */ 5921 FN_SD2_CMD, FN_MMC_CMD, 5922 /* IP14_2 [1] */ 5923 FN_SD2_CLK, FN_MMC_CLK, 5924 /* IP14_1_0 [2] */ 5925 FN_SD1_WP, FN_PWM1_B, FN_SDA1_C, 0, } 5926 }, 5927 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32, 5928 2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) { 5929 /* IP15_31_30 [2] */ 5930 0, 0, 0, 0, 5931 /* IP15_29_27 [3] */ 5932 FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C, 5933 FN_CAN0_TX_B, FN_VI1_DATA5_C, 5934 0, 0, 5935 /* IP15_26_24 [3] */ 5936 FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C, 5937 FN_CAN0_RX_B, FN_VI1_DATA4_C, 5938 0, 0, 5939 /* IP15_23_21 [3] */ 5940 FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK, 5941 FN_TCLK2, FN_VI1_DATA3_C, 0, 5942 /* IP15_20_18 [3] */ 5943 FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C, 5944 0, 0, 0, 5945 /* IP15_17_15 [3] */ 5946 FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C, 5947 FN_TCLK1, FN_VI1_DATA1_C, 5948 0, 0, 5949 /* IP15_14_12 [3] */ 5950 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6, 5951 FN_VI1_G7_B, FN_SCIFA3_SCK_C, 5952 0, 0, 5953 /* IP15_11_9 [3] */ 5954 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5, 5955 FN_VI1_G6_B, FN_SCIFA3_RXD_C, 5956 0, 0, 5957 /* IP15_8_6 [3] */ 5958 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B, 5959 FN_PWM5_B, FN_SCIFA3_TXD_C, 5960 0, 0, 0, 5961 /* IP15_5_4 [2] */ 5962 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0, 5963 /* IP15_3_2 [2] */ 5964 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0, 5965 /* IP15_1_0 [2] */ 5966 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, } 5967 }, 5968 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32, 5969 4, 4, 4, 4, 4, 2, 2, 2, 3, 3) { 5970 /* IP16_31_28 [4] */ 5971 0, 0, 0, 0, 0, 0, 0, 0, 5972 0, 0, 0, 0, 0, 0, 0, 0, 5973 /* IP16_27_24 [4] */ 5974 0, 0, 0, 0, 0, 0, 0, 0, 5975 0, 0, 0, 0, 0, 0, 0, 0, 5976 /* IP16_23_20 [4] */ 5977 0, 0, 0, 0, 0, 0, 0, 0, 5978 0, 0, 0, 0, 0, 0, 0, 0, 5979 /* IP16_19_16 [4] */ 5980 0, 0, 0, 0, 0, 0, 0, 0, 5981 0, 0, 0, 0, 0, 0, 0, 0, 5982 /* IP16_15_12 [4] */ 5983 0, 0, 0, 0, 0, 0, 0, 0, 5984 0, 0, 0, 0, 0, 0, 0, 0, 5985 /* IP16_11_10 [2] */ 5986 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B, 5987 /* IP16_9_8 [2] */ 5988 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B, 5989 /* IP16_7_6 [2] */ 5990 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C, 5991 /* IP16_5_3 [3] */ 5992 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, 5993 FN_GLO_SS_C, FN_VI1_DATA7_C, 5994 0, 0, 0, 5995 /* IP16_2_0 [3] */ 5996 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, 5997 FN_GLO_SDATA_C, FN_VI1_DATA6_C, 5998 0, 0, 0, } 5999 }, 6000 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, 6001 1, 2, 2, 2, 3, 2, 1, 1, 1, 1, 6002 3, 2, 2, 2, 1, 2, 2, 2) { 6003 /* RESEVED [1] */ 6004 0, 0, 6005 /* SEL_SCIF1 [2] */ 6006 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, 6007 /* SEL_SCIFB [2] */ 6008 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3, 6009 /* SEL_SCIFB2 [2] */ 6010 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, 6011 FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3, 6012 /* SEL_SCIFB1 [3] */ 6013 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, 6014 FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, 6015 0, 0, 0, 0, 6016 /* SEL_SCIFA1 [2] */ 6017 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0, 6018 /* SEL_SSI9 [1] */ 6019 FN_SEL_SSI9_0, FN_SEL_SSI9_1, 6020 /* SEL_SCFA [1] */ 6021 FN_SEL_SCFA_0, FN_SEL_SCFA_1, 6022 /* SEL_QSP [1] */ 6023 FN_SEL_QSP_0, FN_SEL_QSP_1, 6024 /* SEL_SSI7 [1] */ 6025 FN_SEL_SSI7_0, FN_SEL_SSI7_1, 6026 /* SEL_HSCIF1 [3] */ 6027 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, 6028 FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4, 6029 0, 0, 0, 6030 /* RESEVED [2] */ 6031 0, 0, 0, 0, 6032 /* SEL_VI1 [2] */ 6033 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0, 6034 /* RESEVED [2] */ 6035 0, 0, 0, 0, 6036 /* SEL_TMU [1] */ 6037 FN_SEL_TMU1_0, FN_SEL_TMU1_1, 6038 /* SEL_LBS [2] */ 6039 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3, 6040 /* SEL_TSIF0 [2] */ 6041 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, 6042 /* SEL_SOF0 [2] */ 6043 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, } 6044 }, 6045 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, 6046 3, 1, 1, 3, 2, 1, 1, 2, 2, 6047 1, 3, 2, 1, 2, 2, 2, 1, 1, 1) { 6048 /* SEL_SCIF0 [3] */ 6049 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, 6050 FN_SEL_SCIF0_3, FN_SEL_SCIF0_4, 6051 0, 0, 0, 6052 /* RESEVED [1] */ 6053 0, 0, 6054 /* SEL_SCIF [1] */ 6055 FN_SEL_SCIF_0, FN_SEL_SCIF_1, 6056 /* SEL_CAN0 [3] */ 6057 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, 6058 FN_SEL_CAN0_4, FN_SEL_CAN0_5, 6059 0, 0, 6060 /* SEL_CAN1 [2] */ 6061 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, 6062 /* RESEVED [1] */ 6063 0, 0, 6064 /* SEL_SCIFA2 [1] */ 6065 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, 6066 /* SEL_SCIF4 [2] */ 6067 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0, 6068 /* RESEVED [2] */ 6069 0, 0, 0, 0, 6070 /* SEL_ADG [1] */ 6071 FN_SEL_ADG_0, FN_SEL_ADG_1, 6072 /* SEL_FM [3] */ 6073 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, 6074 FN_SEL_FM_3, FN_SEL_FM_4, 6075 0, 0, 0, 6076 /* SEL_SCIFA5 [2] */ 6077 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0, 6078 /* RESEVED [1] */ 6079 0, 0, 6080 /* SEL_GPS [2] */ 6081 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, 6082 /* SEL_SCIFA4 [2] */ 6083 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0, 6084 /* SEL_SCIFA3 [2] */ 6085 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0, 6086 /* SEL_SIM [1] */ 6087 FN_SEL_SIM_0, FN_SEL_SIM_1, 6088 /* RESEVED [1] */ 6089 0, 0, 6090 /* SEL_SSI8 [1] */ 6091 FN_SEL_SSI8_0, FN_SEL_SSI8_1, } 6092 }, 6093 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, 6094 2, 2, 2, 2, 2, 2, 2, 2, 6095 1, 1, 2, 2, 3, 2, 2, 2, 1) { 6096 /* SEL_HSCIF2 [2] */ 6097 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, 6098 FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3, 6099 /* SEL_CANCLK [2] */ 6100 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, 6101 FN_SEL_CANCLK_2, FN_SEL_CANCLK_3, 6102 /* SEL_IIC8 [2] */ 6103 FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, 0, 6104 /* SEL_IIC7 [2] */ 6105 FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, 0, 6106 /* SEL_IIC4 [2] */ 6107 FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, 0, 6108 /* SEL_IIC3 [2] */ 6109 FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3, 6110 /* SEL_SCIF3 [2] */ 6111 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, 6112 /* SEL_IEB [2] */ 6113 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, 6114 /* SEL_MMC [1] */ 6115 FN_SEL_MMC_0, FN_SEL_MMC_1, 6116 /* SEL_SCIF5 [1] */ 6117 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, 6118 /* RESEVED [2] */ 6119 0, 0, 0, 0, 6120 /* SEL_IIC2 [2] */ 6121 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, 6122 /* SEL_IIC1 [3] */ 6123 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3, 6124 FN_SEL_IIC1_4, 6125 0, 0, 0, 6126 /* SEL_IIC0 [2] */ 6127 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0, 6128 /* RESEVED [2] */ 6129 0, 0, 0, 0, 6130 /* RESEVED [2] */ 6131 0, 0, 0, 0, 6132 /* RESEVED [1] */ 6133 0, 0, } 6134 }, 6135 { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32, 6136 3, 2, 2, 1, 1, 1, 1, 3, 2, 6137 2, 3, 1, 1, 1, 2, 2, 2, 2) { 6138 /* SEL_SOF1 [3] */ 6139 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3, 6140 FN_SEL_SOF1_4, 6141 0, 0, 0, 6142 /* SEL_HSCIF0 [2] */ 6143 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0, 6144 /* SEL_DIS [2] */ 6145 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0, 6146 /* RESEVED [1] */ 6147 0, 0, 6148 /* SEL_RAD [1] */ 6149 FN_SEL_RAD_0, FN_SEL_RAD_1, 6150 /* SEL_RCN [1] */ 6151 FN_SEL_RCN_0, FN_SEL_RCN_1, 6152 /* SEL_RSP [1] */ 6153 FN_SEL_RSP_0, FN_SEL_RSP_1, 6154 /* SEL_SCIF2 [3] */ 6155 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 6156 FN_SEL_SCIF2_3, FN_SEL_SCIF2_4, 6157 0, 0, 0, 6158 /* RESEVED [2] */ 6159 0, 0, 0, 0, 6160 /* RESEVED [2] */ 6161 0, 0, 0, 0, 6162 /* SEL_SOF2 [3] */ 6163 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, 6164 FN_SEL_SOF2_3, FN_SEL_SOF2_4, 6165 0, 0, 0, 6166 /* RESEVED [1] */ 6167 0, 0, 6168 /* SEL_SSI1 [1] */ 6169 FN_SEL_SSI1_0, FN_SEL_SSI1_1, 6170 /* SEL_SSI0 [1] */ 6171 FN_SEL_SSI0_0, FN_SEL_SSI0_1, 6172 /* SEL_SSP [2] */ 6173 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0, 6174 /* RESEVED [2] */ 6175 0, 0, 0, 0, 6176 /* RESEVED [2] */ 6177 0, 0, 0, 0, 6178 /* RESEVED [2] */ 6179 0, 0, 0, 0, } 6180 }, 6181 { }, 6182 }; 6183 6184 const struct sh_pfc_soc_info r8a7791_pinmux_info = { 6185 .name = "r8a77910_pfc", 6186 .unlock_reg = 0xe6060000, /* PMMR */ 6187 6188 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6189 6190 .pins = pinmux_pins, 6191 .nr_pins = ARRAY_SIZE(pinmux_pins), 6192 .groups = pinmux_groups, 6193 .nr_groups = ARRAY_SIZE(pinmux_groups), 6194 .functions = pinmux_functions, 6195 .nr_functions = ARRAY_SIZE(pinmux_functions), 6196 6197 .cfg_regs = pinmux_config_regs, 6198 6199 .gpio_data = pinmux_data, 6200 .gpio_data_size = ARRAY_SIZE(pinmux_data), 6201 }; 6202