1/* 2 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's EXYNOS5440 SoC. 3 * 4 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 */ 12 13#include <linux/module.h> 14#include <linux/platform_device.h> 15#include <linux/io.h> 16#include <linux/slab.h> 17#include <linux/err.h> 18#include <linux/gpio.h> 19#include <linux/device.h> 20#include <linux/pinctrl/pinctrl.h> 21#include <linux/pinctrl/pinmux.h> 22#include <linux/pinctrl/pinconf.h> 23#include <linux/interrupt.h> 24#include <linux/irqdomain.h> 25#include <linux/of_irq.h> 26#include "../core.h" 27 28/* EXYNOS5440 GPIO and Pinctrl register offsets */ 29#define GPIO_MUX 0x00 30#define GPIO_IE 0x04 31#define GPIO_INT 0x08 32#define GPIO_TYPE 0x0C 33#define GPIO_VAL 0x10 34#define GPIO_OE 0x14 35#define GPIO_IN 0x18 36#define GPIO_PE 0x1C 37#define GPIO_PS 0x20 38#define GPIO_SR 0x24 39#define GPIO_DS0 0x28 40#define GPIO_DS1 0x2C 41 42#define EXYNOS5440_MAX_PINS 23 43#define EXYNOS5440_MAX_GPIO_INT 8 44#define PIN_NAME_LENGTH 10 45 46#define GROUP_SUFFIX "-grp" 47#define GSUFFIX_LEN sizeof(GROUP_SUFFIX) 48#define FUNCTION_SUFFIX "-mux" 49#define FSUFFIX_LEN sizeof(FUNCTION_SUFFIX) 50 51/* 52 * pin configuration type and its value are packed together into a 16-bits. 53 * The upper 8-bits represent the configuration type and the lower 8-bits 54 * hold the value of the configuration type. 55 */ 56#define PINCFG_TYPE_MASK 0xFF 57#define PINCFG_VALUE_SHIFT 8 58#define PINCFG_VALUE_MASK (0xFF << PINCFG_VALUE_SHIFT) 59#define PINCFG_PACK(type, value) (((value) << PINCFG_VALUE_SHIFT) | type) 60#define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK) 61#define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \ 62 PINCFG_VALUE_SHIFT) 63 64/** 65 * enum pincfg_type - possible pin configuration types supported. 66 * @PINCFG_TYPE_PUD: Pull up/down configuration. 67 * @PINCFG_TYPE_DRV: Drive strength configuration. 68 * @PINCFG_TYPE_SKEW_RATE: Skew rate configuration. 69 * @PINCFG_TYPE_INPUT_TYPE: Pin input type configuration. 70 */ 71enum pincfg_type { 72 PINCFG_TYPE_PUD, 73 PINCFG_TYPE_DRV, 74 PINCFG_TYPE_SKEW_RATE, 75 PINCFG_TYPE_INPUT_TYPE 76}; 77 78/** 79 * struct exynos5440_pin_group: represent group of pins for pincfg setting. 80 * @name: name of the pin group, used to lookup the group. 81 * @pins: the pins included in this group. 82 * @num_pins: number of pins included in this group. 83 */ 84struct exynos5440_pin_group { 85 const char *name; 86 const unsigned int *pins; 87 u8 num_pins; 88}; 89 90/** 91 * struct exynos5440_pmx_func: represent a pin function. 92 * @name: name of the pin function, used to lookup the function. 93 * @groups: one or more names of pin groups that provide this function. 94 * @num_groups: number of groups included in @groups. 95 * @function: the function number to be programmed when selected. 96 */ 97struct exynos5440_pmx_func { 98 const char *name; 99 const char **groups; 100 u8 num_groups; 101 unsigned long function; 102}; 103 104/** 105 * struct exynos5440_pinctrl_priv_data: driver's private runtime data. 106 * @reg_base: ioremapped based address of the register space. 107 * @gc: gpio chip registered with gpiolib. 108 * @pin_groups: list of pin groups parsed from device tree. 109 * @nr_groups: number of pin groups available. 110 * @pmx_functions: list of pin functions parsed from device tree. 111 * @nr_functions: number of pin functions available. 112 * @range: gpio range to register with pinctrl 113 */ 114struct exynos5440_pinctrl_priv_data { 115 void __iomem *reg_base; 116 struct gpio_chip *gc; 117 struct irq_domain *irq_domain; 118 119 const struct exynos5440_pin_group *pin_groups; 120 unsigned int nr_groups; 121 const struct exynos5440_pmx_func *pmx_functions; 122 unsigned int nr_functions; 123 struct pinctrl_gpio_range range; 124}; 125 126/** 127 * struct exynos5440_gpio_intr_data: private data for gpio interrupts. 128 * @priv: driver's private runtime data. 129 * @gpio_int: gpio interrupt number. 130 */ 131struct exynos5440_gpio_intr_data { 132 struct exynos5440_pinctrl_priv_data *priv; 133 unsigned int gpio_int; 134}; 135 136/* list of all possible config options supported */ 137static struct pin_config { 138 char *prop_cfg; 139 unsigned int cfg_type; 140} pcfgs[] = { 141 { "samsung,exynos5440-pin-pud", PINCFG_TYPE_PUD }, 142 { "samsung,exynos5440-pin-drv", PINCFG_TYPE_DRV }, 143 { "samsung,exynos5440-pin-skew-rate", PINCFG_TYPE_SKEW_RATE }, 144 { "samsung,exynos5440-pin-input-type", PINCFG_TYPE_INPUT_TYPE }, 145}; 146 147/* check if the selector is a valid pin group selector */ 148static int exynos5440_get_group_count(struct pinctrl_dev *pctldev) 149{ 150 struct exynos5440_pinctrl_priv_data *priv; 151 152 priv = pinctrl_dev_get_drvdata(pctldev); 153 return priv->nr_groups; 154} 155 156/* return the name of the group selected by the group selector */ 157static const char *exynos5440_get_group_name(struct pinctrl_dev *pctldev, 158 unsigned selector) 159{ 160 struct exynos5440_pinctrl_priv_data *priv; 161 162 priv = pinctrl_dev_get_drvdata(pctldev); 163 return priv->pin_groups[selector].name; 164} 165 166/* return the pin numbers associated with the specified group */ 167static int exynos5440_get_group_pins(struct pinctrl_dev *pctldev, 168 unsigned selector, const unsigned **pins, unsigned *num_pins) 169{ 170 struct exynos5440_pinctrl_priv_data *priv; 171 172 priv = pinctrl_dev_get_drvdata(pctldev); 173 *pins = priv->pin_groups[selector].pins; 174 *num_pins = priv->pin_groups[selector].num_pins; 175 return 0; 176} 177 178/* create pinctrl_map entries by parsing device tree nodes */ 179static int exynos5440_dt_node_to_map(struct pinctrl_dev *pctldev, 180 struct device_node *np, struct pinctrl_map **maps, 181 unsigned *nmaps) 182{ 183 struct device *dev = pctldev->dev; 184 struct pinctrl_map *map; 185 unsigned long *cfg = NULL; 186 char *gname, *fname; 187 int cfg_cnt = 0, map_cnt = 0, idx = 0; 188 189 /* count the number of config options specfied in the node */ 190 for (idx = 0; idx < ARRAY_SIZE(pcfgs); idx++) 191 if (of_find_property(np, pcfgs[idx].prop_cfg, NULL)) 192 cfg_cnt++; 193 194 /* 195 * Find out the number of map entries to create. All the config options 196 * can be accomadated into a single config map entry. 197 */ 198 if (cfg_cnt) 199 map_cnt = 1; 200 if (of_find_property(np, "samsung,exynos5440-pin-function", NULL)) 201 map_cnt++; 202 if (!map_cnt) { 203 dev_err(dev, "node %s does not have either config or function " 204 "configurations\n", np->name); 205 return -EINVAL; 206 } 207 208 /* Allocate memory for pin-map entries */ 209 map = kzalloc(sizeof(*map) * map_cnt, GFP_KERNEL); 210 if (!map) { 211 dev_err(dev, "could not alloc memory for pin-maps\n"); 212 return -ENOMEM; 213 } 214 *nmaps = 0; 215 216 /* 217 * Allocate memory for pin group name. The pin group name is derived 218 * from the node name from which these map entries are be created. 219 */ 220 gname = kzalloc(strlen(np->name) + GSUFFIX_LEN, GFP_KERNEL); 221 if (!gname) { 222 dev_err(dev, "failed to alloc memory for group name\n"); 223 goto free_map; 224 } 225 snprintf(gname, strlen(np->name) + 4, "%s%s", np->name, GROUP_SUFFIX); 226 227 /* 228 * don't have config options? then skip over to creating function 229 * map entries. 230 */ 231 if (!cfg_cnt) 232 goto skip_cfgs; 233 234 /* Allocate memory for config entries */ 235 cfg = kzalloc(sizeof(*cfg) * cfg_cnt, GFP_KERNEL); 236 if (!cfg) { 237 dev_err(dev, "failed to alloc memory for configs\n"); 238 goto free_gname; 239 } 240 241 /* Prepare a list of config settings */ 242 for (idx = 0, cfg_cnt = 0; idx < ARRAY_SIZE(pcfgs); idx++) { 243 u32 value; 244 if (!of_property_read_u32(np, pcfgs[idx].prop_cfg, &value)) 245 cfg[cfg_cnt++] = 246 PINCFG_PACK(pcfgs[idx].cfg_type, value); 247 } 248 249 /* create the config map entry */ 250 map[*nmaps].data.configs.group_or_pin = gname; 251 map[*nmaps].data.configs.configs = cfg; 252 map[*nmaps].data.configs.num_configs = cfg_cnt; 253 map[*nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP; 254 *nmaps += 1; 255 256skip_cfgs: 257 /* create the function map entry */ 258 if (of_find_property(np, "samsung,exynos5440-pin-function", NULL)) { 259 fname = kzalloc(strlen(np->name) + FSUFFIX_LEN, GFP_KERNEL); 260 if (!fname) { 261 dev_err(dev, "failed to alloc memory for func name\n"); 262 goto free_cfg; 263 } 264 snprintf(fname, strlen(np->name) + 4, "%s%s", np->name, 265 FUNCTION_SUFFIX); 266 267 map[*nmaps].data.mux.group = gname; 268 map[*nmaps].data.mux.function = fname; 269 map[*nmaps].type = PIN_MAP_TYPE_MUX_GROUP; 270 *nmaps += 1; 271 } 272 273 *maps = map; 274 return 0; 275 276free_cfg: 277 kfree(cfg); 278free_gname: 279 kfree(gname); 280free_map: 281 kfree(map); 282 return -ENOMEM; 283} 284 285/* free the memory allocated to hold the pin-map table */ 286static void exynos5440_dt_free_map(struct pinctrl_dev *pctldev, 287 struct pinctrl_map *map, unsigned num_maps) 288{ 289 int idx; 290 291 for (idx = 0; idx < num_maps; idx++) { 292 if (map[idx].type == PIN_MAP_TYPE_MUX_GROUP) { 293 kfree(map[idx].data.mux.function); 294 if (!idx) 295 kfree(map[idx].data.mux.group); 296 } else if (map->type == PIN_MAP_TYPE_CONFIGS_GROUP) { 297 kfree(map[idx].data.configs.configs); 298 if (!idx) 299 kfree(map[idx].data.configs.group_or_pin); 300 } 301 }; 302 303 kfree(map); 304} 305 306/* list of pinctrl callbacks for the pinctrl core */ 307static const struct pinctrl_ops exynos5440_pctrl_ops = { 308 .get_groups_count = exynos5440_get_group_count, 309 .get_group_name = exynos5440_get_group_name, 310 .get_group_pins = exynos5440_get_group_pins, 311 .dt_node_to_map = exynos5440_dt_node_to_map, 312 .dt_free_map = exynos5440_dt_free_map, 313}; 314 315/* check if the selector is a valid pin function selector */ 316static int exynos5440_get_functions_count(struct pinctrl_dev *pctldev) 317{ 318 struct exynos5440_pinctrl_priv_data *priv; 319 320 priv = pinctrl_dev_get_drvdata(pctldev); 321 return priv->nr_functions; 322} 323 324/* return the name of the pin function specified */ 325static const char *exynos5440_pinmux_get_fname(struct pinctrl_dev *pctldev, 326 unsigned selector) 327{ 328 struct exynos5440_pinctrl_priv_data *priv; 329 330 priv = pinctrl_dev_get_drvdata(pctldev); 331 return priv->pmx_functions[selector].name; 332} 333 334/* return the groups associated for the specified function selector */ 335static int exynos5440_pinmux_get_groups(struct pinctrl_dev *pctldev, 336 unsigned selector, const char * const **groups, 337 unsigned * const num_groups) 338{ 339 struct exynos5440_pinctrl_priv_data *priv; 340 341 priv = pinctrl_dev_get_drvdata(pctldev); 342 *groups = priv->pmx_functions[selector].groups; 343 *num_groups = priv->pmx_functions[selector].num_groups; 344 return 0; 345} 346 347/* enable or disable a pinmux function */ 348static void exynos5440_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector, 349 unsigned group, bool enable) 350{ 351 struct exynos5440_pinctrl_priv_data *priv; 352 void __iomem *base; 353 u32 function; 354 u32 data; 355 356 priv = pinctrl_dev_get_drvdata(pctldev); 357 base = priv->reg_base; 358 function = priv->pmx_functions[selector].function; 359 360 data = readl(base + GPIO_MUX); 361 if (enable) 362 data |= (1 << function); 363 else 364 data &= ~(1 << function); 365 writel(data, base + GPIO_MUX); 366} 367 368/* enable a specified pinmux by writing to registers */ 369static int exynos5440_pinmux_set_mux(struct pinctrl_dev *pctldev, 370 unsigned selector, 371 unsigned group) 372{ 373 exynos5440_pinmux_setup(pctldev, selector, group, true); 374 return 0; 375} 376 377/* 378 * The calls to gpio_direction_output() and gpio_direction_input() 379 * leads to this function call (via the pinctrl_gpio_direction_{input|output}() 380 * function called from the gpiolib interface). 381 */ 382static int exynos5440_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, 383 struct pinctrl_gpio_range *range, unsigned offset, bool input) 384{ 385 return 0; 386} 387 388/* list of pinmux callbacks for the pinmux vertical in pinctrl core */ 389static const struct pinmux_ops exynos5440_pinmux_ops = { 390 .get_functions_count = exynos5440_get_functions_count, 391 .get_function_name = exynos5440_pinmux_get_fname, 392 .get_function_groups = exynos5440_pinmux_get_groups, 393 .set_mux = exynos5440_pinmux_set_mux, 394 .gpio_set_direction = exynos5440_pinmux_gpio_set_direction, 395}; 396 397/* set the pin config settings for a specified pin */ 398static int exynos5440_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 399 unsigned long *configs, 400 unsigned num_configs) 401{ 402 struct exynos5440_pinctrl_priv_data *priv; 403 void __iomem *base; 404 enum pincfg_type cfg_type; 405 u32 cfg_value; 406 u32 data; 407 int i; 408 409 priv = pinctrl_dev_get_drvdata(pctldev); 410 base = priv->reg_base; 411 412 for (i = 0; i < num_configs; i++) { 413 cfg_type = PINCFG_UNPACK_TYPE(configs[i]); 414 cfg_value = PINCFG_UNPACK_VALUE(configs[i]); 415 416 switch (cfg_type) { 417 case PINCFG_TYPE_PUD: 418 /* first set pull enable/disable bit */ 419 data = readl(base + GPIO_PE); 420 data &= ~(1 << pin); 421 if (cfg_value) 422 data |= (1 << pin); 423 writel(data, base + GPIO_PE); 424 425 /* then set pull up/down bit */ 426 data = readl(base + GPIO_PS); 427 data &= ~(1 << pin); 428 if (cfg_value == 2) 429 data |= (1 << pin); 430 writel(data, base + GPIO_PS); 431 break; 432 433 case PINCFG_TYPE_DRV: 434 /* set the first bit of the drive strength */ 435 data = readl(base + GPIO_DS0); 436 data &= ~(1 << pin); 437 data |= ((cfg_value & 1) << pin); 438 writel(data, base + GPIO_DS0); 439 cfg_value >>= 1; 440 441 /* set the second bit of the driver strength */ 442 data = readl(base + GPIO_DS1); 443 data &= ~(1 << pin); 444 data |= ((cfg_value & 1) << pin); 445 writel(data, base + GPIO_DS1); 446 break; 447 case PINCFG_TYPE_SKEW_RATE: 448 data = readl(base + GPIO_SR); 449 data &= ~(1 << pin); 450 data |= ((cfg_value & 1) << pin); 451 writel(data, base + GPIO_SR); 452 break; 453 case PINCFG_TYPE_INPUT_TYPE: 454 data = readl(base + GPIO_TYPE); 455 data &= ~(1 << pin); 456 data |= ((cfg_value & 1) << pin); 457 writel(data, base + GPIO_TYPE); 458 break; 459 default: 460 WARN_ON(1); 461 return -EINVAL; 462 } 463 } /* for each config */ 464 465 return 0; 466} 467 468/* get the pin config settings for a specified pin */ 469static int exynos5440_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 470 unsigned long *config) 471{ 472 struct exynos5440_pinctrl_priv_data *priv; 473 void __iomem *base; 474 enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(*config); 475 u32 data; 476 477 priv = pinctrl_dev_get_drvdata(pctldev); 478 base = priv->reg_base; 479 480 switch (cfg_type) { 481 case PINCFG_TYPE_PUD: 482 data = readl(base + GPIO_PE); 483 data = (data >> pin) & 1; 484 if (!data) 485 *config = 0; 486 else 487 *config = ((readl(base + GPIO_PS) >> pin) & 1) + 1; 488 break; 489 case PINCFG_TYPE_DRV: 490 data = readl(base + GPIO_DS0); 491 data = (data >> pin) & 1; 492 *config = data; 493 data = readl(base + GPIO_DS1); 494 data = (data >> pin) & 1; 495 *config |= (data << 1); 496 break; 497 case PINCFG_TYPE_SKEW_RATE: 498 data = readl(base + GPIO_SR); 499 *config = (data >> pin) & 1; 500 break; 501 case PINCFG_TYPE_INPUT_TYPE: 502 data = readl(base + GPIO_TYPE); 503 *config = (data >> pin) & 1; 504 break; 505 default: 506 WARN_ON(1); 507 return -EINVAL; 508 } 509 510 return 0; 511} 512 513/* set the pin config settings for a specified pin group */ 514static int exynos5440_pinconf_group_set(struct pinctrl_dev *pctldev, 515 unsigned group, unsigned long *configs, 516 unsigned num_configs) 517{ 518 struct exynos5440_pinctrl_priv_data *priv; 519 const unsigned int *pins; 520 unsigned int cnt; 521 522 priv = pinctrl_dev_get_drvdata(pctldev); 523 pins = priv->pin_groups[group].pins; 524 525 for (cnt = 0; cnt < priv->pin_groups[group].num_pins; cnt++) 526 exynos5440_pinconf_set(pctldev, pins[cnt], configs, 527 num_configs); 528 529 return 0; 530} 531 532/* get the pin config settings for a specified pin group */ 533static int exynos5440_pinconf_group_get(struct pinctrl_dev *pctldev, 534 unsigned int group, unsigned long *config) 535{ 536 struct exynos5440_pinctrl_priv_data *priv; 537 const unsigned int *pins; 538 539 priv = pinctrl_dev_get_drvdata(pctldev); 540 pins = priv->pin_groups[group].pins; 541 exynos5440_pinconf_get(pctldev, pins[0], config); 542 return 0; 543} 544 545/* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */ 546static const struct pinconf_ops exynos5440_pinconf_ops = { 547 .pin_config_get = exynos5440_pinconf_get, 548 .pin_config_set = exynos5440_pinconf_set, 549 .pin_config_group_get = exynos5440_pinconf_group_get, 550 .pin_config_group_set = exynos5440_pinconf_group_set, 551}; 552 553/* gpiolib gpio_set callback function */ 554static void exynos5440_gpio_set(struct gpio_chip *gc, unsigned offset, int value) 555{ 556 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev); 557 void __iomem *base = priv->reg_base; 558 u32 data; 559 560 data = readl(base + GPIO_VAL); 561 data &= ~(1 << offset); 562 if (value) 563 data |= 1 << offset; 564 writel(data, base + GPIO_VAL); 565} 566 567/* gpiolib gpio_get callback function */ 568static int exynos5440_gpio_get(struct gpio_chip *gc, unsigned offset) 569{ 570 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev); 571 void __iomem *base = priv->reg_base; 572 u32 data; 573 574 data = readl(base + GPIO_IN); 575 data >>= offset; 576 data &= 1; 577 return data; 578} 579 580/* gpiolib gpio_direction_input callback function */ 581static int exynos5440_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 582{ 583 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev); 584 void __iomem *base = priv->reg_base; 585 u32 data; 586 587 /* first disable the data output enable on this pin */ 588 data = readl(base + GPIO_OE); 589 data &= ~(1 << offset); 590 writel(data, base + GPIO_OE); 591 592 /* now enable input on this pin */ 593 data = readl(base + GPIO_IE); 594 data |= 1 << offset; 595 writel(data, base + GPIO_IE); 596 return 0; 597} 598 599/* gpiolib gpio_direction_output callback function */ 600static int exynos5440_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 601 int value) 602{ 603 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev); 604 void __iomem *base = priv->reg_base; 605 u32 data; 606 607 exynos5440_gpio_set(gc, offset, value); 608 609 /* first disable the data input enable on this pin */ 610 data = readl(base + GPIO_IE); 611 data &= ~(1 << offset); 612 writel(data, base + GPIO_IE); 613 614 /* now enable output on this pin */ 615 data = readl(base + GPIO_OE); 616 data |= 1 << offset; 617 writel(data, base + GPIO_OE); 618 return 0; 619} 620 621/* gpiolib gpio_to_irq callback function */ 622static int exynos5440_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 623{ 624 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev); 625 unsigned int virq; 626 627 if (offset < 16 || offset > 23) 628 return -ENXIO; 629 630 if (!priv->irq_domain) 631 return -ENXIO; 632 633 virq = irq_create_mapping(priv->irq_domain, offset - 16); 634 return virq ? : -ENXIO; 635} 636 637/* parse the pin numbers listed in the 'samsung,exynos5440-pins' property */ 638static int exynos5440_pinctrl_parse_dt_pins(struct platform_device *pdev, 639 struct device_node *cfg_np, unsigned int **pin_list, 640 unsigned int *npins) 641{ 642 struct device *dev = &pdev->dev; 643 struct property *prop; 644 645 prop = of_find_property(cfg_np, "samsung,exynos5440-pins", NULL); 646 if (!prop) 647 return -ENOENT; 648 649 *npins = prop->length / sizeof(unsigned long); 650 if (!*npins) { 651 dev_err(dev, "invalid pin list in %s node", cfg_np->name); 652 return -EINVAL; 653 } 654 655 *pin_list = devm_kzalloc(dev, *npins * sizeof(**pin_list), GFP_KERNEL); 656 if (!*pin_list) { 657 dev_err(dev, "failed to allocate memory for pin list\n"); 658 return -ENOMEM; 659 } 660 661 return of_property_read_u32_array(cfg_np, "samsung,exynos5440-pins", 662 *pin_list, *npins); 663} 664 665/* 666 * Parse the information about all the available pin groups and pin functions 667 * from device node of the pin-controller. 668 */ 669static int exynos5440_pinctrl_parse_dt(struct platform_device *pdev, 670 struct exynos5440_pinctrl_priv_data *priv) 671{ 672 struct device *dev = &pdev->dev; 673 struct device_node *dev_np = dev->of_node; 674 struct device_node *cfg_np; 675 struct exynos5440_pin_group *groups, *grp; 676 struct exynos5440_pmx_func *functions, *func; 677 unsigned *pin_list; 678 unsigned int npins, grp_cnt, func_idx = 0; 679 char *gname, *fname; 680 int ret; 681 682 grp_cnt = of_get_child_count(dev_np); 683 if (!grp_cnt) 684 return -EINVAL; 685 686 groups = devm_kzalloc(dev, grp_cnt * sizeof(*groups), GFP_KERNEL); 687 if (!groups) { 688 dev_err(dev, "failed allocate memory for ping group list\n"); 689 return -EINVAL; 690 } 691 grp = groups; 692 693 functions = devm_kzalloc(dev, grp_cnt * sizeof(*functions), GFP_KERNEL); 694 if (!functions) { 695 dev_err(dev, "failed to allocate memory for function list\n"); 696 return -EINVAL; 697 } 698 func = functions; 699 700 /* 701 * Iterate over all the child nodes of the pin controller node 702 * and create pin groups and pin function lists. 703 */ 704 for_each_child_of_node(dev_np, cfg_np) { 705 u32 function; 706 707 ret = exynos5440_pinctrl_parse_dt_pins(pdev, cfg_np, 708 &pin_list, &npins); 709 if (ret) { 710 gname = NULL; 711 goto skip_to_pin_function; 712 } 713 714 /* derive pin group name from the node name */ 715 gname = devm_kzalloc(dev, strlen(cfg_np->name) + GSUFFIX_LEN, 716 GFP_KERNEL); 717 if (!gname) { 718 dev_err(dev, "failed to alloc memory for group name\n"); 719 return -ENOMEM; 720 } 721 snprintf(gname, strlen(cfg_np->name) + 4, "%s%s", cfg_np->name, 722 GROUP_SUFFIX); 723 724 grp->name = gname; 725 grp->pins = pin_list; 726 grp->num_pins = npins; 727 grp++; 728 729skip_to_pin_function: 730 ret = of_property_read_u32(cfg_np, "samsung,exynos5440-pin-function", 731 &function); 732 if (ret) 733 continue; 734 735 /* derive function name from the node name */ 736 fname = devm_kzalloc(dev, strlen(cfg_np->name) + FSUFFIX_LEN, 737 GFP_KERNEL); 738 if (!fname) { 739 dev_err(dev, "failed to alloc memory for func name\n"); 740 return -ENOMEM; 741 } 742 snprintf(fname, strlen(cfg_np->name) + 4, "%s%s", cfg_np->name, 743 FUNCTION_SUFFIX); 744 745 func->name = fname; 746 func->groups = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL); 747 if (!func->groups) { 748 dev_err(dev, "failed to alloc memory for group list " 749 "in pin function"); 750 return -ENOMEM; 751 } 752 func->groups[0] = gname; 753 func->num_groups = gname ? 1 : 0; 754 func->function = function; 755 func++; 756 func_idx++; 757 } 758 759 priv->pin_groups = groups; 760 priv->nr_groups = grp_cnt; 761 priv->pmx_functions = functions; 762 priv->nr_functions = func_idx; 763 return 0; 764} 765 766/* register the pinctrl interface with the pinctrl subsystem */ 767static int exynos5440_pinctrl_register(struct platform_device *pdev, 768 struct exynos5440_pinctrl_priv_data *priv) 769{ 770 struct device *dev = &pdev->dev; 771 struct pinctrl_desc *ctrldesc; 772 struct pinctrl_dev *pctl_dev; 773 struct pinctrl_pin_desc *pindesc, *pdesc; 774 char *pin_names; 775 int pin, ret; 776 777 ctrldesc = devm_kzalloc(dev, sizeof(*ctrldesc), GFP_KERNEL); 778 if (!ctrldesc) { 779 dev_err(dev, "could not allocate memory for pinctrl desc\n"); 780 return -ENOMEM; 781 } 782 783 ctrldesc->name = "exynos5440-pinctrl"; 784 ctrldesc->owner = THIS_MODULE; 785 ctrldesc->pctlops = &exynos5440_pctrl_ops; 786 ctrldesc->pmxops = &exynos5440_pinmux_ops; 787 ctrldesc->confops = &exynos5440_pinconf_ops; 788 789 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) * 790 EXYNOS5440_MAX_PINS, GFP_KERNEL); 791 if (!pindesc) { 792 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n"); 793 return -ENOMEM; 794 } 795 ctrldesc->pins = pindesc; 796 ctrldesc->npins = EXYNOS5440_MAX_PINS; 797 798 /* dynamically populate the pin number and pin name for pindesc */ 799 for (pin = 0, pdesc = pindesc; pin < ctrldesc->npins; pin++, pdesc++) 800 pdesc->number = pin; 801 802 /* 803 * allocate space for storing the dynamically generated names for all 804 * the pins which belong to this pin-controller. 805 */ 806 pin_names = devm_kzalloc(&pdev->dev, sizeof(char) * PIN_NAME_LENGTH * 807 ctrldesc->npins, GFP_KERNEL); 808 if (!pin_names) { 809 dev_err(&pdev->dev, "mem alloc for pin names failed\n"); 810 return -ENOMEM; 811 } 812 813 /* for each pin, set the name of the pin */ 814 for (pin = 0; pin < ctrldesc->npins; pin++) { 815 snprintf(pin_names, 6, "gpio%02d", pin); 816 pdesc = pindesc + pin; 817 pdesc->name = pin_names; 818 pin_names += PIN_NAME_LENGTH; 819 } 820 821 ret = exynos5440_pinctrl_parse_dt(pdev, priv); 822 if (ret) 823 return ret; 824 825 pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, priv); 826 if (!pctl_dev) { 827 dev_err(&pdev->dev, "could not register pinctrl driver\n"); 828 return -EINVAL; 829 } 830 831 priv->range.name = "exynos5440-pctrl-gpio-range"; 832 priv->range.id = 0; 833 priv->range.base = 0; 834 priv->range.npins = EXYNOS5440_MAX_PINS; 835 priv->range.gc = priv->gc; 836 pinctrl_add_gpio_range(pctl_dev, &priv->range); 837 return 0; 838} 839 840/* register the gpiolib interface with the gpiolib subsystem */ 841static int exynos5440_gpiolib_register(struct platform_device *pdev, 842 struct exynos5440_pinctrl_priv_data *priv) 843{ 844 struct gpio_chip *gc; 845 int ret; 846 847 gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL); 848 if (!gc) { 849 dev_err(&pdev->dev, "mem alloc for gpio_chip failed\n"); 850 return -ENOMEM; 851 } 852 853 priv->gc = gc; 854 gc->base = 0; 855 gc->ngpio = EXYNOS5440_MAX_PINS; 856 gc->dev = &pdev->dev; 857 gc->set = exynos5440_gpio_set; 858 gc->get = exynos5440_gpio_get; 859 gc->direction_input = exynos5440_gpio_direction_input; 860 gc->direction_output = exynos5440_gpio_direction_output; 861 gc->to_irq = exynos5440_gpio_to_irq; 862 gc->label = "gpiolib-exynos5440"; 863 gc->owner = THIS_MODULE; 864 ret = gpiochip_add(gc); 865 if (ret) { 866 dev_err(&pdev->dev, "failed to register gpio_chip %s, error " 867 "code: %d\n", gc->label, ret); 868 return ret; 869 } 870 871 return 0; 872} 873 874/* unregister the gpiolib interface with the gpiolib subsystem */ 875static int exynos5440_gpiolib_unregister(struct platform_device *pdev, 876 struct exynos5440_pinctrl_priv_data *priv) 877{ 878 gpiochip_remove(priv->gc); 879 return 0; 880} 881 882static void exynos5440_gpio_irq_unmask(struct irq_data *irqd) 883{ 884 struct exynos5440_pinctrl_priv_data *d; 885 unsigned long gpio_int; 886 887 d = irq_data_get_irq_chip_data(irqd); 888 gpio_int = readl(d->reg_base + GPIO_INT); 889 gpio_int |= 1 << irqd->hwirq; 890 writel(gpio_int, d->reg_base + GPIO_INT); 891} 892 893static void exynos5440_gpio_irq_mask(struct irq_data *irqd) 894{ 895 struct exynos5440_pinctrl_priv_data *d; 896 unsigned long gpio_int; 897 898 d = irq_data_get_irq_chip_data(irqd); 899 gpio_int = readl(d->reg_base + GPIO_INT); 900 gpio_int &= ~(1 << irqd->hwirq); 901 writel(gpio_int, d->reg_base + GPIO_INT); 902} 903 904/* irq_chip for gpio interrupts */ 905static struct irq_chip exynos5440_gpio_irq_chip = { 906 .name = "exynos5440_gpio_irq_chip", 907 .irq_unmask = exynos5440_gpio_irq_unmask, 908 .irq_mask = exynos5440_gpio_irq_mask, 909}; 910 911/* interrupt handler for GPIO interrupts 0..7 */ 912static irqreturn_t exynos5440_gpio_irq(int irq, void *data) 913{ 914 struct exynos5440_gpio_intr_data *intd = data; 915 struct exynos5440_pinctrl_priv_data *d = intd->priv; 916 int virq; 917 918 virq = irq_linear_revmap(d->irq_domain, intd->gpio_int); 919 if (!virq) 920 return IRQ_NONE; 921 generic_handle_irq(virq); 922 return IRQ_HANDLED; 923} 924 925static int exynos5440_gpio_irq_map(struct irq_domain *h, unsigned int virq, 926 irq_hw_number_t hw) 927{ 928 struct exynos5440_pinctrl_priv_data *d = h->host_data; 929 930 irq_set_chip_data(virq, d); 931 irq_set_chip_and_handler(virq, &exynos5440_gpio_irq_chip, 932 handle_level_irq); 933 set_irq_flags(virq, IRQF_VALID); 934 return 0; 935} 936 937/* irq domain callbacks for gpio interrupt controller */ 938static const struct irq_domain_ops exynos5440_gpio_irqd_ops = { 939 .map = exynos5440_gpio_irq_map, 940 .xlate = irq_domain_xlate_twocell, 941}; 942 943/* setup handling of gpio interrupts */ 944static int exynos5440_gpio_irq_init(struct platform_device *pdev, 945 struct exynos5440_pinctrl_priv_data *priv) 946{ 947 struct device *dev = &pdev->dev; 948 struct exynos5440_gpio_intr_data *intd; 949 int i, irq, ret; 950 951 intd = devm_kzalloc(dev, sizeof(*intd) * EXYNOS5440_MAX_GPIO_INT, 952 GFP_KERNEL); 953 if (!intd) { 954 dev_err(dev, "failed to allocate memory for gpio intr data\n"); 955 return -ENOMEM; 956 } 957 958 for (i = 0; i < EXYNOS5440_MAX_GPIO_INT; i++) { 959 irq = irq_of_parse_and_map(dev->of_node, i); 960 if (irq <= 0) { 961 dev_err(dev, "irq parsing failed\n"); 962 return -EINVAL; 963 } 964 965 intd->gpio_int = i; 966 intd->priv = priv; 967 ret = devm_request_irq(dev, irq, exynos5440_gpio_irq, 968 0, dev_name(dev), intd++); 969 if (ret) { 970 dev_err(dev, "irq request failed\n"); 971 return -ENXIO; 972 } 973 } 974 975 priv->irq_domain = irq_domain_add_linear(dev->of_node, 976 EXYNOS5440_MAX_GPIO_INT, 977 &exynos5440_gpio_irqd_ops, priv); 978 if (!priv->irq_domain) { 979 dev_err(dev, "failed to create irq domain\n"); 980 return -ENXIO; 981 } 982 983 return 0; 984} 985 986static int exynos5440_pinctrl_probe(struct platform_device *pdev) 987{ 988 struct device *dev = &pdev->dev; 989 struct exynos5440_pinctrl_priv_data *priv; 990 struct resource *res; 991 int ret; 992 993 if (!dev->of_node) { 994 dev_err(dev, "device tree node not found\n"); 995 return -ENODEV; 996 } 997 998 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 999 if (!priv) { 1000 dev_err(dev, "could not allocate memory for private data\n"); 1001 return -ENOMEM; 1002 } 1003 1004 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1005 priv->reg_base = devm_ioremap_resource(&pdev->dev, res); 1006 if (IS_ERR(priv->reg_base)) 1007 return PTR_ERR(priv->reg_base); 1008 1009 ret = exynos5440_gpiolib_register(pdev, priv); 1010 if (ret) 1011 return ret; 1012 1013 ret = exynos5440_pinctrl_register(pdev, priv); 1014 if (ret) { 1015 exynos5440_gpiolib_unregister(pdev, priv); 1016 return ret; 1017 } 1018 1019 ret = exynos5440_gpio_irq_init(pdev, priv); 1020 if (ret) { 1021 dev_err(dev, "failed to setup gpio interrupts\n"); 1022 return ret; 1023 } 1024 1025 platform_set_drvdata(pdev, priv); 1026 dev_info(dev, "EXYNOS5440 pinctrl driver registered\n"); 1027 return 0; 1028} 1029 1030static const struct of_device_id exynos5440_pinctrl_dt_match[] = { 1031 { .compatible = "samsung,exynos5440-pinctrl" }, 1032 {}, 1033}; 1034MODULE_DEVICE_TABLE(of, exynos5440_pinctrl_dt_match); 1035 1036static struct platform_driver exynos5440_pinctrl_driver = { 1037 .probe = exynos5440_pinctrl_probe, 1038 .driver = { 1039 .name = "exynos5440-pinctrl", 1040 .of_match_table = exynos5440_pinctrl_dt_match, 1041 }, 1042}; 1043 1044static int __init exynos5440_pinctrl_drv_register(void) 1045{ 1046 return platform_driver_register(&exynos5440_pinctrl_driver); 1047} 1048postcore_initcall(exynos5440_pinctrl_drv_register); 1049 1050static void __exit exynos5440_pinctrl_drv_unregister(void) 1051{ 1052 platform_driver_unregister(&exynos5440_pinctrl_driver); 1053} 1054module_exit(exynos5440_pinctrl_drv_unregister); 1055 1056MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com>"); 1057MODULE_DESCRIPTION("Samsung EXYNOS5440 SoC pinctrl driver"); 1058MODULE_LICENSE("GPL v2"); 1059