1/*
2 * GPIO driver for AMD
3 *
4 * Copyright (c) 2014,2015 Ken Xue <Ken.Xue@amd.com>
5 *		Jeff Wu <Jeff.Wu@amd.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 */
12
13#ifndef _PINCTRL_AMD_H
14#define _PINCTRL_AMD_H
15
16#define TOTAL_NUMBER_OF_PINS	192
17#define AMD_GPIO_PINS_PER_BANK  64
18#define AMD_GPIO_TOTAL_BANKS    3
19
20#define AMD_GPIO_PINS_BANK0     63
21#define AMD_GPIO_PINS_BANK1     64
22#define AMD_GPIO_PINS_BANK2     56
23
24#define WAKE_INT_MASTER_REG 0xfc
25#define EOI_MASK (1 << 29)
26
27#define WAKE_INT_STATUS_REG0 0x2f8
28#define WAKE_INT_STATUS_REG1 0x2fc
29
30#define DB_TMR_OUT_OFF			0
31#define DB_TMR_OUT_UNIT_OFF		4
32#define DB_CNTRL_OFF			5
33#define DB_TMR_LARGE_OFF		7
34#define LEVEL_TRIG_OFF			8
35#define ACTIVE_LEVEL_OFF		9
36#define INTERRUPT_ENABLE_OFF		11
37#define INTERRUPT_MASK_OFF		12
38#define WAKE_CNTRL_OFF			13
39#define PIN_STS_OFF			16
40#define DRV_STRENGTH_SEL_OFF		17
41#define PULL_UP_SEL_OFF			19
42#define PULL_UP_ENABLE_OFF		20
43#define PULL_DOWN_ENABLE_OFF		21
44#define OUTPUT_VALUE_OFF		22
45#define OUTPUT_ENABLE_OFF		23
46#define SW_CNTRL_IN_OFF			24
47#define SW_CNTRL_EN_OFF			25
48#define INTERRUPT_STS_OFF		28
49#define WAKE_STS_OFF			29
50
51#define DB_TMR_OUT_MASK	0xFUL
52#define DB_CNTRl_MASK	0x3UL
53#define ACTIVE_LEVEL_MASK	0x3UL
54#define DRV_STRENGTH_SEL_MASK	0x3UL
55
56#define DB_TYPE_NO_DEBOUNCE               0x0UL
57#define DB_TYPE_PRESERVE_LOW_GLITCH       0x1UL
58#define DB_TYPE_PRESERVE_HIGH_GLITCH      0x2UL
59#define DB_TYPE_REMOVE_GLITCH             0x3UL
60
61#define EDGE_TRAGGER	0x0UL
62#define LEVEL_TRIGGER	0x1UL
63
64#define ACTIVE_HIGH	0x0UL
65#define ACTIVE_LOW	0x1UL
66#define BOTH_EADGE	0x2UL
67
68#define ENABLE_INTERRUPT	0x1UL
69#define DISABLE_INTERRUPT	0x0UL
70
71#define ENABLE_INTERRUPT_MASK	0x0UL
72#define DISABLE_INTERRUPT_MASK	0x1UL
73
74#define CLR_INTR_STAT	0x1UL
75
76struct amd_pingroup {
77	const char *name;
78	const unsigned *pins;
79	unsigned npins;
80};
81
82struct amd_function {
83	const char *name;
84	const char * const *groups;
85	unsigned ngroups;
86};
87
88struct amd_gpio {
89	spinlock_t              lock;
90	void __iomem            *base;
91
92	const struct amd_pingroup *groups;
93	u32 ngroups;
94	struct pinctrl_dev *pctrl;
95	struct gpio_chip        gc;
96	struct resource         *res;
97	struct platform_device  *pdev;
98};
99
100/*  KERNCZ configuration*/
101static const struct pinctrl_pin_desc kerncz_pins[] = {
102	PINCTRL_PIN(0, "GPIO_0"),
103	PINCTRL_PIN(1, "GPIO_1"),
104	PINCTRL_PIN(2, "GPIO_2"),
105	PINCTRL_PIN(3, "GPIO_3"),
106	PINCTRL_PIN(4, "GPIO_4"),
107	PINCTRL_PIN(5, "GPIO_5"),
108	PINCTRL_PIN(6, "GPIO_6"),
109	PINCTRL_PIN(7, "GPIO_7"),
110	PINCTRL_PIN(8, "GPIO_8"),
111	PINCTRL_PIN(9, "GPIO_9"),
112	PINCTRL_PIN(10, "GPIO_10"),
113	PINCTRL_PIN(11, "GPIO_11"),
114	PINCTRL_PIN(12, "GPIO_12"),
115	PINCTRL_PIN(13, "GPIO_13"),
116	PINCTRL_PIN(14, "GPIO_14"),
117	PINCTRL_PIN(15, "GPIO_15"),
118	PINCTRL_PIN(16, "GPIO_16"),
119	PINCTRL_PIN(17, "GPIO_17"),
120	PINCTRL_PIN(18, "GPIO_18"),
121	PINCTRL_PIN(19, "GPIO_19"),
122	PINCTRL_PIN(20, "GPIO_20"),
123	PINCTRL_PIN(23, "GPIO_23"),
124	PINCTRL_PIN(24, "GPIO_24"),
125	PINCTRL_PIN(25, "GPIO_25"),
126	PINCTRL_PIN(26, "GPIO_26"),
127	PINCTRL_PIN(39, "GPIO_39"),
128	PINCTRL_PIN(40, "GPIO_40"),
129	PINCTRL_PIN(43, "GPIO_42"),
130	PINCTRL_PIN(46, "GPIO_46"),
131	PINCTRL_PIN(47, "GPIO_47"),
132	PINCTRL_PIN(48, "GPIO_48"),
133	PINCTRL_PIN(49, "GPIO_49"),
134	PINCTRL_PIN(50, "GPIO_50"),
135	PINCTRL_PIN(51, "GPIO_51"),
136	PINCTRL_PIN(52, "GPIO_52"),
137	PINCTRL_PIN(53, "GPIO_53"),
138	PINCTRL_PIN(54, "GPIO_54"),
139	PINCTRL_PIN(55, "GPIO_55"),
140	PINCTRL_PIN(56, "GPIO_56"),
141	PINCTRL_PIN(57, "GPIO_57"),
142	PINCTRL_PIN(58, "GPIO_58"),
143	PINCTRL_PIN(59, "GPIO_59"),
144	PINCTRL_PIN(60, "GPIO_60"),
145	PINCTRL_PIN(61, "GPIO_61"),
146	PINCTRL_PIN(62, "GPIO_62"),
147	PINCTRL_PIN(64, "GPIO_64"),
148	PINCTRL_PIN(65, "GPIO_65"),
149	PINCTRL_PIN(66, "GPIO_66"),
150	PINCTRL_PIN(68, "GPIO_68"),
151	PINCTRL_PIN(69, "GPIO_69"),
152	PINCTRL_PIN(70, "GPIO_70"),
153	PINCTRL_PIN(71, "GPIO_71"),
154	PINCTRL_PIN(72, "GPIO_72"),
155	PINCTRL_PIN(74, "GPIO_74"),
156	PINCTRL_PIN(75, "GPIO_75"),
157	PINCTRL_PIN(76, "GPIO_76"),
158	PINCTRL_PIN(84, "GPIO_84"),
159	PINCTRL_PIN(85, "GPIO_85"),
160	PINCTRL_PIN(86, "GPIO_86"),
161	PINCTRL_PIN(87, "GPIO_87"),
162	PINCTRL_PIN(88, "GPIO_88"),
163	PINCTRL_PIN(89, "GPIO_89"),
164	PINCTRL_PIN(90, "GPIO_90"),
165	PINCTRL_PIN(91, "GPIO_91"),
166	PINCTRL_PIN(92, "GPIO_92"),
167	PINCTRL_PIN(93, "GPIO_93"),
168	PINCTRL_PIN(95, "GPIO_95"),
169	PINCTRL_PIN(96, "GPIO_96"),
170	PINCTRL_PIN(97, "GPIO_97"),
171	PINCTRL_PIN(98, "GPIO_98"),
172	PINCTRL_PIN(99, "GPIO_99"),
173	PINCTRL_PIN(100, "GPIO_100"),
174	PINCTRL_PIN(101, "GPIO_101"),
175	PINCTRL_PIN(102, "GPIO_102"),
176	PINCTRL_PIN(113, "GPIO_113"),
177	PINCTRL_PIN(114, "GPIO_114"),
178	PINCTRL_PIN(115, "GPIO_115"),
179	PINCTRL_PIN(116, "GPIO_116"),
180	PINCTRL_PIN(117, "GPIO_117"),
181	PINCTRL_PIN(118, "GPIO_118"),
182	PINCTRL_PIN(119, "GPIO_119"),
183	PINCTRL_PIN(120, "GPIO_120"),
184	PINCTRL_PIN(121, "GPIO_121"),
185	PINCTRL_PIN(122, "GPIO_122"),
186	PINCTRL_PIN(126, "GPIO_126"),
187	PINCTRL_PIN(129, "GPIO_129"),
188	PINCTRL_PIN(130, "GPIO_130"),
189	PINCTRL_PIN(131, "GPIO_131"),
190	PINCTRL_PIN(132, "GPIO_132"),
191	PINCTRL_PIN(133, "GPIO_133"),
192	PINCTRL_PIN(135, "GPIO_135"),
193	PINCTRL_PIN(136, "GPIO_136"),
194	PINCTRL_PIN(137, "GPIO_137"),
195	PINCTRL_PIN(138, "GPIO_138"),
196	PINCTRL_PIN(139, "GPIO_139"),
197	PINCTRL_PIN(140, "GPIO_140"),
198	PINCTRL_PIN(141, "GPIO_141"),
199	PINCTRL_PIN(142, "GPIO_142"),
200	PINCTRL_PIN(143, "GPIO_143"),
201	PINCTRL_PIN(144, "GPIO_144"),
202	PINCTRL_PIN(145, "GPIO_145"),
203	PINCTRL_PIN(146, "GPIO_146"),
204	PINCTRL_PIN(147, "GPIO_147"),
205	PINCTRL_PIN(148, "GPIO_148"),
206	PINCTRL_PIN(166, "GPIO_166"),
207	PINCTRL_PIN(167, "GPIO_167"),
208	PINCTRL_PIN(168, "GPIO_168"),
209	PINCTRL_PIN(169, "GPIO_169"),
210	PINCTRL_PIN(170, "GPIO_170"),
211	PINCTRL_PIN(171, "GPIO_171"),
212	PINCTRL_PIN(172, "GPIO_172"),
213	PINCTRL_PIN(173, "GPIO_173"),
214	PINCTRL_PIN(174, "GPIO_174"),
215	PINCTRL_PIN(175, "GPIO_175"),
216	PINCTRL_PIN(176, "GPIO_176"),
217	PINCTRL_PIN(177, "GPIO_177"),
218};
219
220static const unsigned i2c0_pins[] = {145, 146};
221static const unsigned i2c1_pins[] = {147, 148};
222static const unsigned i2c2_pins[] = {113, 114};
223static const unsigned i2c3_pins[] = {19, 20};
224
225static const unsigned uart0_pins[] = {135, 136, 137, 138, 139};
226static const unsigned uart1_pins[] = {140, 141, 142, 143, 144};
227
228static const struct amd_pingroup kerncz_groups[] = {
229	{
230		.name = "i2c0",
231		.pins = i2c0_pins,
232		.npins = 2,
233	},
234	{
235		.name = "i2c1",
236		.pins = i2c1_pins,
237		.npins = 2,
238	},
239	{
240		.name = "i2c2",
241		.pins = i2c2_pins,
242		.npins = 2,
243	},
244	{
245		.name = "i2c3",
246		.pins = i2c3_pins,
247		.npins = 2,
248	},
249	{
250		.name = "uart0",
251		.pins = uart0_pins,
252		.npins = 9,
253	},
254	{
255		.name = "uart1",
256		.pins = uart1_pins,
257		.npins = 5,
258	},
259};
260
261#endif
262