1/*
2 * i.MX1 pinctrl driver based on imx pinmux core
3 *
4 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/platform_device.h>
15#include <linux/pinctrl/pinctrl.h>
16
17#include "pinctrl-imx1.h"
18
19#define PAD_ID(port, pin)	((port) * 32 + (pin))
20#define PA	0
21#define PB	1
22#define PC	2
23#define PD	3
24
25enum imx1_pads {
26	MX1_PAD_A24		= PAD_ID(PA, 0),
27	MX1_PAD_TIN		= PAD_ID(PA, 1),
28	MX1_PAD_PWMO		= PAD_ID(PA, 2),
29	MX1_PAD_CSI_MCLK	= PAD_ID(PA, 3),
30	MX1_PAD_CSI_D0		= PAD_ID(PA, 4),
31	MX1_PAD_CSI_D1		= PAD_ID(PA, 5),
32	MX1_PAD_CSI_D2		= PAD_ID(PA, 6),
33	MX1_PAD_CSI_D3		= PAD_ID(PA, 7),
34	MX1_PAD_CSI_D4		= PAD_ID(PA, 8),
35	MX1_PAD_CSI_D5		= PAD_ID(PA, 9),
36	MX1_PAD_CSI_D6		= PAD_ID(PA, 10),
37	MX1_PAD_CSI_D7		= PAD_ID(PA, 11),
38	MX1_PAD_CSI_VSYNC	= PAD_ID(PA, 12),
39	MX1_PAD_CSI_HSYNC	= PAD_ID(PA, 13),
40	MX1_PAD_CSI_PIXCLK	= PAD_ID(PA, 14),
41	MX1_PAD_I2C_SDA		= PAD_ID(PA, 15),
42	MX1_PAD_I2C_SCL		= PAD_ID(PA, 16),
43	MX1_PAD_DTACK		= PAD_ID(PA, 17),
44	MX1_PAD_BCLK		= PAD_ID(PA, 18),
45	MX1_PAD_LBA		= PAD_ID(PA, 19),
46	MX1_PAD_ECB		= PAD_ID(PA, 20),
47	MX1_PAD_A0		= PAD_ID(PA, 21),
48	MX1_PAD_CS4		= PAD_ID(PA, 22),
49	MX1_PAD_CS5		= PAD_ID(PA, 23),
50	MX1_PAD_A16		= PAD_ID(PA, 24),
51	MX1_PAD_A17		= PAD_ID(PA, 25),
52	MX1_PAD_A18		= PAD_ID(PA, 26),
53	MX1_PAD_A19		= PAD_ID(PA, 27),
54	MX1_PAD_A20		= PAD_ID(PA, 28),
55	MX1_PAD_A21		= PAD_ID(PA, 29),
56	MX1_PAD_A22		= PAD_ID(PA, 30),
57	MX1_PAD_A23		= PAD_ID(PA, 31),
58	MX1_PAD_SD_DAT0		= PAD_ID(PB, 8),
59	MX1_PAD_SD_DAT1		= PAD_ID(PB, 9),
60	MX1_PAD_SD_DAT2		= PAD_ID(PB, 10),
61	MX1_PAD_SD_DAT3		= PAD_ID(PB, 11),
62	MX1_PAD_SD_SCLK		= PAD_ID(PB, 12),
63	MX1_PAD_SD_CMD		= PAD_ID(PB, 13),
64	MX1_PAD_SIM_SVEN	= PAD_ID(PB, 14),
65	MX1_PAD_SIM_PD		= PAD_ID(PB, 15),
66	MX1_PAD_SIM_TX		= PAD_ID(PB, 16),
67	MX1_PAD_SIM_RX		= PAD_ID(PB, 17),
68	MX1_PAD_SIM_RST		= PAD_ID(PB, 18),
69	MX1_PAD_SIM_CLK		= PAD_ID(PB, 19),
70	MX1_PAD_USBD_AFE	= PAD_ID(PB, 20),
71	MX1_PAD_USBD_OE		= PAD_ID(PB, 21),
72	MX1_PAD_USBD_RCV	= PAD_ID(PB, 22),
73	MX1_PAD_USBD_SUSPND	= PAD_ID(PB, 23),
74	MX1_PAD_USBD_VP		= PAD_ID(PB, 24),
75	MX1_PAD_USBD_VM		= PAD_ID(PB, 25),
76	MX1_PAD_USBD_VPO	= PAD_ID(PB, 26),
77	MX1_PAD_USBD_VMO	= PAD_ID(PB, 27),
78	MX1_PAD_UART2_CTS	= PAD_ID(PB, 28),
79	MX1_PAD_UART2_RTS	= PAD_ID(PB, 29),
80	MX1_PAD_UART2_TXD	= PAD_ID(PB, 30),
81	MX1_PAD_UART2_RXD	= PAD_ID(PB, 31),
82	MX1_PAD_SSI_RXFS	= PAD_ID(PC, 3),
83	MX1_PAD_SSI_RXCLK	= PAD_ID(PC, 4),
84	MX1_PAD_SSI_RXDAT	= PAD_ID(PC, 5),
85	MX1_PAD_SSI_TXDAT	= PAD_ID(PC, 6),
86	MX1_PAD_SSI_TXFS	= PAD_ID(PC, 7),
87	MX1_PAD_SSI_TXCLK	= PAD_ID(PC, 8),
88	MX1_PAD_UART1_CTS	= PAD_ID(PC, 9),
89	MX1_PAD_UART1_RTS	= PAD_ID(PC, 10),
90	MX1_PAD_UART1_TXD	= PAD_ID(PC, 11),
91	MX1_PAD_UART1_RXD	= PAD_ID(PC, 12),
92	MX1_PAD_SPI1_RDY	= PAD_ID(PC, 13),
93	MX1_PAD_SPI1_SCLK	= PAD_ID(PC, 14),
94	MX1_PAD_SPI1_SS		= PAD_ID(PC, 15),
95	MX1_PAD_SPI1_MISO	= PAD_ID(PC, 16),
96	MX1_PAD_SPI1_MOSI	= PAD_ID(PC, 17),
97	MX1_PAD_BT13		= PAD_ID(PC, 19),
98	MX1_PAD_BT12		= PAD_ID(PC, 20),
99	MX1_PAD_BT11		= PAD_ID(PC, 21),
100	MX1_PAD_BT10		= PAD_ID(PC, 22),
101	MX1_PAD_BT9		= PAD_ID(PC, 23),
102	MX1_PAD_BT8		= PAD_ID(PC, 24),
103	MX1_PAD_BT7		= PAD_ID(PC, 25),
104	MX1_PAD_BT6		= PAD_ID(PC, 26),
105	MX1_PAD_BT5		= PAD_ID(PC, 27),
106	MX1_PAD_BT4		= PAD_ID(PC, 28),
107	MX1_PAD_BT3		= PAD_ID(PC, 29),
108	MX1_PAD_BT2		= PAD_ID(PC, 30),
109	MX1_PAD_BT1		= PAD_ID(PC, 31),
110	MX1_PAD_LSCLK		= PAD_ID(PD, 6),
111	MX1_PAD_REV		= PAD_ID(PD, 7),
112	MX1_PAD_CLS		= PAD_ID(PD, 8),
113	MX1_PAD_PS		= PAD_ID(PD, 9),
114	MX1_PAD_SPL_SPR		= PAD_ID(PD, 10),
115	MX1_PAD_CONTRAST	= PAD_ID(PD, 11),
116	MX1_PAD_ACD_OE		= PAD_ID(PD, 12),
117	MX1_PAD_LP_HSYNC	= PAD_ID(PD, 13),
118	MX1_PAD_FLM_VSYNC	= PAD_ID(PD, 14),
119	MX1_PAD_LD0		= PAD_ID(PD, 15),
120	MX1_PAD_LD1		= PAD_ID(PD, 16),
121	MX1_PAD_LD2		= PAD_ID(PD, 17),
122	MX1_PAD_LD3		= PAD_ID(PD, 18),
123	MX1_PAD_LD4		= PAD_ID(PD, 19),
124	MX1_PAD_LD5		= PAD_ID(PD, 20),
125	MX1_PAD_LD6		= PAD_ID(PD, 21),
126	MX1_PAD_LD7		= PAD_ID(PD, 22),
127	MX1_PAD_LD8		= PAD_ID(PD, 23),
128	MX1_PAD_LD9		= PAD_ID(PD, 24),
129	MX1_PAD_LD10		= PAD_ID(PD, 25),
130	MX1_PAD_LD11		= PAD_ID(PD, 26),
131	MX1_PAD_LD12		= PAD_ID(PD, 27),
132	MX1_PAD_LD13		= PAD_ID(PD, 28),
133	MX1_PAD_LD14		= PAD_ID(PD, 29),
134	MX1_PAD_LD15		= PAD_ID(PD, 30),
135	MX1_PAD_TMR2OUT		= PAD_ID(PD, 31),
136};
137
138/* Pad names for the pinmux subsystem */
139static const struct pinctrl_pin_desc imx1_pinctrl_pads[] = {
140	IMX_PINCTRL_PIN(MX1_PAD_A24),
141	IMX_PINCTRL_PIN(MX1_PAD_TIN),
142	IMX_PINCTRL_PIN(MX1_PAD_PWMO),
143	IMX_PINCTRL_PIN(MX1_PAD_CSI_MCLK),
144	IMX_PINCTRL_PIN(MX1_PAD_CSI_D0),
145	IMX_PINCTRL_PIN(MX1_PAD_CSI_D1),
146	IMX_PINCTRL_PIN(MX1_PAD_CSI_D2),
147	IMX_PINCTRL_PIN(MX1_PAD_CSI_D3),
148	IMX_PINCTRL_PIN(MX1_PAD_CSI_D4),
149	IMX_PINCTRL_PIN(MX1_PAD_CSI_D5),
150	IMX_PINCTRL_PIN(MX1_PAD_CSI_D6),
151	IMX_PINCTRL_PIN(MX1_PAD_CSI_D7),
152	IMX_PINCTRL_PIN(MX1_PAD_CSI_VSYNC),
153	IMX_PINCTRL_PIN(MX1_PAD_CSI_HSYNC),
154	IMX_PINCTRL_PIN(MX1_PAD_CSI_PIXCLK),
155	IMX_PINCTRL_PIN(MX1_PAD_I2C_SDA),
156	IMX_PINCTRL_PIN(MX1_PAD_I2C_SCL),
157	IMX_PINCTRL_PIN(MX1_PAD_DTACK),
158	IMX_PINCTRL_PIN(MX1_PAD_BCLK),
159	IMX_PINCTRL_PIN(MX1_PAD_LBA),
160	IMX_PINCTRL_PIN(MX1_PAD_ECB),
161	IMX_PINCTRL_PIN(MX1_PAD_A0),
162	IMX_PINCTRL_PIN(MX1_PAD_CS4),
163	IMX_PINCTRL_PIN(MX1_PAD_CS5),
164	IMX_PINCTRL_PIN(MX1_PAD_A16),
165	IMX_PINCTRL_PIN(MX1_PAD_A17),
166	IMX_PINCTRL_PIN(MX1_PAD_A18),
167	IMX_PINCTRL_PIN(MX1_PAD_A19),
168	IMX_PINCTRL_PIN(MX1_PAD_A20),
169	IMX_PINCTRL_PIN(MX1_PAD_A21),
170	IMX_PINCTRL_PIN(MX1_PAD_A22),
171	IMX_PINCTRL_PIN(MX1_PAD_A23),
172	IMX_PINCTRL_PIN(MX1_PAD_SD_DAT0),
173	IMX_PINCTRL_PIN(MX1_PAD_SD_DAT1),
174	IMX_PINCTRL_PIN(MX1_PAD_SD_DAT2),
175	IMX_PINCTRL_PIN(MX1_PAD_SD_DAT3),
176	IMX_PINCTRL_PIN(MX1_PAD_SD_SCLK),
177	IMX_PINCTRL_PIN(MX1_PAD_SD_CMD),
178	IMX_PINCTRL_PIN(MX1_PAD_SIM_SVEN),
179	IMX_PINCTRL_PIN(MX1_PAD_SIM_PD),
180	IMX_PINCTRL_PIN(MX1_PAD_SIM_TX),
181	IMX_PINCTRL_PIN(MX1_PAD_SIM_RX),
182	IMX_PINCTRL_PIN(MX1_PAD_SIM_CLK),
183	IMX_PINCTRL_PIN(MX1_PAD_USBD_AFE),
184	IMX_PINCTRL_PIN(MX1_PAD_USBD_OE),
185	IMX_PINCTRL_PIN(MX1_PAD_USBD_RCV),
186	IMX_PINCTRL_PIN(MX1_PAD_USBD_SUSPND),
187	IMX_PINCTRL_PIN(MX1_PAD_USBD_VP),
188	IMX_PINCTRL_PIN(MX1_PAD_USBD_VM),
189	IMX_PINCTRL_PIN(MX1_PAD_USBD_VPO),
190	IMX_PINCTRL_PIN(MX1_PAD_USBD_VMO),
191	IMX_PINCTRL_PIN(MX1_PAD_UART2_CTS),
192	IMX_PINCTRL_PIN(MX1_PAD_UART2_RTS),
193	IMX_PINCTRL_PIN(MX1_PAD_UART2_TXD),
194	IMX_PINCTRL_PIN(MX1_PAD_UART2_RXD),
195	IMX_PINCTRL_PIN(MX1_PAD_SSI_RXFS),
196	IMX_PINCTRL_PIN(MX1_PAD_SSI_RXCLK),
197	IMX_PINCTRL_PIN(MX1_PAD_SSI_RXDAT),
198	IMX_PINCTRL_PIN(MX1_PAD_SSI_TXDAT),
199	IMX_PINCTRL_PIN(MX1_PAD_SSI_TXFS),
200	IMX_PINCTRL_PIN(MX1_PAD_SSI_TXCLK),
201	IMX_PINCTRL_PIN(MX1_PAD_UART1_CTS),
202	IMX_PINCTRL_PIN(MX1_PAD_UART1_RTS),
203	IMX_PINCTRL_PIN(MX1_PAD_UART1_TXD),
204	IMX_PINCTRL_PIN(MX1_PAD_UART1_RXD),
205	IMX_PINCTRL_PIN(MX1_PAD_SPI1_RDY),
206	IMX_PINCTRL_PIN(MX1_PAD_SPI1_SCLK),
207	IMX_PINCTRL_PIN(MX1_PAD_SPI1_SS),
208	IMX_PINCTRL_PIN(MX1_PAD_SPI1_MISO),
209	IMX_PINCTRL_PIN(MX1_PAD_SPI1_MOSI),
210	IMX_PINCTRL_PIN(MX1_PAD_BT13),
211	IMX_PINCTRL_PIN(MX1_PAD_BT12),
212	IMX_PINCTRL_PIN(MX1_PAD_BT11),
213	IMX_PINCTRL_PIN(MX1_PAD_BT10),
214	IMX_PINCTRL_PIN(MX1_PAD_BT9),
215	IMX_PINCTRL_PIN(MX1_PAD_BT8),
216	IMX_PINCTRL_PIN(MX1_PAD_BT7),
217	IMX_PINCTRL_PIN(MX1_PAD_BT6),
218	IMX_PINCTRL_PIN(MX1_PAD_BT5),
219	IMX_PINCTRL_PIN(MX1_PAD_BT4),
220	IMX_PINCTRL_PIN(MX1_PAD_BT3),
221	IMX_PINCTRL_PIN(MX1_PAD_BT2),
222	IMX_PINCTRL_PIN(MX1_PAD_BT1),
223	IMX_PINCTRL_PIN(MX1_PAD_LSCLK),
224	IMX_PINCTRL_PIN(MX1_PAD_REV),
225	IMX_PINCTRL_PIN(MX1_PAD_CLS),
226	IMX_PINCTRL_PIN(MX1_PAD_PS),
227	IMX_PINCTRL_PIN(MX1_PAD_SPL_SPR),
228	IMX_PINCTRL_PIN(MX1_PAD_CONTRAST),
229	IMX_PINCTRL_PIN(MX1_PAD_ACD_OE),
230	IMX_PINCTRL_PIN(MX1_PAD_LP_HSYNC),
231	IMX_PINCTRL_PIN(MX1_PAD_FLM_VSYNC),
232	IMX_PINCTRL_PIN(MX1_PAD_LD0),
233	IMX_PINCTRL_PIN(MX1_PAD_LD1),
234	IMX_PINCTRL_PIN(MX1_PAD_LD2),
235	IMX_PINCTRL_PIN(MX1_PAD_LD3),
236	IMX_PINCTRL_PIN(MX1_PAD_LD4),
237	IMX_PINCTRL_PIN(MX1_PAD_LD5),
238	IMX_PINCTRL_PIN(MX1_PAD_LD6),
239	IMX_PINCTRL_PIN(MX1_PAD_LD7),
240	IMX_PINCTRL_PIN(MX1_PAD_LD8),
241	IMX_PINCTRL_PIN(MX1_PAD_LD9),
242	IMX_PINCTRL_PIN(MX1_PAD_LD10),
243	IMX_PINCTRL_PIN(MX1_PAD_LD11),
244	IMX_PINCTRL_PIN(MX1_PAD_LD12),
245	IMX_PINCTRL_PIN(MX1_PAD_LD13),
246	IMX_PINCTRL_PIN(MX1_PAD_LD14),
247	IMX_PINCTRL_PIN(MX1_PAD_LD15),
248	IMX_PINCTRL_PIN(MX1_PAD_TMR2OUT),
249};
250
251static struct imx1_pinctrl_soc_info imx1_pinctrl_info = {
252	.pins	= imx1_pinctrl_pads,
253	.npins	= ARRAY_SIZE(imx1_pinctrl_pads),
254};
255
256static int __init imx1_pinctrl_probe(struct platform_device *pdev)
257{
258	return imx1_pinctrl_core_probe(pdev, &imx1_pinctrl_info);
259}
260
261static const struct of_device_id imx1_pinctrl_of_match[] = {
262	{ .compatible = "fsl,imx1-iomuxc", },
263	{ }
264};
265MODULE_DEVICE_TABLE(of, imx1_pinctrl_of_match);
266
267static struct platform_driver imx1_pinctrl_driver = {
268	.driver	= {
269		.name		= "imx1-pinctrl",
270		.of_match_table	= imx1_pinctrl_of_match,
271	},
272	.remove	= imx1_pinctrl_core_remove,
273};
274module_platform_driver_probe(imx1_pinctrl_driver, imx1_pinctrl_probe);
275
276MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
277MODULE_DESCRIPTION("Freescale i.MX1 pinctrl driver");
278MODULE_LICENSE("GPL");
279