1/* 2 * twl4030_usb - TWL4030 USB transceiver, talking to OMAP OTG controller 3 * 4 * Copyright (C) 2004-2007 Texas Instruments 5 * Copyright (C) 2008 Nokia Corporation 6 * Contact: Felipe Balbi <felipe.balbi@nokia.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 * 22 * Current status: 23 * - HS USB ULPI mode works. 24 * - 3-pin mode support may be added in future. 25 */ 26 27#include <linux/module.h> 28#include <linux/init.h> 29#include <linux/interrupt.h> 30#include <linux/platform_device.h> 31#include <linux/workqueue.h> 32#include <linux/io.h> 33#include <linux/delay.h> 34#include <linux/usb/otg.h> 35#include <linux/phy/phy.h> 36#include <linux/pm_runtime.h> 37#include <linux/usb/musb-omap.h> 38#include <linux/usb/ulpi.h> 39#include <linux/i2c/twl.h> 40#include <linux/regulator/consumer.h> 41#include <linux/err.h> 42#include <linux/slab.h> 43 44/* Register defines */ 45 46#define MCPC_CTRL 0x30 47#define MCPC_CTRL_RTSOL (1 << 7) 48#define MCPC_CTRL_EXTSWR (1 << 6) 49#define MCPC_CTRL_EXTSWC (1 << 5) 50#define MCPC_CTRL_VOICESW (1 << 4) 51#define MCPC_CTRL_OUT64K (1 << 3) 52#define MCPC_CTRL_RTSCTSSW (1 << 2) 53#define MCPC_CTRL_HS_UART (1 << 0) 54 55#define MCPC_IO_CTRL 0x33 56#define MCPC_IO_CTRL_MICBIASEN (1 << 5) 57#define MCPC_IO_CTRL_CTS_NPU (1 << 4) 58#define MCPC_IO_CTRL_RXD_PU (1 << 3) 59#define MCPC_IO_CTRL_TXDTYP (1 << 2) 60#define MCPC_IO_CTRL_CTSTYP (1 << 1) 61#define MCPC_IO_CTRL_RTSTYP (1 << 0) 62 63#define MCPC_CTRL2 0x36 64#define MCPC_CTRL2_MCPC_CK_EN (1 << 0) 65 66#define OTHER_FUNC_CTRL 0x80 67#define OTHER_FUNC_CTRL_BDIS_ACON_EN (1 << 4) 68#define OTHER_FUNC_CTRL_FIVEWIRE_MODE (1 << 2) 69 70#define OTHER_IFC_CTRL 0x83 71#define OTHER_IFC_CTRL_OE_INT_EN (1 << 6) 72#define OTHER_IFC_CTRL_CEA2011_MODE (1 << 5) 73#define OTHER_IFC_CTRL_FSLSSERIALMODE_4PIN (1 << 4) 74#define OTHER_IFC_CTRL_HIZ_ULPI_60MHZ_OUT (1 << 3) 75#define OTHER_IFC_CTRL_HIZ_ULPI (1 << 2) 76#define OTHER_IFC_CTRL_ALT_INT_REROUTE (1 << 0) 77 78#define OTHER_INT_EN_RISE 0x86 79#define OTHER_INT_EN_FALL 0x89 80#define OTHER_INT_STS 0x8C 81#define OTHER_INT_LATCH 0x8D 82#define OTHER_INT_VB_SESS_VLD (1 << 7) 83#define OTHER_INT_DM_HI (1 << 6) /* not valid for "latch" reg */ 84#define OTHER_INT_DP_HI (1 << 5) /* not valid for "latch" reg */ 85#define OTHER_INT_BDIS_ACON (1 << 3) /* not valid for "fall" regs */ 86#define OTHER_INT_MANU (1 << 1) 87#define OTHER_INT_ABNORMAL_STRESS (1 << 0) 88 89#define ID_STATUS 0x96 90#define ID_RES_FLOAT (1 << 4) 91#define ID_RES_440K (1 << 3) 92#define ID_RES_200K (1 << 2) 93#define ID_RES_102K (1 << 1) 94#define ID_RES_GND (1 << 0) 95 96#define POWER_CTRL 0xAC 97#define POWER_CTRL_OTG_ENAB (1 << 5) 98 99#define OTHER_IFC_CTRL2 0xAF 100#define OTHER_IFC_CTRL2_ULPI_STP_LOW (1 << 4) 101#define OTHER_IFC_CTRL2_ULPI_TXEN_POL (1 << 3) 102#define OTHER_IFC_CTRL2_ULPI_4PIN_2430 (1 << 2) 103#define OTHER_IFC_CTRL2_USB_INT_OUTSEL_MASK (3 << 0) /* bits 0 and 1 */ 104#define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT1N (0 << 0) 105#define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT2N (1 << 0) 106 107#define REG_CTRL_EN 0xB2 108#define REG_CTRL_ERROR 0xB5 109#define ULPI_I2C_CONFLICT_INTEN (1 << 0) 110 111#define OTHER_FUNC_CTRL2 0xB8 112#define OTHER_FUNC_CTRL2_VBAT_TIMER_EN (1 << 0) 113 114/* following registers do not have separate _clr and _set registers */ 115#define VBUS_DEBOUNCE 0xC0 116#define ID_DEBOUNCE 0xC1 117#define VBAT_TIMER 0xD3 118#define PHY_PWR_CTRL 0xFD 119#define PHY_PWR_PHYPWD (1 << 0) 120#define PHY_CLK_CTRL 0xFE 121#define PHY_CLK_CTRL_CLOCKGATING_EN (1 << 2) 122#define PHY_CLK_CTRL_CLK32K_EN (1 << 1) 123#define REQ_PHY_DPLL_CLK (1 << 0) 124#define PHY_CLK_CTRL_STS 0xFF 125#define PHY_DPLL_CLK (1 << 0) 126 127/* In module TWL_MODULE_PM_MASTER */ 128#define STS_HW_CONDITIONS 0x0F 129 130/* In module TWL_MODULE_PM_RECEIVER */ 131#define VUSB_DEDICATED1 0x7D 132#define VUSB_DEDICATED2 0x7E 133#define VUSB1V5_DEV_GRP 0x71 134#define VUSB1V5_TYPE 0x72 135#define VUSB1V5_REMAP 0x73 136#define VUSB1V8_DEV_GRP 0x74 137#define VUSB1V8_TYPE 0x75 138#define VUSB1V8_REMAP 0x76 139#define VUSB3V1_DEV_GRP 0x77 140#define VUSB3V1_TYPE 0x78 141#define VUSB3V1_REMAP 0x79 142 143/* In module TWL4030_MODULE_INTBR */ 144#define PMBR1 0x0D 145#define GPIO_USB_4PIN_ULPI_2430C (3 << 0) 146 147/* 148 * If VBUS is valid or ID is ground, then we know a 149 * cable is present and we need to be runtime-enabled 150 */ 151static inline bool cable_present(enum omap_musb_vbus_id_status stat) 152{ 153 return stat == OMAP_MUSB_VBUS_VALID || 154 stat == OMAP_MUSB_ID_GROUND; 155} 156 157struct twl4030_usb { 158 struct usb_phy phy; 159 struct device *dev; 160 161 /* TWL4030 internal USB regulator supplies */ 162 struct regulator *usb1v5; 163 struct regulator *usb1v8; 164 struct regulator *usb3v1; 165 166 /* for vbus reporting with irqs disabled */ 167 struct mutex lock; 168 169 /* pin configuration */ 170 enum twl4030_usb_mode usb_mode; 171 172 int irq; 173 enum omap_musb_vbus_id_status linkstat; 174 bool vbus_supplied; 175 176 struct delayed_work id_workaround_work; 177}; 178 179/* internal define on top of container_of */ 180#define phy_to_twl(x) container_of((x), struct twl4030_usb, phy) 181 182/*-------------------------------------------------------------------------*/ 183 184static int twl4030_i2c_write_u8_verify(struct twl4030_usb *twl, 185 u8 module, u8 data, u8 address) 186{ 187 u8 check; 188 189 if ((twl_i2c_write_u8(module, data, address) >= 0) && 190 (twl_i2c_read_u8(module, &check, address) >= 0) && 191 (check == data)) 192 return 0; 193 dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n", 194 1, module, address, check, data); 195 196 /* Failed once: Try again */ 197 if ((twl_i2c_write_u8(module, data, address) >= 0) && 198 (twl_i2c_read_u8(module, &check, address) >= 0) && 199 (check == data)) 200 return 0; 201 dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n", 202 2, module, address, check, data); 203 204 /* Failed again: Return error */ 205 return -EBUSY; 206} 207 208#define twl4030_usb_write_verify(twl, address, data) \ 209 twl4030_i2c_write_u8_verify(twl, TWL_MODULE_USB, (data), (address)) 210 211static inline int twl4030_usb_write(struct twl4030_usb *twl, 212 u8 address, u8 data) 213{ 214 int ret = 0; 215 216 ret = twl_i2c_write_u8(TWL_MODULE_USB, data, address); 217 if (ret < 0) 218 dev_dbg(twl->dev, 219 "TWL4030:USB:Write[0x%x] Error %d\n", address, ret); 220 return ret; 221} 222 223static inline int twl4030_readb(struct twl4030_usb *twl, u8 module, u8 address) 224{ 225 u8 data; 226 int ret = 0; 227 228 ret = twl_i2c_read_u8(module, &data, address); 229 if (ret >= 0) 230 ret = data; 231 else 232 dev_dbg(twl->dev, 233 "TWL4030:readb[0x%x,0x%x] Error %d\n", 234 module, address, ret); 235 236 return ret; 237} 238 239static inline int twl4030_usb_read(struct twl4030_usb *twl, u8 address) 240{ 241 return twl4030_readb(twl, TWL_MODULE_USB, address); 242} 243 244/*-------------------------------------------------------------------------*/ 245 246static inline int 247twl4030_usb_set_bits(struct twl4030_usb *twl, u8 reg, u8 bits) 248{ 249 return twl4030_usb_write(twl, ULPI_SET(reg), bits); 250} 251 252static inline int 253twl4030_usb_clear_bits(struct twl4030_usb *twl, u8 reg, u8 bits) 254{ 255 return twl4030_usb_write(twl, ULPI_CLR(reg), bits); 256} 257 258/*-------------------------------------------------------------------------*/ 259 260static bool twl4030_is_driving_vbus(struct twl4030_usb *twl) 261{ 262 int ret; 263 264 ret = twl4030_usb_read(twl, PHY_CLK_CTRL_STS); 265 if (ret < 0 || !(ret & PHY_DPLL_CLK)) 266 /* 267 * if clocks are off, registers are not updated, 268 * but we can assume we don't drive VBUS in this case 269 */ 270 return false; 271 272 ret = twl4030_usb_read(twl, ULPI_OTG_CTRL); 273 if (ret < 0) 274 return false; 275 276 return (ret & (ULPI_OTG_DRVVBUS | ULPI_OTG_CHRGVBUS)) ? true : false; 277} 278 279static enum omap_musb_vbus_id_status 280 twl4030_usb_linkstat(struct twl4030_usb *twl) 281{ 282 int status; 283 enum omap_musb_vbus_id_status linkstat = OMAP_MUSB_UNKNOWN; 284 285 twl->vbus_supplied = false; 286 287 /* 288 * For ID/VBUS sensing, see manual section 15.4.8 ... 289 * except when using only battery backup power, two 290 * comparators produce VBUS_PRES and ID_PRES signals, 291 * which don't match docs elsewhere. But ... BIT(7) 292 * and BIT(2) of STS_HW_CONDITIONS, respectively, do 293 * seem to match up. If either is true the USB_PRES 294 * signal is active, the OTG module is activated, and 295 * its interrupt may be raised (may wake the system). 296 */ 297 status = twl4030_readb(twl, TWL_MODULE_PM_MASTER, STS_HW_CONDITIONS); 298 if (status < 0) 299 dev_err(twl->dev, "USB link status err %d\n", status); 300 else if (status & (BIT(7) | BIT(2))) { 301 if (status & BIT(7)) { 302 if (twl4030_is_driving_vbus(twl)) 303 status &= ~BIT(7); 304 else 305 twl->vbus_supplied = true; 306 } 307 308 if (status & BIT(2)) 309 linkstat = OMAP_MUSB_ID_GROUND; 310 else if (status & BIT(7)) 311 linkstat = OMAP_MUSB_VBUS_VALID; 312 else 313 linkstat = OMAP_MUSB_VBUS_OFF; 314 } else { 315 if (twl->linkstat != OMAP_MUSB_UNKNOWN) 316 linkstat = OMAP_MUSB_VBUS_OFF; 317 } 318 319 dev_dbg(twl->dev, "HW_CONDITIONS 0x%02x/%d; link %d\n", 320 status, status, linkstat); 321 322 /* REVISIT this assumes host and peripheral controllers 323 * are registered, and that both are active... 324 */ 325 326 return linkstat; 327} 328 329static void twl4030_usb_set_mode(struct twl4030_usb *twl, int mode) 330{ 331 twl->usb_mode = mode; 332 333 switch (mode) { 334 case T2_USB_MODE_ULPI: 335 twl4030_usb_clear_bits(twl, ULPI_IFC_CTRL, 336 ULPI_IFC_CTRL_CARKITMODE); 337 twl4030_usb_set_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB); 338 twl4030_usb_clear_bits(twl, ULPI_FUNC_CTRL, 339 ULPI_FUNC_CTRL_XCVRSEL_MASK | 340 ULPI_FUNC_CTRL_OPMODE_MASK); 341 break; 342 case -1: 343 /* FIXME: power on defaults */ 344 break; 345 default: 346 dev_err(twl->dev, "unsupported T2 transceiver mode %d\n", 347 mode); 348 break; 349 } 350} 351 352static void twl4030_i2c_access(struct twl4030_usb *twl, int on) 353{ 354 unsigned long timeout; 355 int val = twl4030_usb_read(twl, PHY_CLK_CTRL); 356 357 if (val >= 0) { 358 if (on) { 359 /* enable DPLL to access PHY registers over I2C */ 360 val |= REQ_PHY_DPLL_CLK; 361 WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL, 362 (u8)val) < 0); 363 364 timeout = jiffies + HZ; 365 while (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) & 366 PHY_DPLL_CLK) 367 && time_before(jiffies, timeout)) 368 udelay(10); 369 if (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) & 370 PHY_DPLL_CLK)) 371 dev_err(twl->dev, "Timeout setting T2 HSUSB " 372 "PHY DPLL clock\n"); 373 } else { 374 /* let ULPI control the DPLL clock */ 375 val &= ~REQ_PHY_DPLL_CLK; 376 WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL, 377 (u8)val) < 0); 378 } 379 } 380} 381 382static void __twl4030_phy_power(struct twl4030_usb *twl, int on) 383{ 384 u8 pwr = twl4030_usb_read(twl, PHY_PWR_CTRL); 385 386 if (on) 387 pwr &= ~PHY_PWR_PHYPWD; 388 else 389 pwr |= PHY_PWR_PHYPWD; 390 391 WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0); 392} 393 394static int twl4030_usb_runtime_suspend(struct device *dev) 395{ 396 struct twl4030_usb *twl = dev_get_drvdata(dev); 397 398 dev_dbg(twl->dev, "%s\n", __func__); 399 if (pm_runtime_suspended(dev)) 400 return 0; 401 402 __twl4030_phy_power(twl, 0); 403 regulator_disable(twl->usb1v5); 404 regulator_disable(twl->usb1v8); 405 regulator_disable(twl->usb3v1); 406 407 return 0; 408} 409 410static int twl4030_usb_runtime_resume(struct device *dev) 411{ 412 struct twl4030_usb *twl = dev_get_drvdata(dev); 413 int res; 414 415 dev_dbg(twl->dev, "%s\n", __func__); 416 if (pm_runtime_active(dev)) 417 return 0; 418 419 res = regulator_enable(twl->usb3v1); 420 if (res) 421 dev_err(twl->dev, "Failed to enable usb3v1\n"); 422 423 res = regulator_enable(twl->usb1v8); 424 if (res) 425 dev_err(twl->dev, "Failed to enable usb1v8\n"); 426 427 /* 428 * Disabling usb3v1 regulator (= writing 0 to VUSB3V1_DEV_GRP 429 * in twl4030) resets the VUSB_DEDICATED2 register. This reset 430 * enables VUSB3V1_SLEEP bit that remaps usb3v1 ACTIVE state to 431 * SLEEP. We work around this by clearing the bit after usv3v1 432 * is re-activated. This ensures that VUSB3V1 is really active. 433 */ 434 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2); 435 436 res = regulator_enable(twl->usb1v5); 437 if (res) 438 dev_err(twl->dev, "Failed to enable usb1v5\n"); 439 440 __twl4030_phy_power(twl, 1); 441 twl4030_usb_write(twl, PHY_CLK_CTRL, 442 twl4030_usb_read(twl, PHY_CLK_CTRL) | 443 (PHY_CLK_CTRL_CLOCKGATING_EN | 444 PHY_CLK_CTRL_CLK32K_EN)); 445 446 return 0; 447} 448 449static int twl4030_phy_power_off(struct phy *phy) 450{ 451 struct twl4030_usb *twl = phy_get_drvdata(phy); 452 453 dev_dbg(twl->dev, "%s\n", __func__); 454 pm_runtime_mark_last_busy(twl->dev); 455 pm_runtime_put_autosuspend(twl->dev); 456 457 return 0; 458} 459 460static int twl4030_phy_power_on(struct phy *phy) 461{ 462 struct twl4030_usb *twl = phy_get_drvdata(phy); 463 464 dev_dbg(twl->dev, "%s\n", __func__); 465 pm_runtime_get_sync(twl->dev); 466 twl4030_i2c_access(twl, 1); 467 twl4030_usb_set_mode(twl, twl->usb_mode); 468 if (twl->usb_mode == T2_USB_MODE_ULPI) 469 twl4030_i2c_access(twl, 0); 470 schedule_delayed_work(&twl->id_workaround_work, 0); 471 472 return 0; 473} 474 475static int twl4030_usb_ldo_init(struct twl4030_usb *twl) 476{ 477 /* Enable writing to power configuration registers */ 478 twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1, 479 TWL4030_PM_MASTER_PROTECT_KEY); 480 481 twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2, 482 TWL4030_PM_MASTER_PROTECT_KEY); 483 484 /* Keep VUSB3V1 LDO in sleep state until VBUS/ID change detected*/ 485 /*twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);*/ 486 487 /* input to VUSB3V1 LDO is from VBAT, not VBUS */ 488 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0x14, VUSB_DEDICATED1); 489 490 /* Initialize 3.1V regulator */ 491 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_DEV_GRP); 492 493 twl->usb3v1 = devm_regulator_get(twl->dev, "usb3v1"); 494 if (IS_ERR(twl->usb3v1)) 495 return -ENODEV; 496 497 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_TYPE); 498 499 /* Initialize 1.5V regulator */ 500 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_DEV_GRP); 501 502 twl->usb1v5 = devm_regulator_get(twl->dev, "usb1v5"); 503 if (IS_ERR(twl->usb1v5)) 504 return -ENODEV; 505 506 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_TYPE); 507 508 /* Initialize 1.8V regulator */ 509 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_DEV_GRP); 510 511 twl->usb1v8 = devm_regulator_get(twl->dev, "usb1v8"); 512 if (IS_ERR(twl->usb1v8)) 513 return -ENODEV; 514 515 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_TYPE); 516 517 /* disable access to power configuration registers */ 518 twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0, 519 TWL4030_PM_MASTER_PROTECT_KEY); 520 521 return 0; 522} 523 524static ssize_t twl4030_usb_vbus_show(struct device *dev, 525 struct device_attribute *attr, char *buf) 526{ 527 struct twl4030_usb *twl = dev_get_drvdata(dev); 528 int ret = -EINVAL; 529 530 mutex_lock(&twl->lock); 531 ret = sprintf(buf, "%s\n", 532 twl->vbus_supplied ? "on" : "off"); 533 mutex_unlock(&twl->lock); 534 535 return ret; 536} 537static DEVICE_ATTR(vbus, 0444, twl4030_usb_vbus_show, NULL); 538 539static irqreturn_t twl4030_usb_irq(int irq, void *_twl) 540{ 541 struct twl4030_usb *twl = _twl; 542 enum omap_musb_vbus_id_status status; 543 bool status_changed = false; 544 545 status = twl4030_usb_linkstat(twl); 546 547 mutex_lock(&twl->lock); 548 if (status >= 0 && status != twl->linkstat) { 549 status_changed = 550 cable_present(twl->linkstat) != 551 cable_present(status); 552 twl->linkstat = status; 553 } 554 mutex_unlock(&twl->lock); 555 556 if (status_changed) { 557 /* FIXME add a set_power() method so that B-devices can 558 * configure the charger appropriately. It's not always 559 * correct to consume VBUS power, and how much current to 560 * consume is a function of the USB configuration chosen 561 * by the host. 562 * 563 * REVISIT usb_gadget_vbus_connect(...) as needed, ditto 564 * its disconnect() sibling, when changing to/from the 565 * USB_LINK_VBUS state. musb_hdrc won't care until it 566 * starts to handle softconnect right. 567 */ 568 if (cable_present(status)) { 569 pm_runtime_get_sync(twl->dev); 570 } else { 571 pm_runtime_mark_last_busy(twl->dev); 572 pm_runtime_put_autosuspend(twl->dev); 573 } 574 omap_musb_mailbox(status); 575 } 576 577 /* don't schedule during sleep - irq works right then */ 578 if (status == OMAP_MUSB_ID_GROUND && pm_runtime_active(twl->dev)) { 579 cancel_delayed_work(&twl->id_workaround_work); 580 schedule_delayed_work(&twl->id_workaround_work, HZ); 581 } 582 583 if (irq) 584 sysfs_notify(&twl->dev->kobj, NULL, "vbus"); 585 586 return IRQ_HANDLED; 587} 588 589static void twl4030_id_workaround_work(struct work_struct *work) 590{ 591 struct twl4030_usb *twl = container_of(work, struct twl4030_usb, 592 id_workaround_work.work); 593 594 twl4030_usb_irq(0, twl); 595} 596 597static int twl4030_phy_init(struct phy *phy) 598{ 599 struct twl4030_usb *twl = phy_get_drvdata(phy); 600 601 pm_runtime_get_sync(twl->dev); 602 schedule_delayed_work(&twl->id_workaround_work, 0); 603 pm_runtime_mark_last_busy(twl->dev); 604 pm_runtime_put_autosuspend(twl->dev); 605 606 return 0; 607} 608 609static int twl4030_set_peripheral(struct usb_otg *otg, 610 struct usb_gadget *gadget) 611{ 612 if (!otg) 613 return -ENODEV; 614 615 otg->gadget = gadget; 616 if (!gadget) 617 otg->state = OTG_STATE_UNDEFINED; 618 619 return 0; 620} 621 622static int twl4030_set_host(struct usb_otg *otg, struct usb_bus *host) 623{ 624 if (!otg) 625 return -ENODEV; 626 627 otg->host = host; 628 if (!host) 629 otg->state = OTG_STATE_UNDEFINED; 630 631 return 0; 632} 633 634static const struct phy_ops ops = { 635 .init = twl4030_phy_init, 636 .power_on = twl4030_phy_power_on, 637 .power_off = twl4030_phy_power_off, 638 .owner = THIS_MODULE, 639}; 640 641static const struct dev_pm_ops twl4030_usb_pm_ops = { 642 SET_RUNTIME_PM_OPS(twl4030_usb_runtime_suspend, 643 twl4030_usb_runtime_resume, NULL) 644}; 645 646static int twl4030_usb_probe(struct platform_device *pdev) 647{ 648 struct twl4030_usb_data *pdata = dev_get_platdata(&pdev->dev); 649 struct twl4030_usb *twl; 650 struct phy *phy; 651 int status, err; 652 struct usb_otg *otg; 653 struct device_node *np = pdev->dev.of_node; 654 struct phy_provider *phy_provider; 655 656 twl = devm_kzalloc(&pdev->dev, sizeof(*twl), GFP_KERNEL); 657 if (!twl) 658 return -ENOMEM; 659 660 if (np) 661 of_property_read_u32(np, "usb_mode", 662 (enum twl4030_usb_mode *)&twl->usb_mode); 663 else if (pdata) { 664 twl->usb_mode = pdata->usb_mode; 665 } else { 666 dev_err(&pdev->dev, "twl4030 initialized without pdata\n"); 667 return -EINVAL; 668 } 669 670 otg = devm_kzalloc(&pdev->dev, sizeof(*otg), GFP_KERNEL); 671 if (!otg) 672 return -ENOMEM; 673 674 twl->dev = &pdev->dev; 675 twl->irq = platform_get_irq(pdev, 0); 676 twl->vbus_supplied = false; 677 twl->linkstat = OMAP_MUSB_UNKNOWN; 678 679 twl->phy.dev = twl->dev; 680 twl->phy.label = "twl4030"; 681 twl->phy.otg = otg; 682 twl->phy.type = USB_PHY_TYPE_USB2; 683 684 otg->usb_phy = &twl->phy; 685 otg->set_host = twl4030_set_host; 686 otg->set_peripheral = twl4030_set_peripheral; 687 688 phy = devm_phy_create(twl->dev, NULL, &ops); 689 if (IS_ERR(phy)) { 690 dev_dbg(&pdev->dev, "Failed to create PHY\n"); 691 return PTR_ERR(phy); 692 } 693 694 phy_set_drvdata(phy, twl); 695 696 phy_provider = devm_of_phy_provider_register(twl->dev, 697 of_phy_simple_xlate); 698 if (IS_ERR(phy_provider)) 699 return PTR_ERR(phy_provider); 700 701 /* init mutex for workqueue */ 702 mutex_init(&twl->lock); 703 704 INIT_DELAYED_WORK(&twl->id_workaround_work, twl4030_id_workaround_work); 705 706 err = twl4030_usb_ldo_init(twl); 707 if (err) { 708 dev_err(&pdev->dev, "ldo init failed\n"); 709 return err; 710 } 711 usb_add_phy_dev(&twl->phy); 712 713 platform_set_drvdata(pdev, twl); 714 if (device_create_file(&pdev->dev, &dev_attr_vbus)) 715 dev_warn(&pdev->dev, "could not create sysfs file\n"); 716 717 ATOMIC_INIT_NOTIFIER_HEAD(&twl->phy.notifier); 718 719 pm_runtime_use_autosuspend(&pdev->dev); 720 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000); 721 pm_runtime_enable(&pdev->dev); 722 pm_runtime_get_sync(&pdev->dev); 723 724 /* Our job is to use irqs and status from the power module 725 * to keep the transceiver disabled when nothing's connected. 726 * 727 * FIXME we actually shouldn't start enabling it until the 728 * USB controller drivers have said they're ready, by calling 729 * set_host() and/or set_peripheral() ... OTG_capable boards 730 * need both handles, otherwise just one suffices. 731 */ 732 status = devm_request_threaded_irq(twl->dev, twl->irq, NULL, 733 twl4030_usb_irq, IRQF_TRIGGER_FALLING | 734 IRQF_TRIGGER_RISING | IRQF_ONESHOT, "twl4030_usb", twl); 735 if (status < 0) { 736 dev_dbg(&pdev->dev, "can't get IRQ %d, err %d\n", 737 twl->irq, status); 738 return status; 739 } 740 741 if (pdata) 742 err = phy_create_lookup(phy, "usb", "musb-hdrc.0"); 743 if (err) 744 return err; 745 746 pm_runtime_mark_last_busy(&pdev->dev); 747 pm_runtime_put_autosuspend(twl->dev); 748 749 dev_info(&pdev->dev, "Initialized TWL4030 USB module\n"); 750 return 0; 751} 752 753static int twl4030_usb_remove(struct platform_device *pdev) 754{ 755 struct twl4030_usb *twl = platform_get_drvdata(pdev); 756 int val; 757 758 usb_remove_phy(&twl->phy); 759 pm_runtime_get_sync(twl->dev); 760 cancel_delayed_work(&twl->id_workaround_work); 761 device_remove_file(twl->dev, &dev_attr_vbus); 762 763 /* set transceiver mode to power on defaults */ 764 twl4030_usb_set_mode(twl, -1); 765 766 /* idle ulpi before powering off */ 767 if (cable_present(twl->linkstat)) 768 pm_runtime_put_noidle(twl->dev); 769 pm_runtime_mark_last_busy(twl->dev); 770 pm_runtime_put_sync_suspend(twl->dev); 771 pm_runtime_disable(twl->dev); 772 773 /* autogate 60MHz ULPI clock, 774 * clear dpll clock request for i2c access, 775 * disable 32KHz 776 */ 777 val = twl4030_usb_read(twl, PHY_CLK_CTRL); 778 if (val >= 0) { 779 val |= PHY_CLK_CTRL_CLOCKGATING_EN; 780 val &= ~(PHY_CLK_CTRL_CLK32K_EN | REQ_PHY_DPLL_CLK); 781 twl4030_usb_write(twl, PHY_CLK_CTRL, (u8)val); 782 } 783 784 /* disable complete OTG block */ 785 twl4030_usb_clear_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB); 786 787 return 0; 788} 789 790#ifdef CONFIG_OF 791static const struct of_device_id twl4030_usb_id_table[] = { 792 { .compatible = "ti,twl4030-usb" }, 793 {} 794}; 795MODULE_DEVICE_TABLE(of, twl4030_usb_id_table); 796#endif 797 798static struct platform_driver twl4030_usb_driver = { 799 .probe = twl4030_usb_probe, 800 .remove = twl4030_usb_remove, 801 .driver = { 802 .name = "twl4030_usb", 803 .pm = &twl4030_usb_pm_ops, 804 .of_match_table = of_match_ptr(twl4030_usb_id_table), 805 }, 806}; 807 808static int __init twl4030_usb_init(void) 809{ 810 return platform_driver_register(&twl4030_usb_driver); 811} 812subsys_initcall(twl4030_usb_init); 813 814static void __exit twl4030_usb_exit(void) 815{ 816 platform_driver_unregister(&twl4030_usb_driver); 817} 818module_exit(twl4030_usb_exit); 819 820MODULE_ALIAS("platform:twl4030_usb"); 821MODULE_AUTHOR("Texas Instruments, Inc, Nokia Corporation"); 822MODULE_DESCRIPTION("TWL4030 USB transceiver driver"); 823MODULE_LICENSE("GPL"); 824