1 /*
2 * Synopsys Designware PCIe host controller driver
3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Author: Jingoo Han <jg1.han@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/msi.h>
19 #include <linux/of_address.h>
20 #include <linux/of_pci.h>
21 #include <linux/pci.h>
22 #include <linux/pci_regs.h>
23 #include <linux/platform_device.h>
24 #include <linux/types.h>
25
26 #include "pcie-designware.h"
27
28 /* Synopsis specific PCIE configuration registers */
29 #define PCIE_PORT_LINK_CONTROL 0x710
30 #define PORT_LINK_MODE_MASK (0x3f << 16)
31 #define PORT_LINK_MODE_1_LANES (0x1 << 16)
32 #define PORT_LINK_MODE_2_LANES (0x3 << 16)
33 #define PORT_LINK_MODE_4_LANES (0x7 << 16)
34
35 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
36 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
37 #define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8)
38 #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
39 #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
40 #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
41
42 #define PCIE_MSI_ADDR_LO 0x820
43 #define PCIE_MSI_ADDR_HI 0x824
44 #define PCIE_MSI_INTR0_ENABLE 0x828
45 #define PCIE_MSI_INTR0_MASK 0x82C
46 #define PCIE_MSI_INTR0_STATUS 0x830
47
48 #define PCIE_ATU_VIEWPORT 0x900
49 #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
50 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
51 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
52 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
53 #define PCIE_ATU_CR1 0x904
54 #define PCIE_ATU_TYPE_MEM (0x0 << 0)
55 #define PCIE_ATU_TYPE_IO (0x2 << 0)
56 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
57 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
58 #define PCIE_ATU_CR2 0x908
59 #define PCIE_ATU_ENABLE (0x1 << 31)
60 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
61 #define PCIE_ATU_LOWER_BASE 0x90C
62 #define PCIE_ATU_UPPER_BASE 0x910
63 #define PCIE_ATU_LIMIT 0x914
64 #define PCIE_ATU_LOWER_TARGET 0x918
65 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
66 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
67 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
68 #define PCIE_ATU_UPPER_TARGET 0x91C
69
70 static struct hw_pci dw_pci;
71
72 static unsigned long global_io_offset;
73
sys_to_pcie(struct pci_sys_data * sys)74 static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
75 {
76 BUG_ON(!sys->private_data);
77
78 return sys->private_data;
79 }
80
dw_pcie_cfg_read(void __iomem * addr,int where,int size,u32 * val)81 int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
82 {
83 *val = readl(addr);
84
85 if (size == 1)
86 *val = (*val >> (8 * (where & 3))) & 0xff;
87 else if (size == 2)
88 *val = (*val >> (8 * (where & 3))) & 0xffff;
89 else if (size != 4)
90 return PCIBIOS_BAD_REGISTER_NUMBER;
91
92 return PCIBIOS_SUCCESSFUL;
93 }
94
dw_pcie_cfg_write(void __iomem * addr,int where,int size,u32 val)95 int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val)
96 {
97 if (size == 4)
98 writel(val, addr);
99 else if (size == 2)
100 writew(val, addr + (where & 2));
101 else if (size == 1)
102 writeb(val, addr + (where & 3));
103 else
104 return PCIBIOS_BAD_REGISTER_NUMBER;
105
106 return PCIBIOS_SUCCESSFUL;
107 }
108
dw_pcie_readl_rc(struct pcie_port * pp,u32 reg,u32 * val)109 static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val)
110 {
111 if (pp->ops->readl_rc)
112 pp->ops->readl_rc(pp, pp->dbi_base + reg, val);
113 else
114 *val = readl(pp->dbi_base + reg);
115 }
116
dw_pcie_writel_rc(struct pcie_port * pp,u32 val,u32 reg)117 static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg)
118 {
119 if (pp->ops->writel_rc)
120 pp->ops->writel_rc(pp, val, pp->dbi_base + reg);
121 else
122 writel(val, pp->dbi_base + reg);
123 }
124
dw_pcie_rd_own_conf(struct pcie_port * pp,int where,int size,u32 * val)125 static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
126 u32 *val)
127 {
128 int ret;
129
130 if (pp->ops->rd_own_conf)
131 ret = pp->ops->rd_own_conf(pp, where, size, val);
132 else
133 ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where,
134 size, val);
135
136 return ret;
137 }
138
dw_pcie_wr_own_conf(struct pcie_port * pp,int where,int size,u32 val)139 static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
140 u32 val)
141 {
142 int ret;
143
144 if (pp->ops->wr_own_conf)
145 ret = pp->ops->wr_own_conf(pp, where, size, val);
146 else
147 ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where,
148 size, val);
149
150 return ret;
151 }
152
153 static struct irq_chip dw_msi_irq_chip = {
154 .name = "PCI-MSI",
155 .irq_enable = pci_msi_unmask_irq,
156 .irq_disable = pci_msi_mask_irq,
157 .irq_mask = pci_msi_mask_irq,
158 .irq_unmask = pci_msi_unmask_irq,
159 };
160
161 /* MSI int handler */
dw_handle_msi_irq(struct pcie_port * pp)162 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
163 {
164 unsigned long val;
165 int i, pos, irq;
166 irqreturn_t ret = IRQ_NONE;
167
168 for (i = 0; i < MAX_MSI_CTRLS; i++) {
169 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
170 (u32 *)&val);
171 if (val) {
172 ret = IRQ_HANDLED;
173 pos = 0;
174 while ((pos = find_next_bit(&val, 32, pos)) != 32) {
175 irq = irq_find_mapping(pp->irq_domain,
176 i * 32 + pos);
177 dw_pcie_wr_own_conf(pp,
178 PCIE_MSI_INTR0_STATUS + i * 12,
179 4, 1 << pos);
180 generic_handle_irq(irq);
181 pos++;
182 }
183 }
184 }
185
186 return ret;
187 }
188
dw_pcie_msi_init(struct pcie_port * pp)189 void dw_pcie_msi_init(struct pcie_port *pp)
190 {
191 pp->msi_data = __get_free_pages(GFP_KERNEL, 0);
192
193 /* program the msi_data */
194 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
195 virt_to_phys((void *)pp->msi_data));
196 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0);
197 }
198
dw_pcie_msi_clear_irq(struct pcie_port * pp,int irq)199 static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
200 {
201 unsigned int res, bit, val;
202
203 res = (irq / 32) * 12;
204 bit = irq % 32;
205 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
206 val &= ~(1 << bit);
207 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
208 }
209
clear_irq_range(struct pcie_port * pp,unsigned int irq_base,unsigned int nvec,unsigned int pos)210 static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
211 unsigned int nvec, unsigned int pos)
212 {
213 unsigned int i;
214
215 for (i = 0; i < nvec; i++) {
216 irq_set_msi_desc_off(irq_base, i, NULL);
217 /* Disable corresponding interrupt on MSI controller */
218 if (pp->ops->msi_clear_irq)
219 pp->ops->msi_clear_irq(pp, pos + i);
220 else
221 dw_pcie_msi_clear_irq(pp, pos + i);
222 }
223
224 bitmap_release_region(pp->msi_irq_in_use, pos, order_base_2(nvec));
225 }
226
dw_pcie_msi_set_irq(struct pcie_port * pp,int irq)227 static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
228 {
229 unsigned int res, bit, val;
230
231 res = (irq / 32) * 12;
232 bit = irq % 32;
233 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
234 val |= 1 << bit;
235 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
236 }
237
assign_irq(int no_irqs,struct msi_desc * desc,int * pos)238 static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
239 {
240 int irq, pos0, i;
241 struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata);
242
243 pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS,
244 order_base_2(no_irqs));
245 if (pos0 < 0)
246 goto no_valid_irq;
247
248 irq = irq_find_mapping(pp->irq_domain, pos0);
249 if (!irq)
250 goto no_valid_irq;
251
252 /*
253 * irq_create_mapping (called from dw_pcie_host_init) pre-allocates
254 * descs so there is no need to allocate descs here. We can therefore
255 * assume that if irq_find_mapping above returns non-zero, then the
256 * descs are also successfully allocated.
257 */
258
259 for (i = 0; i < no_irqs; i++) {
260 if (irq_set_msi_desc_off(irq, i, desc) != 0) {
261 clear_irq_range(pp, irq, i, pos0);
262 goto no_valid_irq;
263 }
264 /*Enable corresponding interrupt in MSI interrupt controller */
265 if (pp->ops->msi_set_irq)
266 pp->ops->msi_set_irq(pp, pos0 + i);
267 else
268 dw_pcie_msi_set_irq(pp, pos0 + i);
269 }
270
271 *pos = pos0;
272 return irq;
273
274 no_valid_irq:
275 *pos = pos0;
276 return -ENOSPC;
277 }
278
dw_msi_setup_irq(struct msi_controller * chip,struct pci_dev * pdev,struct msi_desc * desc)279 static int dw_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
280 struct msi_desc *desc)
281 {
282 int irq, pos;
283 struct msi_msg msg;
284 struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata);
285
286 if (desc->msi_attrib.is_msix)
287 return -EINVAL;
288
289 irq = assign_irq(1, desc, &pos);
290 if (irq < 0)
291 return irq;
292
293 if (pp->ops->get_msi_addr)
294 msg.address_lo = pp->ops->get_msi_addr(pp);
295 else
296 msg.address_lo = virt_to_phys((void *)pp->msi_data);
297 msg.address_hi = 0x0;
298
299 if (pp->ops->get_msi_data)
300 msg.data = pp->ops->get_msi_data(pp, pos);
301 else
302 msg.data = pos;
303
304 pci_write_msi_msg(irq, &msg);
305
306 return 0;
307 }
308
dw_msi_teardown_irq(struct msi_controller * chip,unsigned int irq)309 static void dw_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
310 {
311 struct irq_data *data = irq_get_irq_data(irq);
312 struct msi_desc *msi = irq_data_get_msi(data);
313 struct pcie_port *pp = sys_to_pcie(msi->dev->bus->sysdata);
314
315 clear_irq_range(pp, irq, 1, data->hwirq);
316 }
317
318 static struct msi_controller dw_pcie_msi_chip = {
319 .setup_irq = dw_msi_setup_irq,
320 .teardown_irq = dw_msi_teardown_irq,
321 };
322
dw_pcie_link_up(struct pcie_port * pp)323 int dw_pcie_link_up(struct pcie_port *pp)
324 {
325 if (pp->ops->link_up)
326 return pp->ops->link_up(pp);
327 else
328 return 0;
329 }
330
dw_pcie_msi_map(struct irq_domain * domain,unsigned int irq,irq_hw_number_t hwirq)331 static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
332 irq_hw_number_t hwirq)
333 {
334 irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq);
335 irq_set_chip_data(irq, domain->host_data);
336 set_irq_flags(irq, IRQF_VALID);
337
338 return 0;
339 }
340
341 static const struct irq_domain_ops msi_domain_ops = {
342 .map = dw_pcie_msi_map,
343 };
344
dw_pcie_host_init(struct pcie_port * pp)345 int dw_pcie_host_init(struct pcie_port *pp)
346 {
347 struct device_node *np = pp->dev->of_node;
348 struct platform_device *pdev = to_platform_device(pp->dev);
349 struct of_pci_range range;
350 struct of_pci_range_parser parser;
351 struct resource *cfg_res;
352 u32 val, na, ns;
353 const __be32 *addrp;
354 int i, index, ret;
355
356 /* Find the address cell size and the number of cells in order to get
357 * the untranslated address.
358 */
359 of_property_read_u32(np, "#address-cells", &na);
360 ns = of_n_size_cells(np);
361
362 cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
363 if (cfg_res) {
364 pp->cfg0_size = resource_size(cfg_res)/2;
365 pp->cfg1_size = resource_size(cfg_res)/2;
366 pp->cfg0_base = cfg_res->start;
367 pp->cfg1_base = cfg_res->start + pp->cfg0_size;
368
369 /* Find the untranslated configuration space address */
370 index = of_property_match_string(np, "reg-names", "config");
371 addrp = of_get_address(np, index, NULL, NULL);
372 pp->cfg0_mod_base = of_read_number(addrp, ns);
373 pp->cfg1_mod_base = pp->cfg0_mod_base + pp->cfg0_size;
374 } else {
375 dev_err(pp->dev, "missing *config* reg space\n");
376 }
377
378 if (of_pci_range_parser_init(&parser, np)) {
379 dev_err(pp->dev, "missing ranges property\n");
380 return -EINVAL;
381 }
382
383 /* Get the I/O and memory ranges from DT */
384 for_each_of_pci_range(&parser, &range) {
385 unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
386
387 if (restype == IORESOURCE_IO) {
388 of_pci_range_to_resource(&range, np, &pp->io);
389 pp->io.name = "I/O";
390 pp->io.start = max_t(resource_size_t,
391 PCIBIOS_MIN_IO,
392 range.pci_addr + global_io_offset);
393 pp->io.end = min_t(resource_size_t,
394 IO_SPACE_LIMIT,
395 range.pci_addr + range.size
396 + global_io_offset - 1);
397 pp->io_size = resource_size(&pp->io);
398 pp->io_bus_addr = range.pci_addr;
399 pp->io_base = range.cpu_addr;
400
401 /* Find the untranslated IO space address */
402 pp->io_mod_base = of_read_number(parser.range -
403 parser.np + na, ns);
404 }
405 if (restype == IORESOURCE_MEM) {
406 of_pci_range_to_resource(&range, np, &pp->mem);
407 pp->mem.name = "MEM";
408 pp->mem_size = resource_size(&pp->mem);
409 pp->mem_bus_addr = range.pci_addr;
410
411 /* Find the untranslated MEM space address */
412 pp->mem_mod_base = of_read_number(parser.range -
413 parser.np + na, ns);
414 }
415 if (restype == 0) {
416 of_pci_range_to_resource(&range, np, &pp->cfg);
417 pp->cfg0_size = resource_size(&pp->cfg)/2;
418 pp->cfg1_size = resource_size(&pp->cfg)/2;
419 pp->cfg0_base = pp->cfg.start;
420 pp->cfg1_base = pp->cfg.start + pp->cfg0_size;
421
422 /* Find the untranslated configuration space address */
423 pp->cfg0_mod_base = of_read_number(parser.range -
424 parser.np + na, ns);
425 pp->cfg1_mod_base = pp->cfg0_mod_base +
426 pp->cfg0_size;
427 }
428 }
429
430 ret = of_pci_parse_bus_range(np, &pp->busn);
431 if (ret < 0) {
432 pp->busn.name = np->name;
433 pp->busn.start = 0;
434 pp->busn.end = 0xff;
435 pp->busn.flags = IORESOURCE_BUS;
436 dev_dbg(pp->dev, "failed to parse bus-range property: %d, using default %pR\n",
437 ret, &pp->busn);
438 }
439
440 if (!pp->dbi_base) {
441 pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start,
442 resource_size(&pp->cfg));
443 if (!pp->dbi_base) {
444 dev_err(pp->dev, "error with ioremap\n");
445 return -ENOMEM;
446 }
447 }
448
449 pp->mem_base = pp->mem.start;
450
451 if (!pp->va_cfg0_base) {
452 pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
453 pp->cfg0_size);
454 if (!pp->va_cfg0_base) {
455 dev_err(pp->dev, "error with ioremap in function\n");
456 return -ENOMEM;
457 }
458 }
459
460 if (!pp->va_cfg1_base) {
461 pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
462 pp->cfg1_size);
463 if (!pp->va_cfg1_base) {
464 dev_err(pp->dev, "error with ioremap\n");
465 return -ENOMEM;
466 }
467 }
468
469 if (of_property_read_u32(np, "num-lanes", &pp->lanes)) {
470 dev_err(pp->dev, "Failed to parse the number of lanes\n");
471 return -EINVAL;
472 }
473
474 if (IS_ENABLED(CONFIG_PCI_MSI)) {
475 if (!pp->ops->msi_host_init) {
476 pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
477 MAX_MSI_IRQS, &msi_domain_ops,
478 &dw_pcie_msi_chip);
479 if (!pp->irq_domain) {
480 dev_err(pp->dev, "irq domain init failed\n");
481 return -ENXIO;
482 }
483
484 for (i = 0; i < MAX_MSI_IRQS; i++)
485 irq_create_mapping(pp->irq_domain, i);
486 } else {
487 ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip);
488 if (ret < 0)
489 return ret;
490 }
491 }
492
493 if (pp->ops->host_init)
494 pp->ops->host_init(pp);
495
496 dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
497
498 /* program correct class for RC */
499 dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
500
501 dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
502 val |= PORT_LOGIC_SPEED_CHANGE;
503 dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
504
505 #ifdef CONFIG_PCI_MSI
506 dw_pcie_msi_chip.dev = pp->dev;
507 dw_pci.msi_ctrl = &dw_pcie_msi_chip;
508 #endif
509
510 dw_pci.nr_controllers = 1;
511 dw_pci.private_data = (void **)&pp;
512
513 pci_common_init_dev(pp->dev, &dw_pci);
514
515 return 0;
516 }
517
dw_pcie_prog_viewport_cfg0(struct pcie_port * pp,u32 busdev)518 static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev)
519 {
520 /* Program viewport 0 : OUTBOUND : CFG0 */
521 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
522 PCIE_ATU_VIEWPORT);
523 dw_pcie_writel_rc(pp, pp->cfg0_mod_base, PCIE_ATU_LOWER_BASE);
524 dw_pcie_writel_rc(pp, (pp->cfg0_mod_base >> 32), PCIE_ATU_UPPER_BASE);
525 dw_pcie_writel_rc(pp, pp->cfg0_mod_base + pp->cfg0_size - 1,
526 PCIE_ATU_LIMIT);
527 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
528 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
529 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG0, PCIE_ATU_CR1);
530 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
531 }
532
dw_pcie_prog_viewport_cfg1(struct pcie_port * pp,u32 busdev)533 static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
534 {
535 /* Program viewport 1 : OUTBOUND : CFG1 */
536 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
537 PCIE_ATU_VIEWPORT);
538 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
539 dw_pcie_writel_rc(pp, pp->cfg1_mod_base, PCIE_ATU_LOWER_BASE);
540 dw_pcie_writel_rc(pp, (pp->cfg1_mod_base >> 32), PCIE_ATU_UPPER_BASE);
541 dw_pcie_writel_rc(pp, pp->cfg1_mod_base + pp->cfg1_size - 1,
542 PCIE_ATU_LIMIT);
543 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
544 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
545 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
546 }
547
dw_pcie_prog_viewport_mem_outbound(struct pcie_port * pp)548 static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
549 {
550 /* Program viewport 0 : OUTBOUND : MEM */
551 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
552 PCIE_ATU_VIEWPORT);
553 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
554 dw_pcie_writel_rc(pp, pp->mem_mod_base, PCIE_ATU_LOWER_BASE);
555 dw_pcie_writel_rc(pp, (pp->mem_mod_base >> 32), PCIE_ATU_UPPER_BASE);
556 dw_pcie_writel_rc(pp, pp->mem_mod_base + pp->mem_size - 1,
557 PCIE_ATU_LIMIT);
558 dw_pcie_writel_rc(pp, pp->mem_bus_addr, PCIE_ATU_LOWER_TARGET);
559 dw_pcie_writel_rc(pp, upper_32_bits(pp->mem_bus_addr),
560 PCIE_ATU_UPPER_TARGET);
561 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
562 }
563
dw_pcie_prog_viewport_io_outbound(struct pcie_port * pp)564 static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
565 {
566 /* Program viewport 1 : OUTBOUND : IO */
567 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
568 PCIE_ATU_VIEWPORT);
569 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
570 dw_pcie_writel_rc(pp, pp->io_mod_base, PCIE_ATU_LOWER_BASE);
571 dw_pcie_writel_rc(pp, (pp->io_mod_base >> 32), PCIE_ATU_UPPER_BASE);
572 dw_pcie_writel_rc(pp, pp->io_mod_base + pp->io_size - 1,
573 PCIE_ATU_LIMIT);
574 dw_pcie_writel_rc(pp, pp->io_bus_addr, PCIE_ATU_LOWER_TARGET);
575 dw_pcie_writel_rc(pp, upper_32_bits(pp->io_bus_addr),
576 PCIE_ATU_UPPER_TARGET);
577 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
578 }
579
dw_pcie_rd_other_conf(struct pcie_port * pp,struct pci_bus * bus,u32 devfn,int where,int size,u32 * val)580 static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
581 u32 devfn, int where, int size, u32 *val)
582 {
583 int ret = PCIBIOS_SUCCESSFUL;
584 u32 address, busdev;
585
586 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
587 PCIE_ATU_FUNC(PCI_FUNC(devfn));
588 address = where & ~0x3;
589
590 if (bus->parent->number == pp->root_bus_nr) {
591 dw_pcie_prog_viewport_cfg0(pp, busdev);
592 ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size,
593 val);
594 dw_pcie_prog_viewport_mem_outbound(pp);
595 } else {
596 dw_pcie_prog_viewport_cfg1(pp, busdev);
597 ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size,
598 val);
599 dw_pcie_prog_viewport_io_outbound(pp);
600 }
601
602 return ret;
603 }
604
dw_pcie_wr_other_conf(struct pcie_port * pp,struct pci_bus * bus,u32 devfn,int where,int size,u32 val)605 static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
606 u32 devfn, int where, int size, u32 val)
607 {
608 int ret = PCIBIOS_SUCCESSFUL;
609 u32 address, busdev;
610
611 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
612 PCIE_ATU_FUNC(PCI_FUNC(devfn));
613 address = where & ~0x3;
614
615 if (bus->parent->number == pp->root_bus_nr) {
616 dw_pcie_prog_viewport_cfg0(pp, busdev);
617 ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size,
618 val);
619 dw_pcie_prog_viewport_mem_outbound(pp);
620 } else {
621 dw_pcie_prog_viewport_cfg1(pp, busdev);
622 ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size,
623 val);
624 dw_pcie_prog_viewport_io_outbound(pp);
625 }
626
627 return ret;
628 }
629
dw_pcie_valid_config(struct pcie_port * pp,struct pci_bus * bus,int dev)630 static int dw_pcie_valid_config(struct pcie_port *pp,
631 struct pci_bus *bus, int dev)
632 {
633 /* If there is no link, then there is no device */
634 if (bus->number != pp->root_bus_nr) {
635 if (!dw_pcie_link_up(pp))
636 return 0;
637 }
638
639 /* access only one slot on each root port */
640 if (bus->number == pp->root_bus_nr && dev > 0)
641 return 0;
642
643 /*
644 * do not read more than one device on the bus directly attached
645 * to RC's (Virtual Bridge's) DS side.
646 */
647 if (bus->primary == pp->root_bus_nr && dev > 0)
648 return 0;
649
650 return 1;
651 }
652
dw_pcie_rd_conf(struct pci_bus * bus,u32 devfn,int where,int size,u32 * val)653 static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
654 int size, u32 *val)
655 {
656 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
657 int ret;
658
659 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
660 *val = 0xffffffff;
661 return PCIBIOS_DEVICE_NOT_FOUND;
662 }
663
664 if (bus->number != pp->root_bus_nr)
665 if (pp->ops->rd_other_conf)
666 ret = pp->ops->rd_other_conf(pp, bus, devfn,
667 where, size, val);
668 else
669 ret = dw_pcie_rd_other_conf(pp, bus, devfn,
670 where, size, val);
671 else
672 ret = dw_pcie_rd_own_conf(pp, where, size, val);
673
674 return ret;
675 }
676
dw_pcie_wr_conf(struct pci_bus * bus,u32 devfn,int where,int size,u32 val)677 static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
678 int where, int size, u32 val)
679 {
680 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
681 int ret;
682
683 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
684 return PCIBIOS_DEVICE_NOT_FOUND;
685
686 if (bus->number != pp->root_bus_nr)
687 if (pp->ops->wr_other_conf)
688 ret = pp->ops->wr_other_conf(pp, bus, devfn,
689 where, size, val);
690 else
691 ret = dw_pcie_wr_other_conf(pp, bus, devfn,
692 where, size, val);
693 else
694 ret = dw_pcie_wr_own_conf(pp, where, size, val);
695
696 return ret;
697 }
698
699 static struct pci_ops dw_pcie_ops = {
700 .read = dw_pcie_rd_conf,
701 .write = dw_pcie_wr_conf,
702 };
703
dw_pcie_setup(int nr,struct pci_sys_data * sys)704 static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
705 {
706 struct pcie_port *pp;
707
708 pp = sys_to_pcie(sys);
709
710 if (global_io_offset < SZ_1M && pp->io_size > 0) {
711 sys->io_offset = global_io_offset - pp->io_bus_addr;
712 pci_ioremap_io(global_io_offset, pp->io_base);
713 global_io_offset += SZ_64K;
714 pci_add_resource_offset(&sys->resources, &pp->io,
715 sys->io_offset);
716 }
717
718 sys->mem_offset = pp->mem.start - pp->mem_bus_addr;
719 pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset);
720 pci_add_resource(&sys->resources, &pp->busn);
721
722 return 1;
723 }
724
dw_pcie_scan_bus(int nr,struct pci_sys_data * sys)725 static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys)
726 {
727 struct pci_bus *bus;
728 struct pcie_port *pp = sys_to_pcie(sys);
729
730 pp->root_bus_nr = sys->busnr;
731 bus = pci_create_root_bus(pp->dev, sys->busnr,
732 &dw_pcie_ops, sys, &sys->resources);
733 if (!bus)
734 return NULL;
735
736 pci_scan_child_bus(bus);
737
738 if (bus && pp->ops->scan_bus)
739 pp->ops->scan_bus(pp);
740
741 return bus;
742 }
743
dw_pcie_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)744 static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
745 {
746 struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);
747 int irq;
748
749 irq = of_irq_parse_and_map_pci(dev, slot, pin);
750 if (!irq)
751 irq = pp->irq;
752
753 return irq;
754 }
755
756 static struct hw_pci dw_pci = {
757 .setup = dw_pcie_setup,
758 .scan = dw_pcie_scan_bus,
759 .map_irq = dw_pcie_map_irq,
760 };
761
dw_pcie_setup_rc(struct pcie_port * pp)762 void dw_pcie_setup_rc(struct pcie_port *pp)
763 {
764 u32 val;
765 u32 membase;
766 u32 memlimit;
767
768 /* set the number of lanes */
769 dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
770 val &= ~PORT_LINK_MODE_MASK;
771 switch (pp->lanes) {
772 case 1:
773 val |= PORT_LINK_MODE_1_LANES;
774 break;
775 case 2:
776 val |= PORT_LINK_MODE_2_LANES;
777 break;
778 case 4:
779 val |= PORT_LINK_MODE_4_LANES;
780 break;
781 }
782 dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
783
784 /* set link width speed control register */
785 dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val);
786 val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
787 switch (pp->lanes) {
788 case 1:
789 val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
790 break;
791 case 2:
792 val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
793 break;
794 case 4:
795 val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
796 break;
797 }
798 dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);
799
800 /* setup RC BARs */
801 dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
802 dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1);
803
804 /* setup interrupt pins */
805 dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);
806 val &= 0xffff00ff;
807 val |= 0x00000100;
808 dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE);
809
810 /* setup bus numbers */
811 dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val);
812 val &= 0xff000000;
813 val |= 0x00010100;
814 dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
815
816 /* setup memory base, memory limit */
817 membase = ((u32)pp->mem_base & 0xfff00000) >> 16;
818 memlimit = (pp->mem_size + (u32)pp->mem_base) & 0xfff00000;
819 val = memlimit | membase;
820 dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
821
822 /* setup command register */
823 dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
824 val &= 0xffff0000;
825 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
826 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
827 dw_pcie_writel_rc(pp, val, PCI_COMMAND);
828 }
829
830 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
831 MODULE_DESCRIPTION("Designware PCIe host controller driver");
832 MODULE_LICENSE("GPL v2");
833