1/****************************************************************************** 2 * 3 * Copyright(c) 2009-2010 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26#ifndef __RTL8821AE_DM_H__ 27#define __RTL8821AE_DM_H__ 28 29#define MAIN_ANT 0 30#define AUX_ANT 1 31#define MAIN_ANT_CG_TRX 1 32#define AUX_ANT_CG_TRX 0 33#define MAIN_ANT_CGCS_RX 0 34#define AUX_ANT_CGCS_RX 1 35 36#define TXSCALE_TABLE_SIZE 37 37 38/*RF REG LIST*/ 39#define DM_REG_RF_MODE_11N 0x00 40#define DM_REG_RF_0B_11N 0x0B 41#define DM_REG_CHNBW_11N 0x18 42#define DM_REG_T_METER_11N 0x24 43#define DM_REG_RF_25_11N 0x25 44#define DM_REG_RF_26_11N 0x26 45#define DM_REG_RF_27_11N 0x27 46#define DM_REG_RF_2B_11N 0x2B 47#define DM_REG_RF_2C_11N 0x2C 48#define DM_REG_RXRF_A3_11N 0x3C 49#define DM_REG_T_METER_92D_11N 0x42 50#define DM_REG_T_METER_88E_11N 0x42 51 52/*BB REG LIST*/ 53/*PAGE 8 */ 54#define DM_REG_BB_CTRL_11N 0x800 55#define DM_REG_RF_PIN_11N 0x804 56#define DM_REG_PSD_CTRL_11N 0x808 57#define DM_REG_TX_ANT_CTRL_11N 0x80C 58#define DM_REG_BB_PWR_SAV5_11N 0x818 59#define DM_REG_CCK_RPT_FORMAT_11N 0x824 60#define DM_REG_RX_DEFUALT_A_11N 0x858 61#define DM_REG_RX_DEFUALT_B_11N 0x85A 62#define DM_REG_BB_PWR_SAV3_11N 0x85C 63#define DM_REG_ANTSEL_CTRL_11N 0x860 64#define DM_REG_RX_ANT_CTRL_11N 0x864 65#define DM_REG_PIN_CTRL_11N 0x870 66#define DM_REG_BB_PWR_SAV1_11N 0x874 67#define DM_REG_ANTSEL_PATH_11N 0x878 68#define DM_REG_BB_3WIRE_11N 0x88C 69#define DM_REG_SC_CNT_11N 0x8C4 70#define DM_REG_PSD_DATA_11N 0x8B4 71/*PAGE 9*/ 72#define DM_REG_ANT_MAPPING1_11N 0x914 73#define DM_REG_ANT_MAPPING2_11N 0x918 74/*PAGE A*/ 75#define DM_REG_CCK_ANTDIV_PARA1_11N 0xA00 76#define DM_REG_CCK_CCA_11N 0xA0A 77#define DM_REG_CCK_CCA_11AC 0xA0A 78#define DM_REG_CCK_ANTDIV_PARA2_11N 0xA0C 79#define DM_REG_CCK_ANTDIV_PARA3_11N 0xA10 80#define DM_REG_CCK_ANTDIV_PARA4_11N 0xA14 81#define DM_REG_CCK_FILTER_PARA1_11N 0xA22 82#define DM_REG_CCK_FILTER_PARA2_11N 0xA23 83#define DM_REG_CCK_FILTER_PARA3_11N 0xA24 84#define DM_REG_CCK_FILTER_PARA4_11N 0xA25 85#define DM_REG_CCK_FILTER_PARA5_11N 0xA26 86#define DM_REG_CCK_FILTER_PARA6_11N 0xA27 87#define DM_REG_CCK_FILTER_PARA7_11N 0xA28 88#define DM_REG_CCK_FILTER_PARA8_11N 0xA29 89#define DM_REG_CCK_FA_RST_11N 0xA2C 90#define DM_REG_CCK_FA_MSB_11N 0xA58 91#define DM_REG_CCK_FA_LSB_11N 0xA5C 92#define DM_REG_CCK_CCA_CNT_11N 0xA60 93#define DM_REG_BB_PWR_SAV4_11N 0xA74 94/*PAGE B */ 95#define DM_REG_LNA_SWITCH_11N 0xB2C 96#define DM_REG_PATH_SWITCH_11N 0xB30 97#define DM_REG_RSSI_CTRL_11N 0xB38 98#define DM_REG_CONFIG_ANTA_11N 0xB68 99#define DM_REG_RSSI_BT_11N 0xB9C 100/*PAGE C */ 101#define DM_REG_OFDM_FA_HOLDC_11N 0xC00 102#define DM_REG_RX_PATH_11N 0xC04 103#define DM_REG_TRMUX_11N 0xC08 104#define DM_REG_OFDM_FA_RSTC_11N 0xC0C 105#define DM_REG_RXIQI_MATRIX_11N 0xC14 106#define DM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C 107#define DM_REG_IGI_A_11N 0xC50 108#define DM_REG_IGI_A_11AC 0xC50 109#define DM_REG_ANTDIV_PARA2_11N 0xC54 110#define DM_REG_IGI_B_11N 0xC58 111#define DM_REG_IGI_B_11AC 0xE50 112#define DM_REG_ANTDIV_PARA3_11N 0xC5C 113#define DM_REG_BB_PWR_SAV2_11N 0xC70 114#define DM_REG_RX_OFF_11N 0xC7C 115#define DM_REG_TXIQK_MATRIXA_11N 0xC80 116#define DM_REG_TXIQK_MATRIXB_11N 0xC88 117#define DM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94 118#define DM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C 119#define DM_REG_RXIQK_MATRIX_LSB_11N 0xCA0 120#define DM_REG_ANTDIV_PARA1_11N 0xCA4 121#define DM_REG_OFDM_FA_TYPE1_11N 0xCF0 122/*PAGE D */ 123#define DM_REG_OFDM_FA_RSTD_11N 0xD00 124#define DM_REG_OFDM_FA_TYPE2_11N 0xDA0 125#define DM_REG_OFDM_FA_TYPE3_11N 0xDA4 126#define DM_REG_OFDM_FA_TYPE4_11N 0xDA8 127/*PAGE E */ 128#define DM_REG_TXAGC_A_6_18_11N 0xE00 129#define DM_REG_TXAGC_A_24_54_11N 0xE04 130#define DM_REG_TXAGC_A_1_MCS32_11N 0xE08 131#define DM_REG_TXAGC_A_MCS0_3_11N 0xE10 132#define DM_REG_TXAGC_A_MCS4_7_11N 0xE14 133#define DM_REG_TXAGC_A_MCS8_11_11N 0xE18 134#define DM_REG_TXAGC_A_MCS12_15_11N 0xE1C 135#define DM_REG_FPGA0_IQK_11N 0xE28 136#define DM_REG_TXIQK_TONE_A_11N 0xE30 137#define DM_REG_RXIQK_TONE_A_11N 0xE34 138#define DM_REG_TXIQK_PI_A_11N 0xE38 139#define DM_REG_RXIQK_PI_A_11N 0xE3C 140#define DM_REG_TXIQK_11N 0xE40 141#define DM_REG_RXIQK_11N 0xE44 142#define DM_REG_IQK_AGC_PTS_11N 0xE48 143#define DM_REG_IQK_AGC_RSP_11N 0xE4C 144#define DM_REG_BLUETOOTH_11N 0xE6C 145#define DM_REG_RX_WAIT_CCA_11N 0xE70 146#define DM_REG_TX_CCK_RFON_11N 0xE74 147#define DM_REG_TX_CCK_BBON_11N 0xE78 148#define DM_REG_OFDM_RFON_11N 0xE7C 149#define DM_REG_OFDM_BBON_11N 0xE80 150#define DM_REG_TX2RX_11N 0xE84 151#define DM_REG_TX2TX_11N 0xE88 152#define DM_REG_RX_CCK_11N 0xE8C 153#define DM_REG_RX_OFDM_11N 0xED0 154#define DM_REG_RX_WAIT_RIFS_11N 0xED4 155#define DM_REG_RX2RX_11N 0xED8 156#define DM_REG_STANDBY_11N 0xEDC 157#define DM_REG_SLEEP_11N 0xEE0 158#define DM_REG_PMPD_ANAEN_11N 0xEEC 159 160/*MAC REG LIST*/ 161#define DM_REG_BB_RST_11N 0x02 162#define DM_REG_ANTSEL_PIN_11N 0x4C 163#define DM_REG_EARLY_MODE_11N 0x4D0 164#define DM_REG_RSSI_MONITOR_11N 0x4FE 165#define DM_REG_EDCA_VO_11N 0x500 166#define DM_REG_EDCA_VI_11N 0x504 167#define DM_REG_EDCA_BE_11N 0x508 168#define DM_REG_EDCA_BK_11N 0x50C 169#define DM_REG_TXPAUSE_11N 0x522 170#define DM_REG_RESP_TX_11N 0x6D8 171#define DM_REG_ANT_TRAIN_PARA1_11N 0x7b0 172#define DM_REG_ANT_TRAIN_PARA2_11N 0x7b4 173 174/*DIG Related*/ 175#define DM_BIT_IGI_11N 0x0000007F 176#define DM_BIT_IGI_11AC 0xFFFFFFFF 177 178#define HAL_DM_DIG_DISABLE BIT(0) 179#define HAL_DM_HIPWR_DISABLE BIT(1) 180 181#define OFDM_TABLE_LENGTH 43 182#define CCK_TABLE_LENGTH 33 183 184#define OFDM_TABLE_SIZE 37 185#define CCK_TABLE_SIZE 33 186 187#define BW_AUTO_SWITCH_HIGH_LOW 25 188#define BW_AUTO_SWITCH_LOW_HIGH 30 189 190#define DM_DIG_FA_UPPER 0x3e 191#define DM_DIG_FA_LOWER 0x1e 192#define DM_DIG_FA_TH0 200 193#define DM_DIG_FA_TH1 0x300 194#define DM_DIG_FA_TH2 0x400 195 196#define RXPATHSELECTION_SS_TH_LOW 30 197#define RXPATHSELECTION_DIFF_TH 18 198 199#define DM_RATR_STA_INIT 0 200#define DM_RATR_STA_HIGH 1 201#define DM_RATR_STA_MIDDLE 2 202#define DM_RATR_STA_LOW 3 203 204#define CTS2SELF_THVAL 30 205#define REGC38_TH 20 206 207#define WAIOTTHVAL 25 208 209#define TXHIGHPWRLEVEL_NORMAL 0 210#define TXHIGHPWRLEVEL_LEVEL1 1 211#define TXHIGHPWRLEVEL_LEVEL2 2 212#define TXHIGHPWRLEVEL_BT1 3 213#define TXHIGHPWRLEVEL_BT2 4 214 215#define DM_TYPE_BYFW 0 216#define DM_TYPE_BYDRIVER 1 217 218#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 219#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 220#define TXPWRTRACK_MAX_IDX 6 221 222/* Dynamic ATC switch */ 223#define ATC_STATUS_OFF 0x0 /* enable */ 224#define ATC_STATUS_ON 0x1 /* disable */ 225#define CFO_THRESHOLD_XTAL 10 /* kHz */ 226#define CFO_THRESHOLD_ATC 80 /* kHz */ 227 228#define AVG_THERMAL_NUM_8812A 4 229#define TXPWR_TRACK_TABLE_SIZE 30 230#define MAX_PATH_NUM_8812A 2 231#define MAX_PATH_NUM_8821A 1 232 233enum FAT_STATE { 234 FAT_NORMAL_STATE = 0, 235 FAT_TRAINING_STATE = 1, 236}; 237 238enum tag_dynamic_init_gain_operation_type_definition { 239 DIG_TYPE_THRESH_HIGH = 0, 240 DIG_TYPE_THRESH_LOW = 1, 241 DIG_TYPE_BACKOFF = 2, 242 DIG_TYPE_RX_GAIN_MIN = 3, 243 DIG_TYPE_RX_GAIN_MAX = 4, 244 DIG_TYPE_ENABLE = 5, 245 DIG_TYPE_DISABLE = 6, 246 DIG_OP_TYPE_MAX 247}; 248 249enum dm_1r_cca_e { 250 CCA_1R = 0, 251 CCA_2R = 1, 252 CCA_MAX = 2, 253}; 254 255enum dm_rf_e { 256 RF_SAVE = 0, 257 RF_NORMAL = 1, 258 RF_MAX = 2, 259}; 260 261enum dm_sw_ant_switch_e { 262 ANS_ANTENNA_B = 1, 263 ANS_ANTENNA_A = 2, 264 ANS_ANTENNA_MAX = 3, 265}; 266 267enum pwr_track_control_method { 268 BBSWING, 269 TXAGC, 270 MIX_MODE 271}; 272 273#define BT_RSSI_STATE_NORMAL_POWER BIT_OFFSET_LEN_MASK_32(0, 1) 274#define BT_RSSI_STATE_AMDPU_OFF BIT_OFFSET_LEN_MASK_32(1, 1) 275#define BT_RSSI_STATE_SPECIAL_LOW BIT_OFFSET_LEN_MASK_32(2, 1) 276#define BT_RSSI_STATE_BG_EDCA_LOW BIT_OFFSET_LEN_MASK_32(3, 1) 277#define BT_RSSI_STATE_TXPOWER_LOW BIT_OFFSET_LEN_MASK_32(4, 1) 278#define GET_UNDECORATED_AVERAGE_RSSI(_priv) \ 279 ((((struct rtl_priv *)(_priv))->mac80211.opmode == \ 280 NL80211_IFTYPE_ADHOC) ? \ 281 (((struct rtl_priv *)(_priv))->dm.entry_min_undec_sm_pwdb) : \ 282 (((struct rtl_priv *)(_priv))->dm.undec_sm_pwdb)) 283 284void rtl8821ae_dm_set_tx_ant_by_tx_info(struct ieee80211_hw *hw, 285 u8 *pdesc, u32 mac_id); 286void rtl8821ae_dm_ant_sel_statistics(struct ieee80211_hw *hw, 287 u8 antsel_tr_mux, u32 mac_id, 288 u32 rx_pwdb_all); 289void rtl8821ae_dm_fast_antenna_training_callback(unsigned long data); 290void rtl8821ae_dm_init(struct ieee80211_hw *hw); 291void rtl8821ae_dm_watchdog(struct ieee80211_hw *hw); 292void rtl8821ae_dm_write_dig(struct ieee80211_hw *hw, u8 current_igi); 293void rtl8821ae_dm_init_edca_turbo(struct ieee80211_hw *hw); 294void rtl8821ae_dm_check_txpower_tracking_thermalmeter(struct ieee80211_hw *hw); 295void rtl8821ae_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw); 296void rtl8821ae_dm_txpower_track_adjust(struct ieee80211_hw *hw, 297 u8 type, u8 *pdirection, 298 u32 *poutwrite_val); 299void rtl8821ae_dm_clear_txpower_tracking_state(struct ieee80211_hw *hw); 300void rtl8821ae_dm_write_cck_cca_thres(struct ieee80211_hw *hw, u8 current_cca); 301void rtl8821ae_dm_initialize_txpower_tracking_thermalmeter(struct ieee80211_hw *hw); 302void rtl8812ae_dm_txpwr_track_set_pwr(struct ieee80211_hw *hw, 303 enum pwr_track_control_method method, 304 u8 rf_path, 305 u8 channel_mapped_index); 306void rtl8821ae_dm_txpwr_track_set_pwr(struct ieee80211_hw *hw, 307 enum pwr_track_control_method method, 308 u8 rf_path, u8 channel_mapped_index); 309 310void rtl8821ae_dm_update_init_rate(struct ieee80211_hw *hw, u8 rate); 311u8 rtl8821ae_hw_rate_to_mrate(struct ieee80211_hw *hw, u8 rate); 312void rtl8812ae_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw); 313void rtl8821ae_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw); 314 315#endif 316