1/****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * wlanfae <wlanfae@realtek.com> 23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 24 * Hsinchu 300, Taiwan. 25 * 26 * Larry Finger <Larry.Finger@lwfinger.net> 27 * 28 *****************************************************************************/ 29 30#ifndef __RTL8723E_DM_H__ 31#define __RTL8723E_DM_H__ 32 33#define HAL_DM_DIG_DISABLE BIT(0) 34#define HAL_DM_HIPWR_DISABLE BIT(1) 35 36#define OFDM_TABLE_LENGTH 37 37#define CCK_TABLE_LENGTH 33 38 39#define OFDM_TABLE_SIZE 37 40#define CCK_TABLE_SIZE 33 41 42#define BW_AUTO_SWITCH_HIGH_LOW 25 43#define BW_AUTO_SWITCH_LOW_HIGH 30 44 45#define DM_DIG_FA_UPPER 0x32 46#define DM_DIG_FA_LOWER 0x20 47#define DM_DIG_FA_TH0 0x20 48#define DM_DIG_FA_TH1 0x100 49#define DM_DIG_FA_TH2 0x200 50 51#define RXPATHSELECTION_SS_TH_LOW 30 52#define RXPATHSELECTION_DIFF_TH 18 53 54#define DM_RATR_STA_INIT 0 55#define DM_RATR_STA_HIGH 1 56#define DM_RATR_STA_MIDDLE 2 57#define DM_RATR_STA_LOW 3 58 59#define CTS2SELF_THVAL 30 60#define REGC38_TH 20 61 62#define WAIOTTHVAL 25 63 64#define TXHIGHPWRLEVEL_NORMAL 0 65#define TXHIGHPWRLEVEL_LEVEL1 1 66#define TXHIGHPWRLEVEL_LEVEL2 2 67#define TXHIGHPWRLEVEL_BT1 3 68#define TXHIGHPWRLEVEL_BT2 4 69 70#define DM_TYPE_BYFW 0 71#define DM_TYPE_BYDRIVER 1 72 73#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 74#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 75 76struct swat_t { 77 u8 failure_cnt; 78 u8 try_flag; 79 u8 stop_trying; 80 long pre_rssi; 81 long trying_threshold; 82 u8 cur_antenna; 83 u8 pre_antenna; 84 85}; 86 87enum tag_dynamic_init_gain_operation_type_definition { 88 DIG_TYPE_THRESH_HIGH = 0, 89 DIG_TYPE_THRESH_LOW = 1, 90 DIG_TYPE_BACKOFF = 2, 91 DIG_TYPE_RX_GAIN_MIN = 3, 92 DIG_TYPE_RX_GAIN_MAX = 4, 93 DIG_TYPE_ENABLE = 5, 94 DIG_TYPE_DISABLE = 6, 95 DIG_OP_TYPE_MAX 96}; 97 98enum dm_1r_cca_e { 99 CCA_1R = 0, 100 CCA_2R = 1, 101 CCA_MAX = 2, 102}; 103 104enum dm_rf_e { 105 RF_SAVE = 0, 106 RF_NORMAL = 1, 107 RF_MAX = 2, 108}; 109 110enum dm_sw_ant_switch_e { 111 ANS_ANTENNA_B = 1, 112 ANS_ANTENNA_A = 2, 113 ANS_ANTENNA_MAX = 3, 114}; 115 116#define BT_RSSI_STATE_NORMAL_POWER BIT_OFFSET_LEN_MASK_32(0, 1) 117#define BT_RSSI_STATE_AMDPU_OFF BIT_OFFSET_LEN_MASK_32(1, 1) 118#define BT_RSSI_STATE_SPECIAL_LOW BIT_OFFSET_LEN_MASK_32(2, 1) 119#define BT_RSSI_STATE_BG_EDCA_LOW BIT_OFFSET_LEN_MASK_32(3, 1) 120#define BT_RSSI_STATE_TXPOWER_LOW BIT_OFFSET_LEN_MASK_32(4, 1) 121#define GET_UNDECORATED_AVERAGE_RSSI(_priv) \ 122 ( \ 123 (((struct rtl_priv *)(_priv))->mac80211.opmode == \ 124 NL80211_IFTYPE_ADHOC) ? \ 125 (((struct rtl_priv *)(_priv))->dm.entry_min_undec_sm_pwdb) : \ 126 (((struct rtl_priv *)(_priv))->dm.undec_sm_pwdb) \ 127 ) 128 129void rtl8723e_dm_init(struct ieee80211_hw *hw); 130void rtl8723e_dm_watchdog(struct ieee80211_hw *hw); 131void rtl8723e_dm_write_dig(struct ieee80211_hw *hw); 132void rtl8723e_dm_check_txpower_tracking(struct ieee80211_hw *hw); 133void rtl8723e_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw); 134void rtl8723e_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal); 135void rtl8723e_dm_bt_coexist(struct ieee80211_hw *hw); 136#endif 137